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path: root/drivers/gpu/drm/i915/intel_pm.c
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* | drm/i915: HSW FBC WaFbcDisableDpfcClockGatingRodrigo Vivi2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display register 46500h bit 23 must be set to 1b for the entire time that Frame Buffer Compression is enabled. v2: Ville suggested to enable it back when disabling fbc to avoid wasting power. v3: RMW to preserve other bits (by Ville) v4: Fix from Ville: sed &/| at RMW v5: Too far on sed. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> [danvet: Insert missing space that checkpatch spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueueRodrigo Vivi2013-05-10
| | | | | | | | | | | | | | | | | | Display register 420B0h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Enable FBC at Haswell.Rodrigo Vivi2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduce Frame Buffer Compression (FBC) support for HSW. FBC is tied to primary plane A in HSW. v2: Ville pointed out docs say FBC must be disabled before disabling the plane on HSW. v3: Really enabling it by default at HSW. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: IVB FBC WaFbcDisableDpfcClockGatingRodrigo Vivi2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Display register 42020h bit 9 must be set to 1b for the entire time that Frame Buffer Compression is enabled. v2: RMW to preserve other bits (by Ville) v3: Fix from Ville: sed &/| at RMW v4: Too far on sed. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueueRodrigo Vivi2013-05-10
| | | | | | | | | | | | | | | | | | Display register 42000h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Add support for FBC on Ivybridge.Rodrigo Vivi2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduce Frame Buffer Compression (FBC) support for IVB, without enabling it by default. It adds a new function gen7_enable_fbc to avoid getting ironlake_enable_fbc messed with many IS_IVYBRIDGE checks. v2: Fixes from Ville. * Fix Plane. FBC is tied to primary plane A in HSW * Fix DPFC initial write to avoid let trash on the register. v3: Checking for bad plane on intel_update_fbc() as Chris suggested. v4: Ville pointed out that according to BSpec FBC_CTL bits 0:3 must be 0. v5: Up to v4 this work was entirely focused on Haswell. However Ville noticed I could reuse the FBC work done for HSW and get FBC for free at Ivybridge. So it makes more sense enable FBC for IVB first. FBC for HSW comming on next patches. We are just not enabling it by default on IVB. v6: Fix confused commit name (by Matt Turner). v7: Remove gtt_offset shift since it is page aligned byte offset (by Ville). Cc: Matt Turner <mattst88@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Organize VBT stuff inside drm_i915_privateRodrigo Vivi2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | drm_i915_private is getting bigger and bigger when adding new vbt stuff. So, the better way of getting drm_i915_private organized is to create a special structure for vbt stuff. v2: Basically conflicts fixes Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: allow stolen, pre-allocated objects to avoid GTT allocation v2Jesse Barnes2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | In some cases, we may not need GTT address space allocated to a stolen object, so allow passing -1 to the preallocated function to indicate as much. v2: remove BUG_ON(gtt_offset & 4095) now that -1 is allowed (Ville) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: BIOS and power context stolen mem handling for VLV v7Jesse Barnes2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | But we need to get the right stolen base and make pre-allocated objects for BIOS stuff so we don't clobber it. If the BIOS hasn't allocated a power context, we allocate one here too, from stolen space as required by the docs. v2: fix stolen to phys if ladder (Ben) keep BIOS reserved space out of allocator altogether (Ben) v3: fix mask of stolen base (Ben) v4: clean up preallocated object on unload (Ben) don't zero reg on unload (Jesse) fix mask harder (Jesse) v5: use unref for freeing stolen bits (Chris) move alloc/free to intel_pm.c (Chris) v6: NULL pctx at disable time so error paths work (Ben) v7: use correct PCI device for config read (Jesse) Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Re-enable FBC WM if the watermark is good on gen6+Ville Syrjälä2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | If the calculated FBC watermark is no good, we simply disable FBC watermarks. But we fail to re-enable them later if the calculated watermark becomes good again. Fix that, but remember to leave FBC watermarks disabled on ILK since that's required by some workarounds. v2: Fix checkpatch complaint Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: HSW: allow PCH clock gating for suspendImre Deak2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | For the device to enter D3 we should enable PCH clock gating. v2: - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo) - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Add references to some workaround we implementDamien Lespiau2013-05-10
| | | | | | | | | | | | | | | | | | We did not mention the workaround name when implementing those. This should help us track what we already implement. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Add platform information to implemented workaroundsDamien Lespiau2013-05-10
| | | | | | | | | | | | Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: add intel_display_power_enabledPaulo Zanoni2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should replace intel_using_power_well. The idea is that we're adding the requested power domain as an argument, so this might enable the code to look less platform-specific and also allows us to easily add new domains in case we need. v2: Add more domains to enum intel_display_power_domain v3: Even more domains requested Requested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: go back to switch for VLV mem freq detection v2Jesse Barnes2013-05-10
| | | | | | | | | | | | | | | | | | Both the docs and the existing code were wrong. So fix both and use a switch statement like we do elsewhere to make things simple & clear. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Only print the info message about incresing stolen size for FBC onceChris Wilson2013-04-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of repeatedly bombarding the user with a request to reboot and increase the stolen size with every fb refresh, just inform them the first time only. v2: Rearrange code so the hint to increase the amount of memory stolen by the BIOS is only emitted if we fail to find sufficient stolen memory for FBC. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Fixup formatting code mismatch that gcc spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: disable interrupts earlier in the driver unload codeDaniel Vetter2013-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our rps code relies on the interrupts being off to prevent re-arming of the work items at inopportune moments. Also drop the redundant cancel_work for the main rps work, disable_gt_powersave already takes care of that. Finally add a WARN_ON to ensure we obey that piece of ordering constraint. Long term I want to lock down the setup/teardown code in a similar way to how we painstakingly check modeset sequence constraints already. v2: Disable polling after hpd handling is shut down - since Egbert's hpd irq storm handling the hotplug work can re-arm the polling handler. Spotted by Jani Nikula. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: create spearate VLV disable_rps functionJesse Barnes2013-04-24
| | | | | | | | | | | | | | | | | | | | We don't want to write reserved regs here, and may want to do other bits in the future, so split it out. Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: cancel RPS work before disabling RPSJesse Barnes2013-04-24
| | | | | | | | | | | | | | | | | | | | | | Ville noticed this while doing another review; we may as well cancel this work just to make sure we don't try anything fancy after disabling the RPS interfaces. Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: make sure GPU freq drops to minimum after entering RC6 v4Jesse Barnes2013-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On VLV, the Punit doesn't automatically drop the GPU to it's minimum voltage level when entering RC6, so we arm a timer to do it for us from the RPS interrupt handler. It'll generally only fire when we go idle (or if for some reason there's a long delay between RPS interrupts), but won't be re-armed again until the next RPS event, so shouldn't affect power consumption after we go idle and it triggers. v2: use delayed work instead of timer + work queue combo (Ville) v3: fix up delayed work cancel (must be outside lock) (Daniel) fix up delayed work handling func for delayed work (Jesse) v4: cancel delayed work before RPS shutdown (Jani) pass delay not absolute time to mod_delayed_work (Jani) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: turbo & RC6 support for VLV v7Jesse Barnes2013-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Uses slightly different interfaces than other platforms. v2: track actual set freq, not requested (Rohit) fix debug prints in init code (Jesse) v3: don't write sleep reg (Jesse) re-add RC6 wake limit write (Ben) fixup thresholds to match other platforms (Ben) clean up mem freq calculation (Ben) clean up debug prints (Ben) v4: move defines from punit patch (Ville) v5: remove writes to nonexistent regs (Jesse) put RP and RC regs together (Jesse) fix RC6 enable (Jesse) v6: use correct fuse reads from NC (Jesse) split out min/max funcs for use in sysfs (Jesse) add debugfs & sysfs freq controls (Jesse) v7: update with Ben's hw_max changes (Jesse) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v6) [danvet: Follow checkpatch sugggestion to use min_t to avoid casting fun.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: VLV GPU frequency to opcode functionsJesse Barnes2013-04-18
| | | | | | | | | | | | | | | | | | | | When requesting frequency changes or querying status from the Punit, we need to use an opcode that corresponds to the frequency, taking into account the memory frequency. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Print plane, pipe, port names as alphabetical insted of decimalVille Syrjälä2013-04-18
|/ | | | | | | | Alway use the alphabetical names in debug/error messages for planes, pipes and ports, instead of using decimal numbers occasionally. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: preserve the PBC bits of TRANS_CHICKEN2Paulo Zanoni2013-04-18
| | | | | | | | | | | Bits 30 and 24:0 are PBC, so don't zero them. Some of the other bits are being zeroed, but I couldn't find a reason for this, so leave them as they are for now to avoid regressions. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> [danvet: Delete the redudant #define that Imre spotted in his review.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: set CPT FDI RX polarity bits based on VBTPaulo Zanoni2013-04-18
| | | | | | | | | | | | | | | Check the VBT to see if the machine has inverted FDI RX polarity on CPT. Based on this bit, set the appropriate bit on the TRANS_CHICKEN2 registers. This should fix some machines that were showing black screens on all outputs. Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60029 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: remove comment about IVB link training from intel_pm.cPaulo Zanoni2013-04-18
| | | | | | | | | We have the exact same comment inside intel_init_display. This is a leftover from when we moved a lot of code from intel_display.c to intel_pm.c. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Scale ring, rather than ia, frequency on HaswellChris Wilson2013-04-18
| | | | | | | | | | | | | | | | | | Haswell introduces a separate frequency domain for the ring (uncore). So where we used to increase the CPU (IA) clock with GPU busyness, we now need to scale the ring frequency directly instead. As the ring limits our memory bandwidth, it is vital for performance that when the GPU is busy, we increase the frequency of the ring to increase the available memory bandwidth. v2: Fix the algorithm to actually use the scaled gpu frequency for the ring. v3: s/max_ring_freq/min_ring_freq/ as that is what it is Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Add space checkpatch complained about.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: add intel_using_power_wellPaulo Zanoni2013-04-18
| | | | | | | | | | It returns true if we've requested to turn the power well on and it's really on. It also returns true for all the previous gens. For now there's just one caller, but I'm going to add more. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Don't default to overclock maxBen Widawsky2013-04-18
| | | | | | | Requested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Better overclock supportBen Widawsky2013-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most importantly this will allow users to set overclock frequencies in sysfs. Previously the max was limited by the RP0 max as opposed to the overclock max. This is useful if one wants to either limit the max overclock frequency, or set the minimum frequency to be in the overclock range. It also fixes an issue where if one sets the max frequency to be below the overclock max, they wouldn't be able to set back the proper overclock max. In addition I've added a couple of other bits: Show the overclock freq. as max in sysfs Print the overclock max in debugfs. Print a warning if the user sets the min frequency to be in the overclock range. In this patch I've decided to store the hw_max when we read it from the pcode at init. The reason I do this is the pcode reads can fail, and are slow. v2: Report when user requested overclocked max (Daniel) Remove when user sets min to overclock range (Daniel) Reported-by: freezer from #intel-gfx on irc Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> [danvet: Fixup the s/100MHz/50MHz/ confusion in an unrelated comment that Mika spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Don't touch South Display when PCH_NOPBen Widawsky2013-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interrupts, clock gating, LVDS, and GMBUS are all within the, "this will be bad for CPU" range when we have PCH_NOP. There is a bit of a hack in init clock gating. We want to do most of the clock gating, but the part we skip will hang the system. It could probably be abstracted a bit better, but I don't feel it's too unsightly. v2: Use inverse HAS_PCH_NOP check (Jani) v3: Actually do what I claimed in v2 (spotted by Daniel) Merge Ivybridge IRQ handler PCH check to decrease whitespace (Daniel) Move LVDS bail into this patch (Ben) v4: logical rebase conflict resolution with SDEIIR (Ben) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Brush up patch a bit and resolve conflicts: - Adjust PCH_NOP checks due to Egbert's hpd handling rework. - Addd a PCH_NOP check in the irq uninstall code. - Resolve conflicts with Paulo's SDE irq handling race fix. v5: Drop the added hunks in the ilk irq handler again, they're bogus. OOps. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* Merge tag 'v3.9-rc5' into drm-intel-next-queuedDaniel Vetter2013-04-03
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backmerge Linux 3.9-rc5 since I want to merge a few dp clock cleanups for -next, but they will conflict all over the place with commit 9d1a455b0ca1c2c956b4d9ab212864a8695270f1 Author: Takashi Iwai <tiwai@suse.de> Date: Mon Mar 18 11:25:36 2013 +0100 drm/i915: Use the fixed pixel clock for eDP in intel_dp_set_m_n() from -fixes. Conflicts: drivers/gpu/drm/i915/intel_dp.c: Simply adjacent lines changed. drivers/gpu/drm/i915/intel_panel.c: A field rename in -next conflicts with a bugfix in -fixes. Take the version from -fixes and apply the rename. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: don't disable the power well yetPaulo Zanoni2013-03-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're still not 100% ready to disable the power well, so don't disable it for now. When we disable it we break the audio driver (because some of the audio registers are on the power well) and machines with eDP on port D (because it doesn't use TRANSCODER_EDP). Also, instead of just reverting the code, add a Kernel option to let us disable it if we want. This will allow us to keep developing and testing the feature while it's not enabled. This fixes problems caused by the following commit: commit d6dd9eb1d96d2b7345fe4664066c2b7ed86da898 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Tue Jan 29 16:35:20 2013 -0200 drm/i915: dynamic Haswell display power well support References: http://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg18788.html Cc: Takashi Iwai <tiwai@suse.de> Cc: Mengdong Lin <mengdong.lin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: drop DPFLIPSTAT enables on VLV v3Jesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | We don't need this until we start using the wait event commands. v2: move to i915_irq.c (Jesse) drop unneeded sprite flip done enables (Ville) v3: drop the DPFLIPSTAT enables altogether (Ville) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: add Punit read/write routines for VLV v2Jesse Barnes2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Slightly different than other platforms. v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine. v3: drop turbo defines from this patch (Ville) use PCI_DEVFN(2,0) instead of open coding (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com> [danvet: Add checkpatch bikeshed about missing space.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: HSW PM Frequency bits fixRodrigo Vivi2013-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to HSW PM programming guide, frequency bits starts at 24 instead of 25. v2: Paulo Zanoni noticed that only frequency bits can be set at GEN6_RPNSWREQ. All others are read only. CC: Ben Widawsky <ben@bwidawsk.net> CC: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Don't overclock on HaswellBen Widawsky2013-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | HSW doesn't overclock the same way as IVB or SNB. I do not know about VLV, so I've kept that off as well. I'm still working on getting the doc updates to explain how we overclock on Haswell. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Add missing () spotted by Wu Fengguang's kernel build robot. Acked by Ben.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Implement WaSwitchSolVfFArbitrationPriorityBen Widawsky2013-03-23
| | | | | | | | | | | | | | | | Bspec mentions this for HSW+. I can't quite tell what the effects are, and I don't easily have a way to test this. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Correct sandybrige overclockingBen Widawsky2013-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the gen6+ max delay if the pcode read was successful (not the inverse). The previous code was all sorts of wrong and has existed since I broke it: commit 42c0526c930523425ff6edc95b7235ce7ab9308d Author: Ben Widawsky <ben@bwidawsk.net> Date: Wed Sep 26 10:34:00 2012 -0700 drm/i915: Extract PCU communication I added some parentheses for clarity, and I also corrected the debug message message to use the mask (wrong before I came along) and added a print to show the value we're changing from. Looking over the code, I'm not actually sure what we're trying to do. I introduced the bug simply by extracting the function not implementing anything new. We already set max_delay based on the capabilities register (which is what we use elsewhere to determine min and max). This would potentially increase it, I suppose? Jesse, I can't find the document which explains the definitions of the pcode commands, maybe you have it around. Based on Jesse's response, this could potentially be for -fixes, or stable, or maybe lead to us dropping it entirely. As the current code is is, things won't completely break because of the aforementioned capabilities register, and in my experimentation, enabling this has no effect, it goes from 1100->1100. I found this while reviewing Jesse's VLV patches. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Bikeshed-away the redudant parens spotted by Chris Wilson.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: set conservative clock gating values on VLV v2Jesse Barnes2013-03-23
| | | | | | | | | | | | | | | | | | We'll re-enable select bits as needed after testing and power measurement. v2: split out wake handling bits (Jani) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: fix WaDisablePSDDualDispatchEnable on VLV v2Jesse Barnes2013-03-23
| | | | | | | | | | | | | | | | | | | | Can prevent a hang when we get to tessellation. We need to set bit 15 as well for this workaround. v2: update changelog with accurate info Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: add media well to VLV force wake routines v2Jesse Barnes2013-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We could split this out into a separate routine at some point as an optimization. v2: use FORCEWAKE_KERNEL (Ville) Note: Ville mentioned in his review that he declines to be responsible if this blows up due to the lack of "readback a register != FW_ACK, but from the same cacheline" magic we have in other forcewake implementations. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Bikeshed overtly long lines according to checkpatch.pl. Nope, this time around I didn't screw up printk message since I've left those alone.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | Merge tag 'v3.9-rc3' into drm-intel-next-queuedDaniel Vetter2013-03-19
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backmerge so that I can merge Imre Deak's coalesced sg entries fixes, which depend upon the new for_each_sg_page introduce in commit a321e91b6d73ed011ffceed384c40d2785cf723b Author: Imre Deak <imre.deak@intel.com> Date: Wed Feb 27 17:02:56 2013 -0800 lib/scatterlist: add simple page iterator The merge itself is just two trivial conflicts: Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Increase the RC6p threshold.Stéphane Marchesin2013-03-05
| | | | | | | | | | | | | | | | | | | | This increases GEN6_RC6p_THRESHOLD from 100000 to 150000. For some reason this avoids the gen6_gt_check_fifodbg.isra warnings and associated GPU lockups, which makes my ivy bridge machine stable. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: add HAS_POWER_WELLPaulo Zanoni2013-03-17
| | | | | | | | | | | | | | | | | | | | | | We're starting to add many IS_HASWELL checks for the power well code, so add a HAS_POWER_WELL macro to properly document that we're checking for hardware that has the power down well. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Resolve conflicts since some converted code was added by not-yet merged patches.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: reduce power in the ilk rc6 enable error messageJani Nikula2013-03-13
| | | | | | | | | | | | | | Even if "power power" is good for grepping. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Single thread force wake isn't used on HSW anymoreVille Syrjälä2013-03-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kill the HSW check from the single thread force wake code. HSW uses MT force wake exclusively these days. The commit that removed HSW single thread forcewake support: commit 36ec8f877481449bdfa072e6adf2060869e2b970 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Oct 18 14:44:35 2012 +0200 drm/i915: unconditionally use mt forcewake on hsw/ivb Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Use '1' instead of FORCEWAKE_KERNEL for ST force wakeVille Syrjälä2013-03-03
| | | | | | | | | | | | | | | | | | | | Use the number '1' instead of FORCEWAKE_KERNEL when requesting single thread force wake since there is only one bit in the register. Using the FORCEWAKE_KERNEL name might give someone the wrong impression. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Use FORCEWAKE_KERNEL instead of hardcoded number in MT forcewake ACKVille Syrjälä2013-03-03
|/ | | | | | | | | | The MT forcewake ACK register also has a corresponding bit to each of the bits in the MT forcewake register. Use the define we have for the bit we care about instead of a hardcoded number. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: remove bogus mutex_unlock from error-pathDaniel Vetter2013-02-19
| | | | | | | | | | | | | | This has been lost in the locking rework for intel_alloc_context_page: commit 2c34b850ee1e9f86b41706149d0954eee58757a3 Author: Ben Widawsky <ben@bwidawsk.net> Date: Sat Mar 19 18:14:26 2011 -0700 drm/i915: fix ilk rc6 teardown locking Cc: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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