aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/fpga/zynq-fpga.c
Commit message (Expand)AuthorAge
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285Thomas Gleixner2019-06-05
* zynq-fpga: Only route PR via PCAP when requiredMike Looijmans2018-11-11
* fpga: mgr: add devm_fpga_mgr_createAlan Tull2018-10-16
* fpga: manager: change api, don't use drvdataAlan Tull2018-05-25
* fpga: zynq: Add support for encrypted bitstreamsMoritz Fischer2017-03-17
* fpga zynq: Use the scatterlist interfaceJason Gunthorpe2017-02-10
* fpga zynq: Check the bitstream for validityJason Gunthorpe2017-02-10
* fpga zynq: Check for errors after completing DMAJason Gunthorpe2017-02-10
* fpga zynq: Fix incorrect ISR state on bootupJason Gunthorpe2016-11-29
* fpga zynq: Remove priv->devJason Gunthorpe2016-11-29
* fpga zynq: Add missing \n to messagesJason Gunthorpe2016-11-29
* fpga-mgr: add fpga image information structAlan Tull2016-11-10
* fpga: zynq-fpga: Fix issue with drvdata being overwritten.Moritz Fischer2015-10-23
* fpga: zynq-fpga: Change fw format to handle bin instead of bit.Moritz Fischer2015-10-23
* fpga: zynq-fpga: Fix unbalanced clock handlingMoritz Fischer2015-10-23
* fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000Moritz Fischer2015-10-18
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 09:18:20 -0400