Commit message (Expand) | Author | Age | |
---|---|---|---|
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner | 2019-05-30 |
* | clk: tegra: dfll: CVB calculation alignment with the regulator | Joseph Lo | 2019-02-06 |
* | clk: tegra: dfll: improve function-level documentation | Julia Lawall | 2016-11-01 |
* | clk: tegra: dfll: Properly clean up on failure and removal | Thierry Reding | 2016-04-28 |
* | clk: tegra: dfll: Make code more comprehensible | Thierry Reding | 2016-04-28 |
* | clk: tegra: Unlock top rates for Tegra124 DFLL clock | Mikko Perttunen | 2015-09-15 |
* | clk: tegra: Add functions for parsing CVB tables | Tuomas Tynkkynen | 2015-07-16 |