| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner | 2019-05-30 |
| * | clk: tegra: dfll: CVB calculation alignment with the regulator | Joseph Lo | 2019-02-06 |
| * | clk: tegra: dfll: Fix drvdata overwriting issue | Nicolin Chen | 2017-11-01 |
| * | clk: tegra: dfll: Properly clean up on failure and removal | Thierry Reding | 2016-04-28 |
| * | clk: tegra: dfll: Reference CVB table instead of copying data | Thierry Reding | 2016-04-28 |
| * | clk: tegra: dfll: Update kerneldoc | Thierry Reding | 2016-04-28 |
| * | clk: tegra: Add Tegra124 DFLL clocksource platform driver | Tuomas Tynkkynen | 2015-07-16 |
| * | clk: tegra: Add library for the DFLL clock source (open-loop mode) | Tuomas Tynkkynen | 2015-07-16 |
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index : litmus-rt-ext-res.git | |
| LITMUS^RT with extended reservations for Forbidden Zones paper @ RTAS'20 | Zelin Tong |
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