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path: root/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
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* clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clockChen-Yu Tsai2017-03-30
* clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai2016-11-21
* clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parentChen-Yu Tsai2016-10-19
* clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clkChen-Yu Tsai2016-09-16
* clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLsChen-Yu Tsai2016-09-16
* clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocksChen-Yu Tsai2016-09-16
* clk: sunxi-ng: Add A31/A31s clocksChen-Yu Tsai2016-08-25