aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/renesas/rcar-gen3-cpg.h
Commit message (Expand)AuthorAge
* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-18
|\
| * clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHISergei Shtylyov2018-09-03
| * clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven2018-08-27
| * clk: renesas: rcar-gen3: Add support for RCKSEL clock selectionGeert Uytterhoeven2018-08-27
| * clk: renesas: rcar-gen3: Add support for OSC EXTAL predividerGeert Uytterhoeven2018-08-27
* | clk: renesas: Convert to SPDX identifiersKuninori Morimoto2018-09-28
|/
* clk: renesas: rcar-gen3: Add Z2 clock divider supportTakeshi Kihara2018-02-12
* clk: renesas: rcar-gen3: Add Z clock divider supportTakeshi Kihara2018-02-12
* clk: renesas: cpg-mssr: Add support to restore core clocks during resumeGeert Uytterhoeven2017-10-20
* clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven2017-08-16
* clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven2017-08-16
* clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven2017-03-21
* clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()Geert Uytterhoeven2016-11-02
* clk: renesas: cpg-mssr: Extract common R-Car Gen3 support codeGeert Uytterhoeven2016-06-06
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 23:07:07 -0400