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path: root/drivers/clk/renesas/r8a774a1-cpg-mssr.c
Commit message (Expand)AuthorAge
* clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara2019-04-02
* clk: renesas: rcar-gen3: Correct parent clock of SYS-DMACTakeshi Kihara2019-04-02
* clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi2019-04-02
* clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi2019-04-02
* clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman2019-04-02
* clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman2019-04-02
* clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara2019-04-02
* clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLKFabrizio Castro2019-02-25
* clk: renesas: r8a774a1: Add missing CANFD clockFabrizio Castro2019-01-21
* clk: renesas: r8a774a1: Add CPEX clockGeert Uytterhoeven2018-12-04
* clk: renesas: cpg-mssr: Add r8a774a1 supportBiju Das2018-08-27