| Commit message (Expand) | Author | Age |
* | perf/x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32() | Peter Zijlstra | 2017-04-21 |
* | perf/x86/intel: Remove an inconsistent NULL check | Dan Carpenter | 2016-10-16 |
* | perf/x86/intel: Clean up LBR state tracking | Peter Zijlstra | 2016-08-10 |
* | perf/x86/intel: Remove redundant test from intel_pmu_lbr_add() | Peter Zijlstra | 2016-08-10 |
* | perf/x86/intel: Eliminate dead code in intel_pmu_lbr_del() | Peter Zijlstra | 2016-08-10 |
* | perf/x86: Ensure perf_sched_cb_{inc,dec}() is only called from pmu::{add,del}() | Peter Zijlstra | 2016-08-10 |
* | perf/x86/intel: Fix rdlbr_to() MSR reading typo | Peter Zijlstra | 2016-07-07 |
* | perf/x86/intel: Add {rd,wr}lbr_{to,from} wrappers | Peter Zijlstra | 2016-06-27 |
* | perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switch | David Carrillo-Cisneros | 2016-06-27 |
* | perf/x86/intel: Fix trivial formatting and style bug | David Carrillo-Cisneros | 2016-06-27 |
* | perf/x86/intel: Fix MSR_LAST_BRANCH_FROM_x bug when no TSX | David Carrillo-Cisneros | 2016-06-27 |
* | perf/x86/intel: Print LBR support statement after validation | David Carrillo-Cisneros | 2016-06-27 |
* | Merge branch 'perf/urgent' into perf/core, to resolve conflict | Ingo Molnar | 2016-04-28 |
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| * | perf/x86/intel: Fix incorrect lbr_sel_mask value | Kan Liang | 2016-04-28 |
* | | perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUs | Kan Liang | 2016-04-23 |
* | | perf/x86/intel: Add Goldmont CPU support | Kan Liang | 2016-04-23 |
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* | Merge branch 'x86/cleanups' into x86/urgent | Ingo Molnar | 2016-03-17 |
* | perf/x86: Move perf_event.h to its new home | Borislav Petkov | 2016-02-17 |
* | perf/x86: Move perf_event_intel_lbr.c ........ => x86/events/intel/lbr.c | Borislav Petkov | 2016-02-17 |