aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm64/include/asm/cache.h
Commit message (Expand)AuthorAge
* arm64: cpufeature: Fix handling of CTR_EL0.IDC fieldSuzuki K Poulose2018-10-16
* arm64: Fix mismatched cache line size detectionSuzuki K Poulose2018-07-05
* arm64: Increase ARCH_DMA_MINALIGN to 128Catalin Marinas2018-05-15
* Revert "arm64: Increase the max granular size"Catalin Marinas2018-05-11
* Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)"Will Deacon2018-03-27
* arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDCShanker Donthineni2018-03-09
* arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)Catalin Marinas2018-03-06
* arm64: cache: Identify VPIPT I-cachesWill Deacon2017-03-20
* arm64: cache: Merge cachetype.h into cache.hWill Deacon2017-03-20
* arm64: Increase the max granular sizeTirumalesh Chalamarla2015-10-28
* arm64: Implement support for read-mostly sectionsJungseok Lee2014-12-03
* arm64: Implement cache_line_size() based on CTR_EL0.CWGCatalin Marinas2014-05-09
* arm64: Cache maintenance routinesCatalin Marinas2012-09-17
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-24 13:43:26 -0400