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* irqchip/gic-v3-its: Allow GIC ITS number more than MAX_NUMNODESHanjun Guo2017-08-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling ITS NUMA support on D05, I got the boot log: [ 0.000000] SRAT: PXM 0 -> ITS 0 -> Node 0 [ 0.000000] SRAT: PXM 0 -> ITS 1 -> Node 0 [ 0.000000] SRAT: PXM 0 -> ITS 2 -> Node 0 [ 0.000000] SRAT: PXM 1 -> ITS 3 -> Node 1 [ 0.000000] SRAT: ITS affinity exceeding max count[4] This is wrong on D05 as we have 8 ITSs with 4 NUMA nodes. So dynamically alloc the memory needed instead of using its_srat_maps[MAX_NUMNODES], which count the number of ITS entry(ies) in SRAT and alloc its_srat_maps as needed, then build the mapping of numa node to ITS ID. Of course, its_srat_maps will be freed after ITS probing because we don't need that after boot. After doing this, I got what I wanted: [ 0.000000] SRAT: PXM 0 -> ITS 0 -> Node 0 [ 0.000000] SRAT: PXM 0 -> ITS 1 -> Node 0 [ 0.000000] SRAT: PXM 0 -> ITS 2 -> Node 0 [ 0.000000] SRAT: PXM 1 -> ITS 3 -> Node 1 [ 0.000000] SRAT: PXM 2 -> ITS 4 -> Node 2 [ 0.000000] SRAT: PXM 2 -> ITS 5 -> Node 2 [ 0.000000] SRAT: PXM 2 -> ITS 6 -> Node 2 [ 0.000000] SRAT: PXM 3 -> ITS 7 -> Node 3 Fixes: dbd2b8267233 ("irqchip/gic-v3-its: Add ACPI NUMA node mapping") Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: John Garry <john.garry@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip: brcmstb-l2: Define an irq_pm_shutdown functionFlorian Fainelli2017-08-07
| | | | | | | | | | | | | The Broadcom STB platforms support S5 and we allow specific hardware wake-up events to take us out of this state. Because we were not defining an irq_pm_shutdown() function pointer, we would not be correctly masking non-wakeup events, which would result in spurious wake-ups from sources that were not explicitly configured for wake-up. Fixes: 7f646e92766e ("irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller") Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic: Ensure we have an ISB between ack and ->handle_irqWill Deacon2017-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devices that expose their interrupt status registers via system registers (e.g. Statistical profiling, CPU PMU, DynamIQ PMU, arch timer, vgic (although unused by Linux), ...) rely on a context synchronising operation on the CPU to ensure that the updated status register is visible to the CPU when handling the interrupt. This usually happens as a result of taking the IRQ exception in the first place, but there are two race scenarios where this isn't the case. For example, let's say we have two peripherals (X and Y), where Y uses a system register for its interrupt status. Case 1: 1. CPU takes an IRQ exception as a result of X raising an interrupt 2. Y then raises its interrupt line, but the update to its system register is not yet visible to the CPU 3. The GIC decides to expose Y's interrupt number first in the Ack register 4. The CPU runs the IRQ handler for Y, but the status register is stale Case 2: 1. CPU takes an IRQ exception as a result of X raising an interrupt 2. CPU reads the interrupt number for X from the Ack register and runs its IRQ handler 3. Y raises its interrupt line and the Ack register is updated, but again, the update to its system register is not yet visible to the CPU. 4. Since the GIC drivers poll the Ack register, we read Y's interrupt number and run its handler without a context synchronisation operation, therefore seeing the stale register value. In either case, we run the risk of missing an IRQ. This patch solves the problem by ensuring that we execute an ISB in the GIC drivers prior to invoking the interrupt handler. This is already the case for GICv3 and EOIMode 1 (the usual case for the host). Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3-its: Remove ACPICA version check for ACPI NUMARobert Richter2017-08-02
| | | | | | | | | | | | The version check was added due to dependency to a618c7f89a02 ACPICA: Add support for new SRAT subtable Now, that this code is in the kernel, remove the check. This is esp. useful to enable backports. Signed-off-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3: Honor forced affinity settingSuzuki K Poulose2017-07-04
| | | | | | | | | | | Honor the 'force' flag for set_affinity, by selecting a CPU from the given mask (which may not be reported "online" by the cpu_online_mask). Some drivers, like ARM PMU, rely on it. Cc: Marc Zyngier <marc.zyngier@arm.com> Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3: Report failures in gic_irq_domain_allocSuzuki K Poulose2017-07-04
| | | | | | | | | | | | If the GIC cannot map an IRQ via irq_domain_ops->alloc(), it doesn't return an error code. This can cause a problem with drivers, where it thinks it has successfully got an IRQ for the device, but requesting the same ends up failure with -ENOSYS (as the IRQ's chip is not set). Fixes: commit 443acc4f37f6 ("irqchip: GICv3: Convert to domain hierarchy") Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v2: Report failures in gic_irq_domain_allocSuzuki K Poulose2017-07-04
| | | | | | | | | | | | | If the GIC cannot map an IRQ via irq_domain_ops->alloc(), it doesn't return an error code. This can cause a problem with drivers, where it thinks it has successfully got an IRQ for the device, but requesting the same ends up failure with -ENOSYS (as the IRQ's chip is not set). Fixes: commit 9a1091ef0017c ("irqchip: gic: Support hierarchy irq domain.") Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/atmel-aic: Remove root argument from ->fixup() prototypeBoris Brezillon2017-07-04
| | | | | | | | We are no longer using the root argument passed to the ->fixup() hooks. Remove it. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/atmel-aic: Fix unbalanced refcount in aic_common_rtc_irq_fixup()Boris Brezillon2017-07-04
| | | | | | | | | | | | | | | of_find_compatible_node() is calling of_node_put() on its first argument thus leading to an unbalanced of_node_get/put() issue if the node has not been retained before that. Instead of passing the root node, pass NULL, which does exactly the same: iterate over all DT nodes, starting from the root node. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Fixes: 3d61467f9bab ("irqchip: atmel-aic: Implement RTC irq fixup") Cc: <stable@vger.kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/atmel-aic: Fix unbalanced of_node_put() in aic_common_irq_fixup()Boris Brezillon2017-07-04
| | | | | | | | | | | aic_common_irq_fixup() is calling twice of_node_put() on the same node thus leading to an unbalanced refcount on the root node. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Fixes: b2f579b58e93 ("irqchip: atmel-aic: Add irq fixup infrastructure") Cc: <stable@vger.kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/or1k-pic: Fix interrupt acknowledgementPedro H. Penna2017-06-30
| | | | | | | | | | | | | | Usually, hardware implicitly acknowledges interrupts when reading them. However, if this is not the case, the IRQ gets fired over and over again in the current implementation. This patch uses the right mask acknowledge function to handle the aforementioned situation on or1k processors that interact with such kind of hardware. Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Pedro H. Penna <pedrohenriquepenna@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-mvebu-gicp: Allocate enough memory for spi_bitmapDan Carpenter2017-06-30
| | | | | | | | | | BITS_TO_LONGS() gives us the number of longs we need, but we want to allocate the number of bytes. Fixes: a68a63cb4dfc ("irqchip/irq-mvebu-gicp: Add new driver for Marvell GICP") Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3: Fix out-of-bound access in gic_set_affinitySuzuki K Poulose2017-06-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv3 driver doesn't check if the target CPU for gic_set_affinity is valid before going ahead and making the changes. This triggers the following splat with KASAN: [ 141.189434] BUG: KASAN: global-out-of-bounds in gic_set_affinity+0x8c/0x140 [ 141.189704] Read of size 8 at addr ffff200009741d20 by task swapper/1/0 [ 141.189958] [ 141.190158] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.12.0-rc7 [ 141.190458] Hardware name: Foundation-v8A (DT) [ 141.190658] Call trace: [ 141.190908] [<ffff200008089d70>] dump_backtrace+0x0/0x328 [ 141.191224] [<ffff20000808a1b4>] show_stack+0x14/0x20 [ 141.191507] [<ffff200008504c3c>] dump_stack+0xa4/0xc8 [ 141.191858] [<ffff20000826c19c>] print_address_description+0x13c/0x250 [ 141.192219] [<ffff20000826c5c8>] kasan_report+0x210/0x300 [ 141.192547] [<ffff20000826ad54>] __asan_load8+0x84/0x98 [ 141.192874] [<ffff20000854eeec>] gic_set_affinity+0x8c/0x140 [ 141.193158] [<ffff200008148b14>] irq_do_set_affinity+0x54/0xb8 [ 141.193473] [<ffff200008148d2c>] irq_set_affinity_locked+0x64/0xf0 [ 141.193828] [<ffff200008148e00>] __irq_set_affinity+0x48/0x78 [ 141.194158] [<ffff200008bc48a4>] arm_perf_starting_cpu+0x104/0x150 [ 141.194513] [<ffff2000080d73bc>] cpuhp_invoke_callback+0x17c/0x1f8 [ 141.194783] [<ffff2000080d94ec>] notify_cpu_starting+0x8c/0xb8 [ 141.195130] [<ffff2000080911ec>] secondary_start_kernel+0x15c/0x200 [ 141.195390] [<0000000080db81b4>] 0x80db81b4 [ 141.195603] [ 141.195685] The buggy address belongs to the variable: [ 141.196012] __cpu_logical_map+0x200/0x220 [ 141.196176] [ 141.196315] Memory state around the buggy address: [ 141.196586] ffff200009741c00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 141.196913] ffff200009741c80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 141.197158] >ffff200009741d00: 00 00 00 00 fa fa fa fa 00 00 00 00 00 00 00 00 [ 141.197487] ^ [ 141.197758] ffff200009741d80: 00 00 00 00 00 00 00 00 fa fa fa fa 00 00 00 00 [ 141.198060] ffff200009741e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 141.198358] ================================================================== [ 141.198609] Disabling lock debugging due to kernel taint [ 141.198961] CPU1: Booted secondary processor [410fd051] This patch adds the check to make sure the cpu is valid. Fixes: commit 021f653791ad17e03f98 ("irqchip: gic-v3: Initial support for GICv3") Cc: stable@vger.kernel.org Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3-its: Don't assume GICv3 hardware supports 16bit INTIDShanker Donthineni2017-06-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ITS driver is assuming every ITS hardware implementation supports minimum of 16bit INTID. But this is not true, as per GICv3 specification, INTID field is IMPLEMENTATION DEFINED in the range of 14-24 bits. We might see an unpredictable system behavior on systems where hardware support less than 16bits and software tries to use 64K LPI interrupts. On Qualcomm Datacenter Technologies QDF2400 platform, boot log shows confusing information about number of LPI chunks as shown below. The QDF2400 ITS hardware supports 24bit INTID. This patch allocates the memory resources for PEND/PROP tables based on discoverable value which is specified in GITS_TYPER.IDbits. Also it fixes the log message that reflects the correct number of LPI chunks were allocated. ITS@0xff7efe0000: allocated 524288 Devices @3c0400000 (indirect, esz 8, psz 64K, shr 1) ITS@0xff7efe0000: allocated 8192 Interrupt Collections @3c0130000 (flat, esz 8, psz 64K, shr 1) ITS@0xff7efe0000: allocated 8192 Virtual CPUs @3c0140000 (flat, esz 8, psz 64K, shr 1) ITS: Allocated 524032 chunks for LPIs PCI/MSI: ITS@0xff7efe0000 domain created Platform MSI: ITS@0xff7efe0000 domain created Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3-its: Add ACPI NUMA node mappingGanapatrao Kulkarni2017-06-23
| | | | | | | | | | | | Add code to parse SRAT ITS Affinity sub table as defined in ACPI 6.2. Later in per device probe, ITS devices are mapped to numa node using ITS Id to proximity domain mapping. [maz: fix dependency on ACPICA, fixed structure name, minor cleanups] Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3-its-platform-msi: Make of_device_ids constArvind Yadav2017-06-23
| | | | | | | | | of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3-its: Make of_device_ids constArvind Yadav2017-06-23
| | | | | | | | | of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-mvebu-icu: Add new driver for Marvell ICUThomas Petazzoni2017-06-23
| | | | | | | | | | | | | | | | | | The Marvell ICU unit is found in the CP110 block of the Marvell Armada 7K and 8K SoCs. It collects the wired interrupts of the devices located in the CP110 and turns them into SPI interrupts in the GIC located in the AP806 side of the SoC, by using a memory transaction. Until now, the ICU was configured in a static fashion by the firmware, and Linux was relying on this static configuration. By having Linux configure the ICU, we are more flexible, and we can allocate dynamically the GIC SPI interrupts only for devices that are actually in use. The driver was initially written by Hanna Hawa <hannah@marvell.com>. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-mvebu-gicp: Add new driver for Marvell GICPThomas Petazzoni2017-06-23
| | | | | | | | | | | | This commit adds a simple driver for the Marvell GICP, a hardware unit that converts memory writes into GIC SPI interrupts. The driver provides a number of functions to the ICU driver to allocate GICP interrupts, and get the physical addresses that the ICUs should write to to set/clear interrupts. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* dt-bindings/interrupt-controller: Add DT binding for the Marvell ICUThomas Petazzoni2017-06-23
| | | | | | | | | | | | This commit adds the Device Tree binding documentation for the Marvell ICU interrupt controller, which collects wired interrupts from the devices located into the CP110 hardware block of Marvell Armada 7K/8K, and converts them into SPI interrupts in the GIC located in the AP hardware block, using the GICP extension. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* dt-bindings/interrupt-controller: Add DT binding for the Marvell GICPThomas Petazzoni2017-06-22
| | | | | | | | | | | This commit adds the Device Tree binding documentation for the Marvell GICP, an extension to the GIC that allows to trigger GIC SPI interrupts using memory transactions. It is used by the ICU unit in the Marvell CP110 block to turn wired interrupts inside the CP into SPI interrupts at the GIC level in the AP. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/qcom: Use builtin_platform_driver to simplify the codeWei Yongjun2017-06-22
| | | | | | | Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/aspeed-i2c-ic: Add I2C IRQ controller for AspeedBrendan Higgins2017-06-22
| | | | | | | | | The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 separate I2C busses. This adds a dummy irqchip which maps the single hardware interrupt to software interrupts for each of the busses. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/aspeed-i2c-ic: Add binding docs for Aspeed I2C Interrupt ControllerBrendan Higgins2017-06-22
| | | | | | | | | Added device tree binding documentation for Aspeed I2C Interrupt Controller. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/aspeed-vic: Add AST2500 compatible stringAndrew Jeffery2017-06-22
| | | | | | | | | In addition to introducing the new compatible string the bindings description is reworked to be more generic. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/aspeed-vic: Constify irq_domain_opsTobias Klauser2017-06-22
| | | | | | | | struct irq_domain_ops is not modified, so it can be made const. Cc: Joel Stanley <joel@jms.id.au> Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* Revert "irqchip/armada-370-xp: Fix regression by clearing IRQ_NOAUTOEN"Thomas Petazzoni2017-06-22
| | | | | | | | | | This reverts commit 353d6d6c82e5d2533ba22e7f9fb081582bf50dc2, which is no longer needed, now that the irq-armada-370-xp driver properly re-enables per-CPU interrupt on both the boot CPU and secondary CPUs after resume. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume timeThomas Petazzoni2017-06-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to irq_set_probe(). While the commit log seems to imply that there are no functional changes, there are indeed functional changes introduced by this commit: the IRQ_NOAUTOEN flag is no longer cleared. This functional change caused a regression on Armada XP, which no longer works properly after suspend/resume because per-CPU interrupts remain disabled. This regression was temporarly worked around in commit 353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit implements the solution that was initially discussed with Thomas Gleixner. Due to how the hardware registers work, the irq-armada-370-xp cannot simply save/restore a bunch of registers at suspend/resume to make sure that the interrupts remain in the same state after resuming. Therefore, it relies on the kernel to say whether the interrupt is disabled or not, using the irqd_irq_disabled() function. This was all working fine while the IRQ_NOAUTOEN flag was cleared. With the change introduced by Rob Herring in d17cab4451df1, the IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled() returns false for per-CPU interrupts, and therefore our per-CPU interrupts are no longer re-enabled after resume. This commit fixes that by using irqd_irq_disabled() only for global interrupts, and using the newly introduced irq_percpu_is_enabled() for per-CPU interrupts. Also, it fixes a related problems that per-CPU interrupts were only re-enabled on the boot CPU and not other CPUs. Until now this wasn't a problem since on this platform, only the local timers are using per-CPU interrupts and the local timers of secondary CPUs are turned off/on during CPU hotplug before suspend, after after resume. However, since Linux 4.4, we are also be using per-CPU interrupts for the network controller, so we need to properly restore the per-CPU interrupts on secondary CPUs as well. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/armada-370-xp: Document the overall driver logicThomas Petazzoni2017-06-22
| | | | | | | | | | | Since the overall logic of the driver to handle the global and per-CPU masking of the interrupts is far from trivial, this commit adds a long comment detailing how the hardware operates and what strategy the driver implements on top of that. Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/armada-370-xp: Re-order register definitionsThomas Petazzoni2017-06-22
| | | | | | | | | | | In order to clarify to which register base the various register definitions apply, this commit re-orders them, and adds a comment that clearly indicate which registers are relative to "main_int_base" and which registers are relative to "per_cpu_int_base". Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gicv3-its: Skip irq affinity setting when target cpu is the same as ↵MaJun2017-06-22
| | | | | | | | | | | current setting Just skip the irq affinity setting when the target cpu is the same as current setting. This is a small optimization for irq affinity setting logic. Signed-off-by: MaJun <majun258@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3-its: Fix MSI alias accountingRobin Murphy2017-06-22
| | | | | | | | | | | | | | | | | | | | | The call to pci_for_each_dma_alias() in the ITS PCI code has aroused suspicion in the past, and upon closer inspection does turn out to be completely backwards. Rather than iterating through each RID alias of the given device, what we actually want to be doing here is iterating through all the *other* devices which may also alias the same RID, in order to size the table for the worst case. Do the right thing by ignoring the initial DMA aliases themselves and just using that walk to detect an aliasing bridge, then walking back down the bus topology as necessary to actually count everything else. Our alias handling still isn't perfect, since we don't account for the cases of certain bridges only taking ownership of transactions under particular circumstances, but without completely reworking the ITS code to cope with the notion of multiple DevIDs per device, it'll have to do. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-renesas-h8s: Constify irq_domain_opsTobias Klauser2017-06-22
| | | | | | | | | struct irq_domain_ops is not modified, so it can be made const. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: uclinux-h8-devel@lists.sourceforge.jp Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-renesas-h8300h: Constify irq_domain_opsTobias Klauser2017-06-22
| | | | | | | | | struct irq_domain_ops is not modified, so it can be made const. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: uclinux-h8-devel@lists.sourceforge.jp Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-mips-gic: Constify irq_domain_opsTobias Klauser2017-06-22
| | | | | | | struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-mbigen: Constify irq_domain_opsTobias Klauser2017-06-22
| | | | | | | struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-imx-gpcv2: Constify irq_domain_opsTobias Klauser2017-06-22
| | | | | | | struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/i8259: Constify irq_domain_opsTobias Klauser2017-06-22
| | | | | | | struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/sunxi-nmi: Support sun6i-a31-r-intc compatibleChen-Yu Tsai2017-06-22
| | | | | | | | | | | | | | | | | The R_INTC on the A31 is undocumented. It was previously supported by the sun6i-a31-sc-nmi compatible. This compatible however required the register region to start at the first used register, rather than the boundaries laid out in the SoC's memory map. The new compatible fixes the alignment, while also naming it properly. Since the only difference between the old and new compatibles are a fixed offset for the registers, and since the old one is deprecated, this patch adds a set of register defines for the new compatible, while modifying the old set to reference the new set minus a fixed offset. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* dt-bindings/interrupt-controller: sunxi-nmi: Add compatible for A31 R_INTCChen-Yu Tsai2017-06-22
| | | | | | | | | | | | | | | | | | | | | | | | The A31 and later have an R_INTC block which handles the NMI interrupt pin on the SoC. This interrupt pin is used by the external PMIC to signal interrupts to the SoC. While this hardware block is undocumented, the interrupt offsets combined with the register regions for the existing "sun6i-a31-sc-nmi" compatible line up with the old interrupt controller found on the A10. Experiments show that only the first 32 interrupt lines can be enabled, and only the first (NMI) interrupt is actually connected. This patch adds a new, properly named compatible for the A31 R_INTC block, which requires the register region to be properly aligned to the block boundary. For comparison, the old "sun6i-a31-sc-nmi" compatible had its register region aligned with the first used register. This didn't match up with the memory map in the SoC's datasheet/user manual. Since the new compatible supercedes the old one, deprecate the old one. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/sunxi-nmi: Const-ify sunxi_sc_nmi_reg_offs structuresChen-Yu Tsai2017-06-22
| | | | | | | | | | | | | The sunxi_sc_nmi_reg_offs, which hold the register offsets for the various variants, is never modified, and only used at init time within the init functions referenced by IRQCHIP_DECLARE, which themselves are tagged __init. Const-ify the sunxi_sc_nmi_reg_offs structures, and tag them as __initconst. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/sunxi-nmi: Reorder sunxi_sc_nmi_reg_offs' in ascending orderChen-Yu Tsai2017-06-22
| | | | | | | | This is a pure code move to reorder the various sunxi_sc_nmi_reg_offs' by family and alphabetical order. No functionality changes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/sunxi-nmi: Document interrupt disabling and clearing at probe timeChen-Yu Tsai2017-06-22
| | | | | | | | | | The sunxi-nmi disables all its interrupts and clears any pending interrupts at probe time. Add comments documenting it, just to make it clear. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/sunxi-nmi: Convert magic numbers to definesChen-Yu Tsai2017-06-22
| | | | | | | | | The sunxi-nmi driver has a bunch of raw register offsets and bit values. Convert them into define macros for better readability. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* Linux 4.12-rc4Linus Torvalds2017-06-04
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* fs/ufs: Set UFS default maximum bytes per fileRichard Narron2017-06-04
| | | | | | | | | | | | | | | | | | | | | | | | | This fixes a problem with reading files larger than 2GB from a UFS-2 file system: https://bugzilla.kernel.org/show_bug.cgi?id=195721 The incorrect UFS s_maxsize limit became a problem as of commit c2a9737f45e2 ("vfs,mm: fix a dead loop in truncate_inode_pages_range()") which started using s_maxbytes to avoid a page index overflow in do_generic_file_read(). That caused files to be truncated on UFS-2 file systems because the default maximum file size is 2GB (MAX_NON_LFS) and UFS didn't update it. Here I simply increase the default to a common value used by other file systems. Signed-off-by: Richard Narron <comet.berkeley@gmail.com> Cc: Al Viro <viro@zeniv.linux.org.uk> Cc: Will B <will.brokenbourgh2877@gmail.com> Cc: Theodore Ts'o <tytso@mit.edu> Cc: <stable@vger.kernel.org> # v4.9 and backports of c2a9737f45e2 Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'nfs-for-4.12-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfsLinus Torvalds2017-06-04
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull NFS client bugfixes from Trond Myklebust: "Bugfixes include: - Fix a typo in commit e092693443b ("NFS append COMMIT after synchronous COPY") that breaks copy offload - Fix the connect error propagation in xs_tcp_setup_socket() - Fix a lock leak in nfs40_walk_client_list - Verify that pNFS requests lie within the offset range of the layout segment" * tag 'nfs-for-4.12-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs: nfs: Mark unnecessarily extern functions as static SUNRPC: ensure correct error is reported by xs_tcp_setup_socket() NFSv4.0: Fix a lock leak in nfs40_walk_client_list pnfs: Fix the check for requests in range of layout segment xprtrdma: Delete an error message for a failed memory allocation in xprt_rdma_bc_setup() pNFS/flexfiles: missing error code in ff_layout_alloc_lseg() NFS fix COMMIT after COPY
| * nfs: Mark unnecessarily extern functions as staticJan Kara2017-06-03
| | | | | | | | | | | | | | | | | | | | | | nfs_initialise_sb() and nfs_clone_super() are declared as extern even though they are used only in fs/nfs/super.c. Mark them as static. Also remove explicit 'inline' directive from nfs_initialise_sb() and leave it upto compiler to decide whether inlining is worth it. Signed-off-by: Jan Kara <jack@suse.cz> Signed-off-by: Trond Myklebust <trond.myklebust@primarydata.com>
| * SUNRPC: ensure correct error is reported by xs_tcp_setup_socket()NeilBrown2017-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you attempt a TCP mount from an host that is unreachable in a way that triggers an immediate error from kernel_connect(), that error does not propagate up, instead EAGAIN is reported. This results in call_connect_status receiving the wrong error. A case that it easy to demonstrate is to attempt to mount from an address that results in ENETUNREACH, but first deleting any default route. Without this patch, the mount.nfs process is persistently runnable and is hard to kill. With this patch it exits as it should. The problem is caused by the fact that xs_tcp_force_close() eventually calls xprt_wake_pending_tasks(xprt, -EAGAIN); which causes an error return of -EAGAIN. so when xs_tcp_setup_sock() calls xprt_wake_pending_tasks(xprt, status); the status is ignored. Fixes: 4efdd92c9211 ("SUNRPC: Remove TCP client connection reset hack") Signed-off-by: NeilBrown <neilb@suse.com> Signed-off-by: Trond Myklebust <trond.myklebust@primarydata.com>
| * NFSv4.0: Fix a lock leak in nfs40_walk_client_listTrond Myklebust2017-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xiaolong Ye's kernel test robot detected the following Oops: [ 299.158991] BUG: scheduling while atomic: mount.nfs/9387/0x00000002 [ 299.169587] 2 locks held by mount.nfs/9387: [ 299.176165] #0: (nfs_clid_init_mutex){......}, at: [<ffffffff8130cc92>] nfs4_discover_server_trunking+0x47/0x1fc [ 299.201802] #1: (&(&nn->nfs_client_lock)->rlock){......}, at: [<ffffffff813125fa>] nfs40_walk_client_list+0x2e9/0x338 [ 299.221979] CPU: 0 PID: 9387 Comm: mount.nfs Not tainted 4.11.0-rc7-00021-g14d1bbb #45 [ 299.235584] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.9.3-20161025_171302-gandalf 04/01/2014 [ 299.251176] Call Trace: [ 299.255192] dump_stack+0x61/0x7e [ 299.260416] __schedule_bug+0x65/0x74 [ 299.266208] __schedule+0x5d/0x87c [ 299.271883] schedule+0x89/0x9a [ 299.276937] schedule_timeout+0x232/0x289 [ 299.283223] ? detach_if_pending+0x10b/0x10b [ 299.289935] schedule_timeout_uninterruptible+0x2a/0x2c [ 299.298266] ? put_rpccred+0x3e/0x115 [ 299.304327] ? schedule_timeout_uninterruptible+0x2a/0x2c [ 299.312851] msleep+0x1e/0x22 [ 299.317612] nfs4_discover_server_trunking+0x102/0x1fc [ 299.325644] nfs4_init_client+0x13f/0x194 It looks as if we recently added a spin_lock() leak to nfs40_walk_client_list() when cleaning up the code. Reported-by: kernel test robot <xiaolong.ye@intel.com> Fixes: 14d1bbb0ca42 ("NFS: Create a common nfs4_match_client() function") Cc: Anna Schumaker <Anna.Schumaker@Netapp.com> Signed-off-by: Trond Myklebust <trond.myklebust@primarydata.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 23:40:42 -0400