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authorChen-Yu Tsai <wens@csie.org>2017-06-06 01:59:28 -0400
committerMarc Zyngier <marc.zyngier@arm.com>2017-06-22 09:08:17 -0400
commit173bda53b3403d7278d74c4dabedf3d4325a2f89 (patch)
tree1422183d1c521332d38fb1d416554a16a8b3ee39
parentcd647575ac2f0c72dfded033f1d8c36c4cf13aa6 (diff)
irqchip/sunxi-nmi: Support sun6i-a31-r-intc compatible
The R_INTC on the A31 is undocumented. It was previously supported by the sun6i-a31-sc-nmi compatible. This compatible however required the register region to start at the first used register, rather than the boundaries laid out in the SoC's memory map. The new compatible fixes the alignment, while also naming it properly. Since the only difference between the old and new compatibles are a fixed offset for the registers, and since the old one is deprecated, this patch adds a set of register defines for the new compatible, while modifying the old set to reference the new set minus a fixed offset. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
-rw-r--r--drivers/irqchip/irq-sunxi-nmi.c29
1 files changed, 26 insertions, 3 deletions
diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index e713ec66322b..a412b5d5d0fa 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -27,9 +27,18 @@
27 27
28#define SUNXI_NMI_IRQ_BIT BIT(0) 28#define SUNXI_NMI_IRQ_BIT BIT(0)
29 29
30#define SUN6I_NMI_CTRL 0x00 30#define SUN6I_R_INTC_CTRL 0x0c
31#define SUN6I_NMI_PENDING 0x04 31#define SUN6I_R_INTC_PENDING 0x10
32#define SUN6I_NMI_ENABLE 0x34 32#define SUN6I_R_INTC_ENABLE 0x40
33
34/*
35 * For deprecated sun6i-a31-sc-nmi compatible.
36 * Registers are offset by 0x0c.
37 */
38#define SUN6I_R_INTC_NMI_OFFSET 0x0c
39#define SUN6I_NMI_CTRL (SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET)
40#define SUN6I_NMI_PENDING (SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET)
41#define SUN6I_NMI_ENABLE (SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET)
33 42
34#define SUN7I_NMI_CTRL 0x00 43#define SUN7I_NMI_CTRL 0x00
35#define SUN7I_NMI_PENDING 0x04 44#define SUN7I_NMI_PENDING 0x04
@@ -52,6 +61,12 @@ struct sunxi_sc_nmi_reg_offs {
52 u32 enable; 61 u32 enable;
53}; 62};
54 63
64static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = {
65 .ctrl = SUN6I_R_INTC_CTRL,
66 .pend = SUN6I_R_INTC_PENDING,
67 .enable = SUN6I_R_INTC_ENABLE,
68};
69
55static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = { 70static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = {
56 .ctrl = SUN6I_NMI_CTRL, 71 .ctrl = SUN6I_NMI_CTRL,
57 .pend = SUN6I_NMI_PENDING, 72 .pend = SUN6I_NMI_PENDING,
@@ -217,6 +232,14 @@ fail_irqd_remove:
217 return ret; 232 return ret;
218} 233}
219 234
235static int __init sun6i_r_intc_irq_init(struct device_node *node,
236 struct device_node *parent)
237{
238 return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs);
239}
240IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc",
241 sun6i_r_intc_irq_init);
242
220static int __init sun6i_sc_nmi_irq_init(struct device_node *node, 243static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
221 struct device_node *parent) 244 struct device_node *parent)
222{ 245{