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-rw-r--r--virt/kvm/arm/mmu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 1d90d79706bd..ea7314296ad1 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -196,6 +196,10 @@ static void clear_stage2_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr
196 * This is why right after unmapping a page/section and invalidating 196 * This is why right after unmapping a page/section and invalidating
197 * the corresponding TLBs, we call kvm_flush_dcache_p*() to make sure 197 * the corresponding TLBs, we call kvm_flush_dcache_p*() to make sure
198 * the IO subsystem will never hit in the cache. 198 * the IO subsystem will never hit in the cache.
199 *
200 * This is all avoided on systems that have ARM64_HAS_STAGE2_FWB, as
201 * we then fully enforce cacheability of RAM, no matter what the guest
202 * does.
199 */ 203 */
200static void unmap_stage2_ptes(struct kvm *kvm, pmd_t *pmd, 204static void unmap_stage2_ptes(struct kvm *kvm, pmd_t *pmd,
201 phys_addr_t addr, phys_addr_t end) 205 phys_addr_t addr, phys_addr_t end)