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-rw-r--r--tools/perf/pmu-events/arch/x86/ivytown/cache.json692
-rw-r--r--tools/perf/pmu-events/arch/x86/ivytown/frontend.json122
-rw-r--r--tools/perf/pmu-events/arch/x86/ivytown/memory.json368
-rw-r--r--tools/perf/pmu-events/arch/x86/ivytown/other.json20
-rw-r--r--tools/perf/pmu-events/arch/x86/ivytown/pipeline.json812
-rw-r--r--tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json60
6 files changed, 630 insertions, 1444 deletions
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf/pmu-events/arch/x86/ivytown/cache.json
index ff27a620edd8..d8cc93b3a04c 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json
@@ -10,6 +10,16 @@
10 "CounterHTOff": "0,1,2,3,4,5,6,7" 10 "CounterHTOff": "0,1,2,3,4,5,6,7"
11 }, 11 },
12 { 12 {
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
14 "EventCode": "0x24",
15 "Counter": "0,1,2,3",
16 "UMask": "0x3",
17 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
18 "SampleAfterValue": "200003",
19 "BriefDescription": "Demand Data Read requests",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
21 },
22 {
13 "PublicDescription": "RFO requests that hit L2 cache.", 23 "PublicDescription": "RFO requests that hit L2 cache.",
14 "EventCode": "0x24", 24 "EventCode": "0x24",
15 "Counter": "0,1,2,3", 25 "Counter": "0,1,2,3",
@@ -30,6 +40,16 @@
30 "CounterHTOff": "0,1,2,3,4,5,6,7" 40 "CounterHTOff": "0,1,2,3,4,5,6,7"
31 }, 41 },
32 { 42 {
43 "PublicDescription": "Counts all L2 store RFO requests.",
44 "EventCode": "0x24",
45 "Counter": "0,1,2,3",
46 "UMask": "0xc",
47 "EventName": "L2_RQSTS.ALL_RFO",
48 "SampleAfterValue": "200003",
49 "BriefDescription": "RFO requests to L2 cache",
50 "CounterHTOff": "0,1,2,3,4,5,6,7"
51 },
52 {
33 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
34 "EventCode": "0x24", 54 "EventCode": "0x24",
35 "Counter": "0,1,2,3", 55 "Counter": "0,1,2,3",
@@ -50,6 +70,16 @@
50 "CounterHTOff": "0,1,2,3,4,5,6,7" 70 "CounterHTOff": "0,1,2,3,4,5,6,7"
51 }, 71 },
52 { 72 {
73 "PublicDescription": "Counts all L2 code requests.",
74 "EventCode": "0x24",
75 "Counter": "0,1,2,3",
76 "UMask": "0x30",
77 "EventName": "L2_RQSTS.ALL_CODE_RD",
78 "SampleAfterValue": "200003",
79 "BriefDescription": "L2 code requests",
80 "CounterHTOff": "0,1,2,3,4,5,6,7"
81 },
82 {
53 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 83 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
54 "EventCode": "0x24", 84 "EventCode": "0x24",
55 "Counter": "0,1,2,3", 85 "Counter": "0,1,2,3",
@@ -70,36 +100,6 @@
70 "CounterHTOff": "0,1,2,3,4,5,6,7" 100 "CounterHTOff": "0,1,2,3,4,5,6,7"
71 }, 101 },
72 { 102 {
73 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
74 "EventCode": "0x24",
75 "Counter": "0,1,2,3",
76 "UMask": "0x3",
77 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
78 "SampleAfterValue": "200003",
79 "BriefDescription": "Demand Data Read requests",
80 "CounterHTOff": "0,1,2,3,4,5,6,7"
81 },
82 {
83 "PublicDescription": "Counts all L2 store RFO requests.",
84 "EventCode": "0x24",
85 "Counter": "0,1,2,3",
86 "UMask": "0xc",
87 "EventName": "L2_RQSTS.ALL_RFO",
88 "SampleAfterValue": "200003",
89 "BriefDescription": "RFO requests to L2 cache",
90 "CounterHTOff": "0,1,2,3,4,5,6,7"
91 },
92 {
93 "PublicDescription": "Counts all L2 code requests.",
94 "EventCode": "0x24",
95 "Counter": "0,1,2,3",
96 "UMask": "0x30",
97 "EventName": "L2_RQSTS.ALL_CODE_RD",
98 "SampleAfterValue": "200003",
99 "BriefDescription": "L2 code requests",
100 "CounterHTOff": "0,1,2,3,4,5,6,7"
101 },
102 {
103 "PublicDescription": "Counts all L2 HW prefetcher requests.", 103 "PublicDescription": "Counts all L2 HW prefetcher requests.",
104 "EventCode": "0x24", 104 "EventCode": "0x24",
105 "Counter": "0,1,2,3", 105 "Counter": "0,1,2,3",
@@ -219,6 +219,29 @@
219 "CounterHTOff": "2" 219 "CounterHTOff": "2"
220 }, 220 },
221 { 221 {
222 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
223 "EventCode": "0x48",
224 "Counter": "2",
225 "UMask": "0x1",
226 "AnyThread": "1",
227 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
228 "SampleAfterValue": "2000003",
229 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
230 "CounterMask": "1",
231 "CounterHTOff": "2"
232 },
233 {
234 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
235 "EventCode": "0x48",
236 "Counter": "0,1,2,3",
237 "UMask": "0x2",
238 "EventName": "L1D_PEND_MISS.FB_FULL",
239 "SampleAfterValue": "2000003",
240 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
241 "CounterMask": "1",
242 "CounterHTOff": "0,1,2,3,4,5,6,7"
243 },
244 {
222 "PublicDescription": "Counts the number of lines brought into the L1 data cache.", 245 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
223 "EventCode": "0x51", 246 "EventCode": "0x51",
224 "Counter": "0,1,2,3", 247 "Counter": "0,1,2,3",
@@ -239,76 +262,87 @@
239 "CounterHTOff": "0,1,2,3,4,5,6,7" 262 "CounterHTOff": "0,1,2,3,4,5,6,7"
240 }, 263 },
241 { 264 {
242 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 265 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
243 "EventCode": "0x60", 266 "EventCode": "0x60",
244 "Counter": "0,1,2,3", 267 "Counter": "0,1,2,3",
245 "UMask": "0x2", 268 "UMask": "0x1",
246 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 269 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
247 "SampleAfterValue": "2000003", 270 "SampleAfterValue": "2000003",
248 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 271 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
272 "CounterMask": "1",
249 "CounterHTOff": "0,1,2,3,4,5,6,7" 273 "CounterHTOff": "0,1,2,3,4,5,6,7"
250 }, 274 },
251 { 275 {
252 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 276 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
253 "EventCode": "0x60", 277 "EventCode": "0x60",
254 "Counter": "0,1,2,3", 278 "Counter": "0,1,2,3",
255 "UMask": "0x4", 279 "UMask": "0x1",
256 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 280 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
257 "SampleAfterValue": "2000003", 281 "SampleAfterValue": "2000003",
258 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 282 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
283 "CounterMask": "6",
259 "CounterHTOff": "0,1,2,3,4,5,6,7" 284 "CounterHTOff": "0,1,2,3,4,5,6,7"
260 }, 285 },
261 { 286 {
262 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 287 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
263 "EventCode": "0x60", 288 "EventCode": "0x60",
264 "Counter": "0,1,2,3", 289 "Counter": "0,1,2,3",
265 "UMask": "0x8", 290 "UMask": "0x2",
266 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 291 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
267 "SampleAfterValue": "2000003", 292 "SampleAfterValue": "2000003",
268 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 293 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
269 "CounterHTOff": "0,1,2,3,4,5,6,7" 294 "CounterHTOff": "0,1,2,3,4,5,6,7"
270 }, 295 },
271 { 296 {
272 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 297 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
273 "EventCode": "0x60", 298 "EventCode": "0x60",
274 "Counter": "0,1,2,3", 299 "Counter": "0,1,2,3",
275 "UMask": "0x1", 300 "UMask": "0x2",
276 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 301 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
277 "SampleAfterValue": "2000003", 302 "SampleAfterValue": "2000003",
278 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", 303 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
279 "CounterMask": "1", 304 "CounterMask": "1",
280 "CounterHTOff": "0,1,2,3,4,5,6,7" 305 "CounterHTOff": "0,1,2,3,4,5,6,7"
281 }, 306 },
282 { 307 {
283 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 308 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
284 "EventCode": "0x60", 309 "EventCode": "0x60",
285 "Counter": "0,1,2,3", 310 "Counter": "0,1,2,3",
286 "UMask": "0x8", 311 "UMask": "0x4",
287 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 312 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
288 "SampleAfterValue": "2000003", 313 "SampleAfterValue": "2000003",
289 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", 314 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
290 "CounterMask": "1",
291 "CounterHTOff": "0,1,2,3,4,5,6,7" 315 "CounterHTOff": "0,1,2,3,4,5,6,7"
292 }, 316 },
293 { 317 {
294 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 318 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
295 "EventCode": "0x60", 319 "EventCode": "0x60",
296 "Counter": "0,1,2,3", 320 "Counter": "0,1,2,3",
297 "UMask": "0x2", 321 "UMask": "0x4",
298 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", 322 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
299 "SampleAfterValue": "2000003", 323 "SampleAfterValue": "2000003",
300 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 324 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
301 "CounterMask": "1", 325 "CounterMask": "1",
302 "CounterHTOff": "0,1,2,3,4,5,6,7" 326 "CounterHTOff": "0,1,2,3,4,5,6,7"
303 }, 327 },
304 { 328 {
305 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 329 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
306 "EventCode": "0x60", 330 "EventCode": "0x60",
307 "Counter": "0,1,2,3", 331 "Counter": "0,1,2,3",
308 "UMask": "0x4", 332 "UMask": "0x8",
309 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 333 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
310 "SampleAfterValue": "2000003", 334 "SampleAfterValue": "2000003",
311 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 335 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
336 "CounterHTOff": "0,1,2,3,4,5,6,7"
337 },
338 {
339 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
340 "EventCode": "0x60",
341 "Counter": "0,1,2,3",
342 "UMask": "0x8",
343 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
344 "SampleAfterValue": "2000003",
345 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
312 "CounterMask": "1", 346 "CounterMask": "1",
313 "CounterHTOff": "0,1,2,3,4,5,6,7" 347 "CounterHTOff": "0,1,2,3,4,5,6,7"
314 }, 348 },
@@ -379,7 +413,7 @@
379 "UMask": "0x11", 413 "UMask": "0x11",
380 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 414 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
381 "SampleAfterValue": "100003", 415 "SampleAfterValue": "100003",
382 "BriefDescription": "Retired load uops that miss the STLB.", 416 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
383 "CounterHTOff": "0,1,2,3" 417 "CounterHTOff": "0,1,2,3"
384 }, 418 },
385 { 419 {
@@ -389,7 +423,7 @@
389 "UMask": "0x12", 423 "UMask": "0x12",
390 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 424 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
391 "SampleAfterValue": "100003", 425 "SampleAfterValue": "100003",
392 "BriefDescription": "Retired store uops that miss the STLB.", 426 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
393 "CounterHTOff": "0,1,2,3" 427 "CounterHTOff": "0,1,2,3"
394 }, 428 },
395 { 429 {
@@ -399,7 +433,7 @@
399 "UMask": "0x21", 433 "UMask": "0x21",
400 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 434 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
401 "SampleAfterValue": "100007", 435 "SampleAfterValue": "100007",
402 "BriefDescription": "Retired load uops with locked access.", 436 "BriefDescription": "Retired load uops with locked access. (Precise Event)",
403 "CounterHTOff": "0,1,2,3" 437 "CounterHTOff": "0,1,2,3"
404 }, 438 },
405 { 439 {
@@ -409,7 +443,7 @@
409 "UMask": "0x41", 443 "UMask": "0x41",
410 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 444 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
411 "SampleAfterValue": "100003", 445 "SampleAfterValue": "100003",
412 "BriefDescription": "Retired load uops that split across a cacheline boundary.", 446 "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
413 "CounterHTOff": "0,1,2,3" 447 "CounterHTOff": "0,1,2,3"
414 }, 448 },
415 { 449 {
@@ -419,7 +453,7 @@
419 "UMask": "0x42", 453 "UMask": "0x42",
420 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 454 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
421 "SampleAfterValue": "100003", 455 "SampleAfterValue": "100003",
422 "BriefDescription": "Retired store uops that split across a cacheline boundary.", 456 "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
423 "CounterHTOff": "0,1,2,3" 457 "CounterHTOff": "0,1,2,3"
424 }, 458 },
425 { 459 {
@@ -429,7 +463,7 @@
429 "UMask": "0x81", 463 "UMask": "0x81",
430 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 464 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
431 "SampleAfterValue": "2000003", 465 "SampleAfterValue": "2000003",
432 "BriefDescription": "All retired load uops.", 466 "BriefDescription": "All retired load uops. (Precise Event)",
433 "CounterHTOff": "0,1,2,3" 467 "CounterHTOff": "0,1,2,3"
434 }, 468 },
435 { 469 {
@@ -439,67 +473,61 @@
439 "UMask": "0x82", 473 "UMask": "0x82",
440 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 474 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
441 "SampleAfterValue": "2000003", 475 "SampleAfterValue": "2000003",
442 "BriefDescription": "All retired store uops.", 476 "BriefDescription": "All retired store uops. (Precise Event)",
443 "CounterHTOff": "0,1,2,3" 477 "CounterHTOff": "0,1,2,3"
444 }, 478 },
445 { 479 {
446 "PEBS": "1", 480 "PEBS": "1",
447 "PublicDescription": "Retired load uops with L1 cache hits as data sources.",
448 "EventCode": "0xD1", 481 "EventCode": "0xD1",
449 "Counter": "0,1,2,3", 482 "Counter": "0,1,2,3",
450 "UMask": "0x1", 483 "UMask": "0x1",
451 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 484 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
452 "SampleAfterValue": "2000003", 485 "SampleAfterValue": "2000003",
453 "BriefDescription": "Retired load uops with L1 cache hits as data sources. ", 486 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
454 "CounterHTOff": "0,1,2,3" 487 "CounterHTOff": "0,1,2,3"
455 }, 488 },
456 { 489 {
457 "PEBS": "1", 490 "PEBS": "1",
458 "PublicDescription": "Retired load uops with L2 cache hits as data sources.",
459 "EventCode": "0xD1", 491 "EventCode": "0xD1",
460 "Counter": "0,1,2,3", 492 "Counter": "0,1,2,3",
461 "UMask": "0x2", 493 "UMask": "0x2",
462 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 494 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
463 "SampleAfterValue": "100003", 495 "SampleAfterValue": "100003",
464 "BriefDescription": "Retired load uops with L2 cache hits as data sources. ", 496 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
465 "CounterHTOff": "0,1,2,3" 497 "CounterHTOff": "0,1,2,3"
466 }, 498 },
467 { 499 {
468 "PEBS": "1", 500 "PEBS": "1",
469 "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.",
470 "EventCode": "0xD1", 501 "EventCode": "0xD1",
471 "Counter": "0,1,2,3", 502 "Counter": "0,1,2,3",
472 "UMask": "0x4", 503 "UMask": "0x4",
473 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", 504 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
474 "SampleAfterValue": "50021", 505 "SampleAfterValue": "50021",
475 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ", 506 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
476 "CounterHTOff": "0,1,2,3" 507 "CounterHTOff": "0,1,2,3"
477 }, 508 },
478 { 509 {
479 "PEBS": "1", 510 "PEBS": "1",
480 "PublicDescription": "Retired load uops whose data source followed an L1 miss.",
481 "EventCode": "0xD1", 511 "EventCode": "0xD1",
482 "Counter": "0,1,2,3", 512 "Counter": "0,1,2,3",
483 "UMask": "0x8", 513 "UMask": "0x8",
484 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 514 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
485 "SampleAfterValue": "100003", 515 "SampleAfterValue": "100003",
486 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss", 516 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
487 "CounterHTOff": "0,1,2,3" 517 "CounterHTOff": "0,1,2,3"
488 }, 518 },
489 { 519 {
490 "PEBS": "1", 520 "PEBS": "1",
491 "PublicDescription": "Retired load uops that missed L2, excluding unknown sources.",
492 "EventCode": "0xD1", 521 "EventCode": "0xD1",
493 "Counter": "0,1,2,3", 522 "Counter": "0,1,2,3",
494 "UMask": "0x10", 523 "UMask": "0x10",
495 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 524 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
496 "SampleAfterValue": "50021", 525 "SampleAfterValue": "50021",
497 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", 526 "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
498 "CounterHTOff": "0,1,2,3" 527 "CounterHTOff": "0,1,2,3"
499 }, 528 },
500 { 529 {
501 "PEBS": "1", 530 "PEBS": "1",
502 "PublicDescription": "Retired load uops whose data source is LLC miss.",
503 "EventCode": "0xD1", 531 "EventCode": "0xD1",
504 "Counter": "0,1,2,3", 532 "Counter": "0,1,2,3",
505 "UMask": "0x20", 533 "UMask": "0x20",
@@ -510,67 +538,61 @@
510 }, 538 },
511 { 539 {
512 "PEBS": "1", 540 "PEBS": "1",
513 "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
514 "EventCode": "0xD1", 541 "EventCode": "0xD1",
515 "Counter": "0,1,2,3", 542 "Counter": "0,1,2,3",
516 "UMask": "0x40", 543 "UMask": "0x40",
517 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 544 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
518 "SampleAfterValue": "100003", 545 "SampleAfterValue": "100003",
519 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ", 546 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
520 "CounterHTOff": "0,1,2,3" 547 "CounterHTOff": "0,1,2,3"
521 }, 548 },
522 { 549 {
523 "PEBS": "1", 550 "PEBS": "1",
524 "PublicDescription": "Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed.",
525 "EventCode": "0xD2", 551 "EventCode": "0xD2",
526 "Counter": "0,1,2,3", 552 "Counter": "0,1,2,3",
527 "UMask": "0x1", 553 "UMask": "0x1",
528 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", 554 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
529 "SampleAfterValue": "20011", 555 "SampleAfterValue": "20011",
530 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ", 556 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
531 "CounterHTOff": "0,1,2,3" 557 "CounterHTOff": "0,1,2,3"
532 }, 558 },
533 { 559 {
534 "PEBS": "1", 560 "PEBS": "1",
535 "PublicDescription": "Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits.",
536 "EventCode": "0xD2", 561 "EventCode": "0xD2",
537 "Counter": "0,1,2,3", 562 "Counter": "0,1,2,3",
538 "UMask": "0x2", 563 "UMask": "0x2",
539 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", 564 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
540 "SampleAfterValue": "20011", 565 "SampleAfterValue": "20011",
541 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ", 566 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
542 "CounterHTOff": "0,1,2,3" 567 "CounterHTOff": "0,1,2,3"
543 }, 568 },
544 { 569 {
545 "PEBS": "1", 570 "PEBS": "1",
546 "PublicDescription": "Retired load uops whose data source was an on-package core cache with HitM responses.",
547 "EventCode": "0xD2", 571 "EventCode": "0xD2",
548 "Counter": "0,1,2,3", 572 "Counter": "0,1,2,3",
549 "UMask": "0x4", 573 "UMask": "0x4",
550 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", 574 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
551 "SampleAfterValue": "20011", 575 "SampleAfterValue": "20011",
552 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ", 576 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
553 "CounterHTOff": "0,1,2,3" 577 "CounterHTOff": "0,1,2,3"
554 }, 578 },
555 { 579 {
556 "PEBS": "1", 580 "PEBS": "1",
557 "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.",
558 "EventCode": "0xD2", 581 "EventCode": "0xD2",
559 "Counter": "0,1,2,3", 582 "Counter": "0,1,2,3",
560 "UMask": "0x8", 583 "UMask": "0x8",
561 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", 584 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
562 "SampleAfterValue": "100003", 585 "SampleAfterValue": "100003",
563 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ", 586 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
564 "CounterHTOff": "0,1,2,3" 587 "CounterHTOff": "0,1,2,3"
565 }, 588 },
566 { 589 {
567 "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)",
568 "EventCode": "0xD3", 590 "EventCode": "0xD3",
569 "Counter": "0,1,2,3", 591 "Counter": "0,1,2,3",
570 "UMask": "0x1", 592 "UMask": "0x3",
571 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", 593 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
572 "SampleAfterValue": "100007", 594 "SampleAfterValue": "100007",
573 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", 595 "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
574 "CounterHTOff": "0,1,2,3" 596 "CounterHTOff": "0,1,2,3"
575 }, 597 },
576 { 598 {
@@ -778,495 +800,5 @@
778 "SampleAfterValue": "100003", 800 "SampleAfterValue": "100003",
779 "BriefDescription": "Split locks in SQ", 801 "BriefDescription": "Split locks in SQ",
780 "CounterHTOff": "0,1,2,3,4,5,6,7" 802 "CounterHTOff": "0,1,2,3,4,5,6,7"
781 },
782 {
783 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
784 "EventCode": "0x60",
785 "Counter": "0,1,2,3",
786 "UMask": "0x1",
787 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
788 "SampleAfterValue": "2000003",
789 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
790 "CounterMask": "6",
791 "CounterHTOff": "0,1,2,3,4,5,6,7"
792 },
793 {
794 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
795 "EventCode": "0x48",
796 "Counter": "2",
797 "UMask": "0x1",
798 "AnyThread": "1",
799 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
800 "SampleAfterValue": "2000003",
801 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
802 "CounterMask": "1",
803 "CounterHTOff": "2"
804 },
805 {
806 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
807 "EventCode": "0x48",
808 "Counter": "0,1,2,3",
809 "UMask": "0x2",
810 "EventName": "L1D_PEND_MISS.FB_FULL",
811 "SampleAfterValue": "2000003",
812 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
813 "CounterMask": "1",
814 "CounterHTOff": "0,1,2,3,4,5,6,7"
815 },
816 {
817 "EventCode": "0xB7, 0xBB",
818 "MSRValue": "0x4003c0091",
819 "Counter": "0,1,2,3",
820 "UMask": "0x1",
821 "Offcore": "1",
822 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
823 "MSRIndex": "0x1a6,0x1a7",
824 "SampleAfterValue": "100003",
825 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
826 "CounterHTOff": "0,1,2,3"
827 },
828 {
829 "EventCode": "0xB7, 0xBB",
830 "MSRValue": "0x10003c0091",
831 "Counter": "0,1,2,3",
832 "UMask": "0x1",
833 "Offcore": "1",
834 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
835 "MSRIndex": "0x1a6,0x1a7",
836 "SampleAfterValue": "100003",
837 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
838 "CounterHTOff": "0,1,2,3"
839 },
840 {
841 "EventCode": "0xB7, 0xBB",
842 "MSRValue": "0x1003c0091",
843 "Counter": "0,1,2,3",
844 "UMask": "0x1",
845 "Offcore": "1",
846 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
847 "MSRIndex": "0x1a6,0x1a7",
848 "SampleAfterValue": "100003",
849 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
850 "CounterHTOff": "0,1,2,3"
851 },
852 {
853 "EventCode": "0xB7, 0xBB",
854 "MSRValue": "0x2003c0091",
855 "Counter": "0,1,2,3",
856 "UMask": "0x1",
857 "Offcore": "1",
858 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
859 "MSRIndex": "0x1a6,0x1a7",
860 "SampleAfterValue": "100003",
861 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
862 "CounterHTOff": "0,1,2,3"
863 },
864 {
865 "EventCode": "0xB7, 0xBB",
866 "MSRValue": "0x3f803c0090",
867 "Counter": "0,1,2,3",
868 "UMask": "0x1",
869 "Offcore": "1",
870 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
871 "MSRIndex": "0x1a6,0x1a7",
872 "SampleAfterValue": "100003",
873 "BriefDescription": "Counts all prefetch data reads that hit the LLC",
874 "CounterHTOff": "0,1,2,3"
875 },
876 {
877 "EventCode": "0xB7, 0xBB",
878 "MSRValue": "0x4003c0090",
879 "Counter": "0,1,2,3",
880 "UMask": "0x1",
881 "Offcore": "1",
882 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
883 "MSRIndex": "0x1a6,0x1a7",
884 "SampleAfterValue": "100003",
885 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
886 "CounterHTOff": "0,1,2,3"
887 },
888 {
889 "EventCode": "0xB7, 0xBB",
890 "MSRValue": "0x10003c0090",
891 "Counter": "0,1,2,3",
892 "UMask": "0x1",
893 "Offcore": "1",
894 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
895 "MSRIndex": "0x1a6,0x1a7",
896 "SampleAfterValue": "100003",
897 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
898 "CounterHTOff": "0,1,2,3"
899 },
900 {
901 "EventCode": "0xB7, 0xBB",
902 "MSRValue": "0x1003c0090",
903 "Counter": "0,1,2,3",
904 "UMask": "0x1",
905 "Offcore": "1",
906 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
907 "MSRIndex": "0x1a6,0x1a7",
908 "SampleAfterValue": "100003",
909 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
910 "CounterHTOff": "0,1,2,3"
911 },
912 {
913 "EventCode": "0xB7, 0xBB",
914 "MSRValue": "0x2003c0090",
915 "Counter": "0,1,2,3",
916 "UMask": "0x1",
917 "Offcore": "1",
918 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
919 "MSRIndex": "0x1a6,0x1a7",
920 "SampleAfterValue": "100003",
921 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
922 "CounterHTOff": "0,1,2,3"
923 },
924 {
925 "EventCode": "0xB7, 0xBB",
926 "MSRValue": "0x3f803c03f7",
927 "Counter": "0,1,2,3",
928 "UMask": "0x1",
929 "Offcore": "1",
930 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
931 "MSRIndex": "0x1a6,0x1a7",
932 "SampleAfterValue": "100003",
933 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
934 "CounterHTOff": "0,1,2,3"
935 },
936 {
937 "EventCode": "0xB7, 0xBB",
938 "MSRValue": "0x4003c03f7",
939 "Counter": "0,1,2,3",
940 "UMask": "0x1",
941 "Offcore": "1",
942 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
943 "MSRIndex": "0x1a6,0x1a7",
944 "SampleAfterValue": "100003",
945 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
946 "CounterHTOff": "0,1,2,3"
947 },
948 {
949 "EventCode": "0xB7, 0xBB",
950 "MSRValue": "0x10003c03f7",
951 "Counter": "0,1,2,3",
952 "UMask": "0x1",
953 "Offcore": "1",
954 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
955 "MSRIndex": "0x1a6,0x1a7",
956 "SampleAfterValue": "100003",
957 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
958 "CounterHTOff": "0,1,2,3"
959 },
960 {
961 "EventCode": "0xB7, 0xBB",
962 "MSRValue": "0x1003c03f7",
963 "Counter": "0,1,2,3",
964 "UMask": "0x1",
965 "Offcore": "1",
966 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
967 "MSRIndex": "0x1a6,0x1a7",
968 "SampleAfterValue": "100003",
969 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
970 "CounterHTOff": "0,1,2,3"
971 },
972 {
973 "EventCode": "0xB7, 0xBB",
974 "MSRValue": "0x2003c03f7",
975 "Counter": "0,1,2,3",
976 "UMask": "0x1",
977 "Offcore": "1",
978 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
979 "MSRIndex": "0x1a6,0x1a7",
980 "SampleAfterValue": "100003",
981 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
982 "CounterHTOff": "0,1,2,3"
983 },
984 {
985 "EventCode": "0xB7, 0xBB",
986 "MSRValue": "0x10008",
987 "Counter": "0,1,2,3",
988 "UMask": "0x1",
989 "Offcore": "1",
990 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
991 "MSRIndex": "0x1a6,0x1a7",
992 "SampleAfterValue": "100003",
993 "BriefDescription": "Counts all writebacks from the core to the LLC",
994 "CounterHTOff": "0,1,2,3"
995 },
996 {
997 "EventCode": "0xB7, 0xBB",
998 "MSRValue": "0x3f803c0004",
999 "Counter": "0,1,2,3",
1000 "UMask": "0x1",
1001 "Offcore": "1",
1002 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
1003 "MSRIndex": "0x1a6,0x1a7",
1004 "SampleAfterValue": "100003",
1005 "BriefDescription": "Counts all demand code reads that hit in the LLC",
1006 "CounterHTOff": "0,1,2,3"
1007 },
1008 {
1009 "EventCode": "0xB7, 0xBB",
1010 "MSRValue": "0x3f803c0001",
1011 "Counter": "0,1,2,3",
1012 "UMask": "0x1",
1013 "Offcore": "1",
1014 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
1015 "MSRIndex": "0x1a6,0x1a7",
1016 "SampleAfterValue": "100003",
1017 "BriefDescription": "Counts all demand data reads that hit in the LLC",
1018 "CounterHTOff": "0,1,2,3"
1019 },
1020 {
1021 "EventCode": "0xB7, 0xBB",
1022 "MSRValue": "0x4003c0001",
1023 "Counter": "0,1,2,3",
1024 "UMask": "0x1",
1025 "Offcore": "1",
1026 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1027 "MSRIndex": "0x1a6,0x1a7",
1028 "SampleAfterValue": "100003",
1029 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1030 "CounterHTOff": "0,1,2,3"
1031 },
1032 {
1033 "EventCode": "0xB7, 0xBB",
1034 "MSRValue": "0x10003c0001",
1035 "Counter": "0,1,2,3",
1036 "UMask": "0x1",
1037 "Offcore": "1",
1038 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1039 "MSRIndex": "0x1a6,0x1a7",
1040 "SampleAfterValue": "100003",
1041 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1042 "CounterHTOff": "0,1,2,3"
1043 },
1044 {
1045 "EventCode": "0xB7, 0xBB",
1046 "MSRValue": "0x1003c0001",
1047 "Counter": "0,1,2,3",
1048 "UMask": "0x1",
1049 "Offcore": "1",
1050 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1051 "MSRIndex": "0x1a6,0x1a7",
1052 "SampleAfterValue": "100003",
1053 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1054 "CounterHTOff": "0,1,2,3"
1055 },
1056 {
1057 "EventCode": "0xB7, 0xBB",
1058 "MSRValue": "0x2003c0001",
1059 "Counter": "0,1,2,3",
1060 "UMask": "0x1",
1061 "Offcore": "1",
1062 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
1063 "MSRIndex": "0x1a6,0x1a7",
1064 "SampleAfterValue": "100003",
1065 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
1066 "CounterHTOff": "0,1,2,3"
1067 },
1068 {
1069 "EventCode": "0xB7, 0xBB",
1070 "MSRValue": "0x10003c0002",
1071 "Counter": "0,1,2,3",
1072 "UMask": "0x1",
1073 "Offcore": "1",
1074 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
1075 "MSRIndex": "0x1a6,0x1a7",
1076 "SampleAfterValue": "100003",
1077 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1078 "CounterHTOff": "0,1,2,3"
1079 },
1080 {
1081 "EventCode": "0xB7, 0xBB",
1082 "MSRValue": "0x803c8000",
1083 "Counter": "0,1,2,3",
1084 "UMask": "0x1",
1085 "Offcore": "1",
1086 "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
1087 "MSRIndex": "0x1a6,0x1a7",
1088 "SampleAfterValue": "100003",
1089 "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
1090 "CounterHTOff": "0,1,2,3"
1091 },
1092 {
1093 "EventCode": "0xB7, 0xBB",
1094 "MSRValue": "0x23ffc08000",
1095 "Counter": "0,1,2,3",
1096 "UMask": "0x1",
1097 "Offcore": "1",
1098 "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
1099 "MSRIndex": "0x1a6,0x1a7",
1100 "SampleAfterValue": "100003",
1101 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
1102 "CounterHTOff": "0,1,2,3"
1103 },
1104 {
1105 "EventCode": "0xB7, 0xBB",
1106 "MSRValue": "0x3f803c0040",
1107 "Counter": "0,1,2,3",
1108 "UMask": "0x1",
1109 "Offcore": "1",
1110 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
1111 "MSRIndex": "0x1a6,0x1a7",
1112 "SampleAfterValue": "100003",
1113 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
1114 "CounterHTOff": "0,1,2,3"
1115 },
1116 {
1117 "EventCode": "0xB7, 0xBB",
1118 "MSRValue": "0x3f803c0010",
1119 "Counter": "0,1,2,3",
1120 "UMask": "0x1",
1121 "Offcore": "1",
1122 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
1123 "MSRIndex": "0x1a6,0x1a7",
1124 "SampleAfterValue": "100003",
1125 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
1126 "CounterHTOff": "0,1,2,3"
1127 },
1128 {
1129 "EventCode": "0xB7, 0xBB",
1130 "MSRValue": "0x4003c0010",
1131 "Counter": "0,1,2,3",
1132 "UMask": "0x1",
1133 "Offcore": "1",
1134 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1135 "MSRIndex": "0x1a6,0x1a7",
1136 "SampleAfterValue": "100003",
1137 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1138 "CounterHTOff": "0,1,2,3"
1139 },
1140 {
1141 "EventCode": "0xB7, 0xBB",
1142 "MSRValue": "0x10003c0010",
1143 "Counter": "0,1,2,3",
1144 "UMask": "0x1",
1145 "Offcore": "1",
1146 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1147 "MSRIndex": "0x1a6,0x1a7",
1148 "SampleAfterValue": "100003",
1149 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1150 "CounterHTOff": "0,1,2,3"
1151 },
1152 {
1153 "EventCode": "0xB7, 0xBB",
1154 "MSRValue": "0x1003c0010",
1155 "Counter": "0,1,2,3",
1156 "UMask": "0x1",
1157 "Offcore": "1",
1158 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1159 "MSRIndex": "0x1a6,0x1a7",
1160 "SampleAfterValue": "100003",
1161 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1162 "CounterHTOff": "0,1,2,3"
1163 },
1164 {
1165 "EventCode": "0xB7, 0xBB",
1166 "MSRValue": "0x2003c0010",
1167 "Counter": "0,1,2,3",
1168 "UMask": "0x1",
1169 "Offcore": "1",
1170 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
1171 "MSRIndex": "0x1a6,0x1a7",
1172 "SampleAfterValue": "100003",
1173 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
1174 "CounterHTOff": "0,1,2,3"
1175 },
1176 {
1177 "EventCode": "0xB7, 0xBB",
1178 "MSRValue": "0x3f803c0200",
1179 "Counter": "0,1,2,3",
1180 "UMask": "0x1",
1181 "Offcore": "1",
1182 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
1183 "MSRIndex": "0x1a6,0x1a7",
1184 "SampleAfterValue": "100003",
1185 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
1186 "CounterHTOff": "0,1,2,3"
1187 },
1188 {
1189 "EventCode": "0xB7, 0xBB",
1190 "MSRValue": "0x3f803c0080",
1191 "Counter": "0,1,2,3",
1192 "UMask": "0x1",
1193 "Offcore": "1",
1194 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
1195 "MSRIndex": "0x1a6,0x1a7",
1196 "SampleAfterValue": "100003",
1197 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
1198 "CounterHTOff": "0,1,2,3"
1199 },
1200 {
1201 "EventCode": "0xB7, 0xBB",
1202 "MSRValue": "0x4003c0080",
1203 "Counter": "0,1,2,3",
1204 "UMask": "0x1",
1205 "Offcore": "1",
1206 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1207 "MSRIndex": "0x1a6,0x1a7",
1208 "SampleAfterValue": "100003",
1209 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1210 "CounterHTOff": "0,1,2,3"
1211 },
1212 {
1213 "EventCode": "0xB7, 0xBB",
1214 "MSRValue": "0x10003c0080",
1215 "Counter": "0,1,2,3",
1216 "UMask": "0x1",
1217 "Offcore": "1",
1218 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1219 "MSRIndex": "0x1a6,0x1a7",
1220 "SampleAfterValue": "100003",
1221 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1222 "CounterHTOff": "0,1,2,3"
1223 },
1224 {
1225 "EventCode": "0xB7, 0xBB",
1226 "MSRValue": "0x1003c0080",
1227 "Counter": "0,1,2,3",
1228 "UMask": "0x1",
1229 "Offcore": "1",
1230 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1231 "MSRIndex": "0x1a6,0x1a7",
1232 "SampleAfterValue": "100003",
1233 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1234 "CounterHTOff": "0,1,2,3"
1235 },
1236 {
1237 "EventCode": "0xB7, 0xBB",
1238 "MSRValue": "0x2003c0080",
1239 "Counter": "0,1,2,3",
1240 "UMask": "0x1",
1241 "Offcore": "1",
1242 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
1243 "MSRIndex": "0x1a6,0x1a7",
1244 "SampleAfterValue": "100003",
1245 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
1246 "CounterHTOff": "0,1,2,3"
1247 },
1248 {
1249 "EventCode": "0xB7, 0xBB",
1250 "MSRValue": "0x10400",
1251 "Counter": "0,1,2,3",
1252 "UMask": "0x1",
1253 "Offcore": "1",
1254 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
1255 "MSRIndex": "0x1a6,0x1a7",
1256 "SampleAfterValue": "100003",
1257 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
1258 "CounterHTOff": "0,1,2,3"
1259 },
1260 {
1261 "EventCode": "0xB7, 0xBB",
1262 "MSRValue": "0x10800",
1263 "Counter": "0,1,2,3",
1264 "UMask": "0x1",
1265 "Offcore": "1",
1266 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
1267 "MSRIndex": "0x1a6,0x1a7",
1268 "SampleAfterValue": "100003",
1269 "BriefDescription": "Counts non-temporal stores",
1270 "CounterHTOff": "0,1,2,3"
1271 } 803 }
1272] \ No newline at end of file 804] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
index de72b84b3536..efaa949ead31 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
@@ -20,76 +20,45 @@
20 "CounterHTOff": "0,1,2,3,4,5,6,7" 20 "CounterHTOff": "0,1,2,3,4,5,6,7"
21 }, 21 },
22 { 22 {
23 "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", 23 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
24 "EventCode": "0x79",
25 "Counter": "0,1,2,3",
26 "UMask": "0x8",
27 "EventName": "IDQ.DSB_UOPS",
28 "SampleAfterValue": "2000003",
29 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
31 },
32 {
33 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
34 "EventCode": "0x79",
35 "Counter": "0,1,2,3",
36 "UMask": "0x10",
37 "EventName": "IDQ.MS_DSB_UOPS",
38 "SampleAfterValue": "2000003",
39 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
40 "CounterHTOff": "0,1,2,3,4,5,6,7"
41 },
42 {
43 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
44 "EventCode": "0x79",
45 "Counter": "0,1,2,3",
46 "UMask": "0x20",
47 "EventName": "IDQ.MS_MITE_UOPS",
48 "SampleAfterValue": "2000003",
49 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
50 "CounterHTOff": "0,1,2,3,4,5,6,7"
51 },
52 {
53 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
54 "EventCode": "0x79", 24 "EventCode": "0x79",
55 "Counter": "0,1,2,3", 25 "Counter": "0,1,2,3",
56 "UMask": "0x30", 26 "UMask": "0x4",
57 "EventName": "IDQ.MS_UOPS", 27 "EventName": "IDQ.MITE_CYCLES",
58 "SampleAfterValue": "2000003", 28 "SampleAfterValue": "2000003",
59 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 29 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
30 "CounterMask": "1",
60 "CounterHTOff": "0,1,2,3,4,5,6,7" 31 "CounterHTOff": "0,1,2,3,4,5,6,7"
61 }, 32 },
62 { 33 {
63 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 34 "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
64 "EventCode": "0x79", 35 "EventCode": "0x79",
65 "Counter": "0,1,2,3", 36 "Counter": "0,1,2,3",
66 "UMask": "0x30", 37 "UMask": "0x8",
67 "EventName": "IDQ.MS_CYCLES", 38 "EventName": "IDQ.DSB_UOPS",
68 "SampleAfterValue": "2000003", 39 "SampleAfterValue": "2000003",
69 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 40 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
70 "CounterMask": "1",
71 "CounterHTOff": "0,1,2,3,4,5,6,7" 41 "CounterHTOff": "0,1,2,3,4,5,6,7"
72 }, 42 },
73 { 43 {
74 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", 44 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
75 "EventCode": "0x79", 45 "EventCode": "0x79",
76 "Counter": "0,1,2,3", 46 "Counter": "0,1,2,3",
77 "UMask": "0x4", 47 "UMask": "0x8",
78 "EventName": "IDQ.MITE_CYCLES", 48 "EventName": "IDQ.DSB_CYCLES",
79 "SampleAfterValue": "2000003", 49 "SampleAfterValue": "2000003",
80 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", 50 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
81 "CounterMask": "1", 51 "CounterMask": "1",
82 "CounterHTOff": "0,1,2,3,4,5,6,7" 52 "CounterHTOff": "0,1,2,3,4,5,6,7"
83 }, 53 },
84 { 54 {
85 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 55 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
86 "EventCode": "0x79", 56 "EventCode": "0x79",
87 "Counter": "0,1,2,3", 57 "Counter": "0,1,2,3",
88 "UMask": "0x8", 58 "UMask": "0x10",
89 "EventName": "IDQ.DSB_CYCLES", 59 "EventName": "IDQ.MS_DSB_UOPS",
90 "SampleAfterValue": "2000003", 60 "SampleAfterValue": "2000003",
91 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 61 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
92 "CounterMask": "1",
93 "CounterHTOff": "0,1,2,3,4,5,6,7" 62 "CounterHTOff": "0,1,2,3,4,5,6,7"
94 }, 63 },
95 { 64 {
@@ -138,6 +107,16 @@
138 "CounterHTOff": "0,1,2,3,4,5,6,7" 107 "CounterHTOff": "0,1,2,3,4,5,6,7"
139 }, 108 },
140 { 109 {
110 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
111 "EventCode": "0x79",
112 "Counter": "0,1,2,3",
113 "UMask": "0x20",
114 "EventName": "IDQ.MS_MITE_UOPS",
115 "SampleAfterValue": "2000003",
116 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
117 "CounterHTOff": "0,1,2,3,4,5,6,7"
118 },
119 {
141 "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", 120 "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
142 "EventCode": "0x79", 121 "EventCode": "0x79",
143 "Counter": "0,1,2,3", 122 "Counter": "0,1,2,3",
@@ -160,6 +139,39 @@
160 "CounterHTOff": "0,1,2,3,4,5,6,7" 139 "CounterHTOff": "0,1,2,3,4,5,6,7"
161 }, 140 },
162 { 141 {
142 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
143 "EventCode": "0x79",
144 "Counter": "0,1,2,3",
145 "UMask": "0x30",
146 "EventName": "IDQ.MS_UOPS",
147 "SampleAfterValue": "2000003",
148 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
149 "CounterHTOff": "0,1,2,3,4,5,6,7"
150 },
151 {
152 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
153 "EventCode": "0x79",
154 "Counter": "0,1,2,3",
155 "UMask": "0x30",
156 "EventName": "IDQ.MS_CYCLES",
157 "SampleAfterValue": "2000003",
158 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
159 "CounterMask": "1",
160 "CounterHTOff": "0,1,2,3,4,5,6,7"
161 },
162 {
163 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
164 "EventCode": "0x79",
165 "Counter": "0,1,2,3",
166 "UMask": "0x30",
167 "EdgeDetect": "1",
168 "EventName": "IDQ.MS_SWITCHES",
169 "SampleAfterValue": "2000003",
170 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
171 "CounterMask": "1",
172 "CounterHTOff": "0,1,2,3,4,5,6,7"
173 },
174 {
163 "PublicDescription": "Number of uops delivered to IDQ from any path.", 175 "PublicDescription": "Number of uops delivered to IDQ from any path.",
164 "EventCode": "0x79", 176 "EventCode": "0x79",
165 "Counter": "0,1,2,3", 177 "Counter": "0,1,2,3",
@@ -206,7 +218,7 @@
206 "UMask": "0x1", 218 "UMask": "0x1",
207 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 219 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
208 "SampleAfterValue": "2000003", 220 "SampleAfterValue": "2000003",
209 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ", 221 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
210 "CounterHTOff": "0,1,2,3" 222 "CounterHTOff": "0,1,2,3"
211 }, 223 },
212 { 224 {
@@ -289,17 +301,5 @@
289 "SampleAfterValue": "2000003", 301 "SampleAfterValue": "2000003",
290 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", 302 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
291 "CounterHTOff": "0,1,2,3,4,5,6,7" 303 "CounterHTOff": "0,1,2,3,4,5,6,7"
292 },
293 {
294 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
295 "EventCode": "0x79",
296 "Counter": "0,1,2,3",
297 "UMask": "0x30",
298 "EdgeDetect": "1",
299 "EventName": "IDQ.MS_SWITCHES",
300 "SampleAfterValue": "2000003",
301 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
302 "CounterMask": "1",
303 "CounterHTOff": "0,1,2,3,4,5,6,7"
304 } 304 }
305] \ No newline at end of file 305] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/perf/pmu-events/arch/x86/ivytown/memory.json
index 437d98f3e344..4ec94df8d70b 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json
@@ -30,18 +30,6 @@
30 }, 30 },
31 { 31 {
32 "PEBS": "2", 32 "PEBS": "2",
33 "EventCode": "0xCD",
34 "Counter": "3",
35 "UMask": "0x2",
36 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
37 "SampleAfterValue": "2000003",
38 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
39 "PRECISE_STORE": "1",
40 "TakenAlone": "1",
41 "CounterHTOff": "3"
42 },
43 {
44 "PEBS": "2",
45 "PublicDescription": "Loads with latency value being above 4.", 33 "PublicDescription": "Loads with latency value being above 4.",
46 "EventCode": "0xCD", 34 "EventCode": "0xCD",
47 "MSRValue": "0x4", 35 "MSRValue": "0x4",
@@ -153,351 +141,15 @@
153 "CounterHTOff": "3" 141 "CounterHTOff": "3"
154 }, 142 },
155 { 143 {
156 "EventCode": "0xB7, 0xBB", 144 "PEBS": "2",
157 "MSRValue": "0x3fffc00244", 145 "EventCode": "0xCD",
158 "Counter": "0,1,2,3", 146 "Counter": "3",
159 "UMask": "0x1", 147 "UMask": "0x2",
160 "Offcore": "1", 148 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
161 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", 149 "SampleAfterValue": "2000003",
162 "MSRIndex": "0x1a6,0x1a7", 150 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
163 "SampleAfterValue": "100003", 151 "PRECISE_STORE": "1",
164 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC", 152 "TakenAlone": "1",
165 "CounterHTOff": "0,1,2,3" 153 "CounterHTOff": "3"
166 },
167 {
168 "EventCode": "0xB7, 0xBB",
169 "MSRValue": "0x67f800244",
170 "Counter": "0,1,2,3",
171 "UMask": "0x1",
172 "Offcore": "1",
173 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM",
174 "MSRIndex": "0x1a6,0x1a7",
175 "SampleAfterValue": "100003",
176 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram",
177 "CounterHTOff": "0,1,2,3"
178 },
179 {
180 "EventCode": "0xB7, 0xBB",
181 "MSRValue": "0x87f800244",
182 "Counter": "0,1,2,3",
183 "UMask": "0x1",
184 "Offcore": "1",
185 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
186 "MSRIndex": "0x1a6,0x1a7",
187 "SampleAfterValue": "100003",
188 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache",
189 "CounterHTOff": "0,1,2,3"
190 },
191 {
192 "EventCode": "0xB7, 0xBB",
193 "MSRValue": "0x3fffc20091",
194 "Counter": "0,1,2,3",
195 "UMask": "0x1",
196 "Offcore": "1",
197 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
198 "MSRIndex": "0x1a6,0x1a7",
199 "SampleAfterValue": "100003",
200 "BriefDescription": "Counts all demand & prefetch data reads that hits the LLC",
201 "CounterHTOff": "0,1,2,3"
202 },
203 {
204 "EventCode": "0xB7, 0xBB",
205 "MSRValue": "0x3fffc203f7",
206 "Counter": "0,1,2,3",
207 "UMask": "0x1",
208 "Offcore": "1",
209 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
210 "MSRIndex": "0x1a6,0x1a7",
211 "SampleAfterValue": "100003",
212 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC",
213 "CounterHTOff": "0,1,2,3"
214 },
215 {
216 "EventCode": "0xB7, 0xBB",
217 "MSRValue": "0x6004003f7",
218 "Counter": "0,1,2,3",
219 "UMask": "0x1",
220 "Offcore": "1",
221 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
222 "MSRIndex": "0x1a6,0x1a7",
223 "SampleAfterValue": "100003",
224 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram",
225 "CounterHTOff": "0,1,2,3"
226 },
227 {
228 "EventCode": "0xB7, 0xBB",
229 "MSRValue": "0x87f8203f7",
230 "Counter": "0,1,2,3",
231 "UMask": "0x1",
232 "Offcore": "1",
233 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
234 "MSRIndex": "0x1a6,0x1a7",
235 "SampleAfterValue": "100003",
236 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache",
237 "CounterHTOff": "0,1,2,3"
238 },
239 {
240 "EventCode": "0xB7, 0xBB",
241 "MSRValue": "0x107fc003f7",
242 "Counter": "0,1,2,3",
243 "UMask": "0x1",
244 "Offcore": "1",
245 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
246 "MSRIndex": "0x1a6,0x1a7",
247 "SampleAfterValue": "100003",
248 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there",
249 "CounterHTOff": "0,1,2,3"
250 },
251 {
252 "EventCode": "0xB7, 0xBB",
253 "MSRValue": "0x3fffc20004",
254 "Counter": "0,1,2,3",
255 "UMask": "0x1",
256 "Offcore": "1",
257 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
258 "MSRIndex": "0x1a6,0x1a7",
259 "SampleAfterValue": "100003",
260 "BriefDescription": "Counts all demand code reads that miss the LLC",
261 "CounterHTOff": "0,1,2,3"
262 },
263 {
264 "EventCode": "0xB7, 0xBB",
265 "MSRValue": "0x600400004",
266 "Counter": "0,1,2,3",
267 "UMask": "0x1",
268 "Offcore": "1",
269 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
270 "MSRIndex": "0x1a6,0x1a7",
271 "SampleAfterValue": "100003",
272 "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
273 "CounterHTOff": "0,1,2,3"
274 },
275 {
276 "EventCode": "0xB7, 0xBB",
277 "MSRValue": "0x67f800004",
278 "Counter": "0,1,2,3",
279 "UMask": "0x1",
280 "Offcore": "1",
281 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
282 "MSRIndex": "0x1a6,0x1a7",
283 "SampleAfterValue": "100003",
284 "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
285 "CounterHTOff": "0,1,2,3"
286 },
287 {
288 "EventCode": "0xB7, 0xBB",
289 "MSRValue": "0x87f820004",
290 "Counter": "0,1,2,3",
291 "UMask": "0x1",
292 "Offcore": "1",
293 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
294 "MSRIndex": "0x1a6,0x1a7",
295 "SampleAfterValue": "100003",
296 "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
297 "CounterHTOff": "0,1,2,3"
298 },
299 {
300 "EventCode": "0xB7, 0xBB",
301 "MSRValue": "0x107fc00004",
302 "Counter": "0,1,2,3",
303 "UMask": "0x1",
304 "Offcore": "1",
305 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
306 "MSRIndex": "0x1a6,0x1a7",
307 "SampleAfterValue": "100003",
308 "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
309 "CounterHTOff": "0,1,2,3"
310 },
311 {
312 "EventCode": "0xB7, 0xBB",
313 "MSRValue": "0x67fc00001",
314 "Counter": "0,1,2,3",
315 "UMask": "0x1",
316 "Offcore": "1",
317 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
318 "MSRIndex": "0x1a6,0x1a7",
319 "SampleAfterValue": "100003",
320 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
321 "CounterHTOff": "0,1,2,3"
322 },
323 {
324 "EventCode": "0xB7, 0xBB",
325 "MSRValue": "0x3fffc20001",
326 "Counter": "0,1,2,3",
327 "UMask": "0x1",
328 "Offcore": "1",
329 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
330 "MSRIndex": "0x1a6,0x1a7",
331 "SampleAfterValue": "100003",
332 "BriefDescription": "Counts demand data reads that miss in the LLC",
333 "CounterHTOff": "0,1,2,3"
334 },
335 {
336 "EventCode": "0xB7, 0xBB",
337 "MSRValue": "0x600400001",
338 "Counter": "0,1,2,3",
339 "UMask": "0x1",
340 "Offcore": "1",
341 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
342 "MSRIndex": "0x1a6,0x1a7",
343 "SampleAfterValue": "100003",
344 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
345 "CounterHTOff": "0,1,2,3"
346 },
347 {
348 "EventCode": "0xB7, 0xBB",
349 "MSRValue": "0x67f800001",
350 "Counter": "0,1,2,3",
351 "UMask": "0x1",
352 "Offcore": "1",
353 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
354 "MSRIndex": "0x1a6,0x1a7",
355 "SampleAfterValue": "100003",
356 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
357 "CounterHTOff": "0,1,2,3"
358 },
359 {
360 "EventCode": "0xB7, 0xBB",
361 "MSRValue": "0x87f820001",
362 "Counter": "0,1,2,3",
363 "UMask": "0x1",
364 "Offcore": "1",
365 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
366 "MSRIndex": "0x1a6,0x1a7",
367 "SampleAfterValue": "100003",
368 "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
369 "CounterHTOff": "0,1,2,3"
370 },
371 {
372 "EventCode": "0xB7, 0xBB",
373 "MSRValue": "0x107fc00001",
374 "Counter": "0,1,2,3",
375 "UMask": "0x1",
376 "Offcore": "1",
377 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
378 "MSRIndex": "0x1a6,0x1a7",
379 "SampleAfterValue": "100003",
380 "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
381 "CounterHTOff": "0,1,2,3"
382 },
383 {
384 "EventCode": "0xB7, 0xBB",
385 "MSRValue": "0x107fc20002",
386 "Counter": "0,1,2,3",
387 "UMask": "0x1",
388 "Offcore": "1",
389 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
390 "MSRIndex": "0x1a6,0x1a7",
391 "SampleAfterValue": "100003",
392 "BriefDescription": "Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there.",
393 "CounterHTOff": "0,1,2,3"
394 },
395 {
396 "EventCode": "0xB7, 0xBB",
397 "MSRValue": "0x3fffc20040",
398 "Counter": "0,1,2,3",
399 "UMask": "0x1",
400 "Offcore": "1",
401 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
402 "MSRIndex": "0x1a6,0x1a7",
403 "SampleAfterValue": "100003",
404 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
405 "CounterHTOff": "0,1,2,3"
406 },
407 {
408 "EventCode": "0xB7, 0xBB",
409 "MSRValue": "0x67fc00010",
410 "Counter": "0,1,2,3",
411 "UMask": "0x1",
412 "Offcore": "1",
413 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
414 "MSRIndex": "0x1a6,0x1a7",
415 "SampleAfterValue": "100003",
416 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
417 "CounterHTOff": "0,1,2,3"
418 },
419 {
420 "EventCode": "0xB7, 0xBB",
421 "MSRValue": "0x3fffc20010",
422 "Counter": "0,1,2,3",
423 "UMask": "0x1",
424 "Offcore": "1",
425 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
426 "MSRIndex": "0x1a6,0x1a7",
427 "SampleAfterValue": "100003",
428 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
429 "CounterHTOff": "0,1,2,3"
430 },
431 {
432 "EventCode": "0xB7, 0xBB",
433 "MSRValue": "0x600400010",
434 "Counter": "0,1,2,3",
435 "UMask": "0x1",
436 "Offcore": "1",
437 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
438 "MSRIndex": "0x1a6,0x1a7",
439 "SampleAfterValue": "100003",
440 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
441 "CounterHTOff": "0,1,2,3"
442 },
443 {
444 "EventCode": "0xB7, 0xBB",
445 "MSRValue": "0x67f800010",
446 "Counter": "0,1,2,3",
447 "UMask": "0x1",
448 "Offcore": "1",
449 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
450 "MSRIndex": "0x1a6,0x1a7",
451 "SampleAfterValue": "100003",
452 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
453 "CounterHTOff": "0,1,2,3"
454 },
455 {
456 "EventCode": "0xB7, 0xBB",
457 "MSRValue": "0x87f820010",
458 "Counter": "0,1,2,3",
459 "UMask": "0x1",
460 "Offcore": "1",
461 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
462 "MSRIndex": "0x1a6,0x1a7",
463 "SampleAfterValue": "100003",
464 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
465 "CounterHTOff": "0,1,2,3"
466 },
467 {
468 "EventCode": "0xB7, 0xBB",
469 "MSRValue": "0x107fc00010",
470 "Counter": "0,1,2,3",
471 "UMask": "0x1",
472 "Offcore": "1",
473 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
474 "MSRIndex": "0x1a6,0x1a7",
475 "SampleAfterValue": "100003",
476 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
477 "CounterHTOff": "0,1,2,3"
478 },
479 {
480 "EventCode": "0xB7, 0xBB",
481 "MSRValue": "0x3fffc20200",
482 "Counter": "0,1,2,3",
483 "UMask": "0x1",
484 "Offcore": "1",
485 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
486 "MSRIndex": "0x1a6,0x1a7",
487 "SampleAfterValue": "100003",
488 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
489 "CounterHTOff": "0,1,2,3"
490 },
491 {
492 "EventCode": "0xB7, 0xBB",
493 "MSRValue": "0x3fffc20080",
494 "Counter": "0,1,2,3",
495 "UMask": "0x1",
496 "Offcore": "1",
497 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
498 "MSRIndex": "0x1a6,0x1a7",
499 "SampleAfterValue": "100003",
500 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC",
501 "CounterHTOff": "0,1,2,3"
502 } 154 }
503] \ No newline at end of file 155] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf/pmu-events/arch/x86/ivytown/other.json
index 9c2dd0511a32..4eb83ee40412 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/other.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json
@@ -10,16 +10,6 @@
10 "CounterHTOff": "0,1,2,3,4,5,6,7" 10 "CounterHTOff": "0,1,2,3,4,5,6,7"
11 }, 11 },
12 { 12 {
13 "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
14 "EventCode": "0x5C",
15 "Counter": "0,1,2,3",
16 "UMask": "0x2",
17 "EventName": "CPL_CYCLES.RING123",
18 "SampleAfterValue": "2000003",
19 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
21 },
22 {
23 "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", 13 "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",
24 "EventCode": "0x5C", 14 "EventCode": "0x5C",
25 "Counter": "0,1,2,3", 15 "Counter": "0,1,2,3",
@@ -32,6 +22,16 @@
32 "CounterHTOff": "0,1,2,3,4,5,6,7" 22 "CounterHTOff": "0,1,2,3,4,5,6,7"
33 }, 23 },
34 { 24 {
25 "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
26 "EventCode": "0x5C",
27 "Counter": "0,1,2,3",
28 "UMask": "0x2",
29 "EventName": "CPL_CYCLES.RING123",
30 "SampleAfterValue": "2000003",
31 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
32 "CounterHTOff": "0,1,2,3,4,5,6,7"
33 },
34 {
35 "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", 35 "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
36 "EventCode": "0x63", 36 "EventCode": "0x63",
37 "Counter": "0,1,2,3", 37 "Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
index 2145c28193f7..0afbfd95ea30 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
@@ -1,30 +1,41 @@
1[ 1[
2 { 2 {
3 "EventCode": "0x00", 3 "EventCode": "0x00",
4 "Counter": "Fixed counter 1", 4 "Counter": "Fixed counter 0",
5 "UMask": "0x1", 5 "UMask": "0x1",
6 "EventName": "INST_RETIRED.ANY", 6 "EventName": "INST_RETIRED.ANY",
7 "SampleAfterValue": "2000003", 7 "SampleAfterValue": "2000003",
8 "BriefDescription": "Instructions retired from execution.", 8 "BriefDescription": "Instructions retired from execution.",
9 "CounterHTOff": "Fixed counter 1" 9 "CounterHTOff": "Fixed counter 0"
10 }, 10 },
11 { 11 {
12 "EventCode": "0x00", 12 "EventCode": "0x00",
13 "Counter": "Fixed counter 2", 13 "Counter": "Fixed counter 1",
14 "UMask": "0x2", 14 "UMask": "0x2",
15 "EventName": "CPU_CLK_UNHALTED.THREAD", 15 "EventName": "CPU_CLK_UNHALTED.THREAD",
16 "SampleAfterValue": "2000003", 16 "SampleAfterValue": "2000003",
17 "BriefDescription": "Core cycles when the thread is not in halt state.", 17 "BriefDescription": "Core cycles when the thread is not in halt state.",
18 "CounterHTOff": "Fixed counter 2" 18 "CounterHTOff": "Fixed counter 1"
19 }, 19 },
20 { 20 {
21 "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
21 "EventCode": "0x00", 22 "EventCode": "0x00",
22 "Counter": "Fixed counter 3", 23 "Counter": "Fixed counter 1",
24 "UMask": "0x2",
25 "AnyThread": "1",
26 "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
27 "SampleAfterValue": "2000003",
28 "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
29 "CounterHTOff": "Fixed counter 1"
30 },
31 {
32 "EventCode": "0x00",
33 "Counter": "Fixed counter 2",
23 "UMask": "0x3", 34 "UMask": "0x3",
24 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 35 "EventName": "CPU_CLK_UNHALTED.REF_TSC",
25 "SampleAfterValue": "2000003", 36 "SampleAfterValue": "2000003",
26 "BriefDescription": "Reference cycles when the core is not in halt state.", 37 "BriefDescription": "Reference cycles when the core is not in halt state.",
27 "CounterHTOff": "Fixed counter 3" 38 "CounterHTOff": "Fixed counter 2"
28 }, 39 },
29 { 40 {
30 "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", 41 "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.",
@@ -78,6 +89,17 @@
78 "CounterHTOff": "0,1,2,3,4,5,6,7" 89 "CounterHTOff": "0,1,2,3,4,5,6,7"
79 }, 90 },
80 { 91 {
92 "EventCode": "0x0D",
93 "Counter": "0,1,2,3",
94 "UMask": "0x3",
95 "AnyThread": "1",
96 "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
97 "SampleAfterValue": "2000003",
98 "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
99 "CounterMask": "1",
100 "CounterHTOff": "0,1,2,3,4,5,6,7"
101 },
102 {
81 "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", 103 "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.",
82 "EventCode": "0x0E", 104 "EventCode": "0x0E",
83 "Counter": "0,1,2,3", 105 "Counter": "0,1,2,3",
@@ -175,6 +197,17 @@
175 "CounterHTOff": "0,1,2,3,4,5,6,7" 197 "CounterHTOff": "0,1,2,3,4,5,6,7"
176 }, 198 },
177 { 199 {
200 "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
201 "EventCode": "0x3C",
202 "Counter": "0,1,2,3",
203 "UMask": "0x0",
204 "AnyThread": "1",
205 "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
206 "SampleAfterValue": "2000003",
207 "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
208 "CounterHTOff": "0,1,2,3,4,5,6,7"
209 },
210 {
178 "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", 211 "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
179 "EventCode": "0x3C", 212 "EventCode": "0x3C",
180 "Counter": "0,1,2,3", 213 "Counter": "0,1,2,3",
@@ -187,6 +220,36 @@
187 { 220 {
188 "EventCode": "0x3C", 221 "EventCode": "0x3C",
189 "Counter": "0,1,2,3", 222 "Counter": "0,1,2,3",
223 "UMask": "0x1",
224 "AnyThread": "1",
225 "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
226 "SampleAfterValue": "2000003",
227 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
228 "CounterHTOff": "0,1,2,3,4,5,6,7"
229 },
230 {
231 "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
232 "EventCode": "0x3C",
233 "Counter": "0,1,2,3",
234 "UMask": "0x1",
235 "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
236 "SampleAfterValue": "2000003",
237 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
238 "CounterHTOff": "0,1,2,3,4,5,6,7"
239 },
240 {
241 "EventCode": "0x3C",
242 "Counter": "0,1,2,3",
243 "UMask": "0x1",
244 "AnyThread": "1",
245 "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
246 "SampleAfterValue": "2000003",
247 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
248 "CounterHTOff": "0,1,2,3,4,5,6,7"
249 },
250 {
251 "EventCode": "0x3C",
252 "Counter": "0,1,2,3",
190 "UMask": "0x2", 253 "UMask": "0x2",
191 "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 254 "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
192 "SampleAfterValue": "2000003", 255 "SampleAfterValue": "2000003",
@@ -194,6 +257,15 @@
194 "CounterHTOff": "0,1,2,3" 257 "CounterHTOff": "0,1,2,3"
195 }, 258 },
196 { 259 {
260 "EventCode": "0x3C",
261 "Counter": "0,1,2,3",
262 "UMask": "0x2",
263 "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
264 "SampleAfterValue": "2000003",
265 "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
266 "CounterHTOff": "0,1,2,3,4,5,6,7"
267 },
268 {
197 "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", 269 "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
198 "EventCode": "0x4C", 270 "EventCode": "0x4C",
199 "Counter": "0,1,2,3", 271 "Counter": "0,1,2,3",
@@ -216,37 +288,37 @@
216 { 288 {
217 "EventCode": "0x58", 289 "EventCode": "0x58",
218 "Counter": "0,1,2,3", 290 "Counter": "0,1,2,3",
219 "UMask": "0x4", 291 "UMask": "0x1",
220 "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", 292 "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
221 "SampleAfterValue": "1000003", 293 "SampleAfterValue": "1000003",
222 "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", 294 "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
223 "CounterHTOff": "0,1,2,3,4,5,6,7" 295 "CounterHTOff": "0,1,2,3,4,5,6,7"
224 }, 296 },
225 { 297 {
226 "EventCode": "0x58", 298 "EventCode": "0x58",
227 "Counter": "0,1,2,3", 299 "Counter": "0,1,2,3",
228 "UMask": "0x8", 300 "UMask": "0x2",
229 "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", 301 "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
230 "SampleAfterValue": "1000003", 302 "SampleAfterValue": "1000003",
231 "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", 303 "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
232 "CounterHTOff": "0,1,2,3,4,5,6,7" 304 "CounterHTOff": "0,1,2,3,4,5,6,7"
233 }, 305 },
234 { 306 {
235 "EventCode": "0x58", 307 "EventCode": "0x58",
236 "Counter": "0,1,2,3", 308 "Counter": "0,1,2,3",
237 "UMask": "0x1", 309 "UMask": "0x4",
238 "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", 310 "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
239 "SampleAfterValue": "1000003", 311 "SampleAfterValue": "1000003",
240 "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", 312 "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
241 "CounterHTOff": "0,1,2,3,4,5,6,7" 313 "CounterHTOff": "0,1,2,3,4,5,6,7"
242 }, 314 },
243 { 315 {
244 "EventCode": "0x58", 316 "EventCode": "0x58",
245 "Counter": "0,1,2,3", 317 "Counter": "0,1,2,3",
246 "UMask": "0x2", 318 "UMask": "0x8",
247 "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", 319 "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
248 "SampleAfterValue": "1000003", 320 "SampleAfterValue": "1000003",
249 "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", 321 "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
250 "CounterHTOff": "0,1,2,3,4,5,6,7" 322 "CounterHTOff": "0,1,2,3,4,5,6,7"
251 }, 323 },
252 { 324 {
@@ -260,6 +332,18 @@
260 "CounterHTOff": "0,1,2,3,4,5,6,7" 332 "CounterHTOff": "0,1,2,3,4,5,6,7"
261 }, 333 },
262 { 334 {
335 "EventCode": "0x5E",
336 "Invert": "1",
337 "Counter": "0,1,2,3",
338 "UMask": "0x1",
339 "EdgeDetect": "1",
340 "EventName": "RS_EVENTS.EMPTY_END",
341 "SampleAfterValue": "200003",
342 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
343 "CounterMask": "1",
344 "CounterHTOff": "0,1,2,3,4,5,6,7"
345 },
346 {
263 "EventCode": "0x87", 347 "EventCode": "0x87",
264 "Counter": "0,1,2,3", 348 "Counter": "0,1,2,3",
265 "UMask": "0x1", 349 "UMask": "0x1",
@@ -498,118 +582,118 @@
498 "CounterHTOff": "0,1,2,3,4,5,6,7" 582 "CounterHTOff": "0,1,2,3,4,5,6,7"
499 }, 583 },
500 { 584 {
501 "PublicDescription": "Cycles which a Uop is dispatched on port 1.", 585 "PublicDescription": "Cycles per core when uops are dispatched to port 0.",
502 "EventCode": "0xA1", 586 "EventCode": "0xA1",
503 "Counter": "0,1,2,3", 587 "Counter": "0,1,2,3",
504 "UMask": "0x2", 588 "UMask": "0x1",
505 "EventName": "UOPS_DISPATCHED_PORT.PORT_1", 589 "AnyThread": "1",
590 "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
506 "SampleAfterValue": "2000003", 591 "SampleAfterValue": "2000003",
507 "BriefDescription": "Cycles per thread when uops are dispatched to port 1", 592 "BriefDescription": "Cycles per core when uops are dispatched to port 0",
508 "CounterHTOff": "0,1,2,3,4,5,6,7" 593 "CounterHTOff": "0,1,2,3,4,5,6,7"
509 }, 594 },
510 { 595 {
511 "PublicDescription": "Cycles which a Uop is dispatched on port 4.", 596 "PublicDescription": "Cycles which a Uop is dispatched on port 1.",
512 "EventCode": "0xA1", 597 "EventCode": "0xA1",
513 "Counter": "0,1,2,3", 598 "Counter": "0,1,2,3",
514 "UMask": "0x40", 599 "UMask": "0x2",
515 "EventName": "UOPS_DISPATCHED_PORT.PORT_4", 600 "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
516 "SampleAfterValue": "2000003", 601 "SampleAfterValue": "2000003",
517 "BriefDescription": "Cycles per thread when uops are dispatched to port 4", 602 "BriefDescription": "Cycles per thread when uops are dispatched to port 1",
518 "CounterHTOff": "0,1,2,3,4,5,6,7" 603 "CounterHTOff": "0,1,2,3,4,5,6,7"
519 }, 604 },
520 { 605 {
521 "PublicDescription": "Cycles which a Uop is dispatched on port 5.", 606 "PublicDescription": "Cycles per core when uops are dispatched to port 1.",
522 "EventCode": "0xA1", 607 "EventCode": "0xA1",
523 "Counter": "0,1,2,3", 608 "Counter": "0,1,2,3",
524 "UMask": "0x80", 609 "UMask": "0x2",
525 "EventName": "UOPS_DISPATCHED_PORT.PORT_5", 610 "AnyThread": "1",
611 "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
526 "SampleAfterValue": "2000003", 612 "SampleAfterValue": "2000003",
527 "BriefDescription": "Cycles per thread when uops are dispatched to port 5", 613 "BriefDescription": "Cycles per core when uops are dispatched to port 1",
528 "CounterHTOff": "0,1,2,3,4,5,6,7" 614 "CounterHTOff": "0,1,2,3,4,5,6,7"
529 }, 615 },
530 { 616 {
531 "PublicDescription": "Cycles per core when uops are dispatched to port 0.", 617 "PublicDescription": "Cycles which a Uop is dispatched on port 2.",
532 "EventCode": "0xA1", 618 "EventCode": "0xA1",
533 "Counter": "0,1,2,3", 619 "Counter": "0,1,2,3",
534 "UMask": "0x1", 620 "UMask": "0xc",
535 "AnyThread": "1", 621 "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
536 "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
537 "SampleAfterValue": "2000003", 622 "SampleAfterValue": "2000003",
538 "BriefDescription": "Cycles per core when uops are dispatched to port 0", 623 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",
539 "CounterHTOff": "0,1,2,3,4,5,6,7" 624 "CounterHTOff": "0,1,2,3,4,5,6,7"
540 }, 625 },
541 { 626 {
542 "PublicDescription": "Cycles per core when uops are dispatched to port 1.",
543 "EventCode": "0xA1", 627 "EventCode": "0xA1",
544 "Counter": "0,1,2,3", 628 "Counter": "0,1,2,3",
545 "UMask": "0x2", 629 "UMask": "0xc",
546 "AnyThread": "1", 630 "AnyThread": "1",
547 "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", 631 "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
548 "SampleAfterValue": "2000003", 632 "SampleAfterValue": "2000003",
549 "BriefDescription": "Cycles per core when uops are dispatched to port 1", 633 "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).",
550 "CounterHTOff": "0,1,2,3,4,5,6,7" 634 "CounterHTOff": "0,1,2,3,4,5,6,7"
551 }, 635 },
552 { 636 {
553 "PublicDescription": "Cycles per core when uops are dispatched to port 4.", 637 "PublicDescription": "Cycles which a Uop is dispatched on port 3.",
554 "EventCode": "0xA1", 638 "EventCode": "0xA1",
555 "Counter": "0,1,2,3", 639 "Counter": "0,1,2,3",
556 "UMask": "0x40", 640 "UMask": "0x30",
557 "AnyThread": "1", 641 "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
558 "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
559 "SampleAfterValue": "2000003", 642 "SampleAfterValue": "2000003",
560 "BriefDescription": "Cycles per core when uops are dispatched to port 4", 643 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
561 "CounterHTOff": "0,1,2,3,4,5,6,7" 644 "CounterHTOff": "0,1,2,3,4,5,6,7"
562 }, 645 },
563 { 646 {
564 "PublicDescription": "Cycles per core when uops are dispatched to port 5.", 647 "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
565 "EventCode": "0xA1", 648 "EventCode": "0xA1",
566 "Counter": "0,1,2,3", 649 "Counter": "0,1,2,3",
567 "UMask": "0x80", 650 "UMask": "0x30",
568 "AnyThread": "1", 651 "AnyThread": "1",
569 "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", 652 "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
570 "SampleAfterValue": "2000003", 653 "SampleAfterValue": "2000003",
571 "BriefDescription": "Cycles per core when uops are dispatched to port 5", 654 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
572 "CounterHTOff": "0,1,2,3,4,5,6,7" 655 "CounterHTOff": "0,1,2,3,4,5,6,7"
573 }, 656 },
574 { 657 {
575 "PublicDescription": "Cycles which a Uop is dispatched on port 2.", 658 "PublicDescription": "Cycles which a Uop is dispatched on port 4.",
576 "EventCode": "0xA1", 659 "EventCode": "0xA1",
577 "Counter": "0,1,2,3", 660 "Counter": "0,1,2,3",
578 "UMask": "0xc", 661 "UMask": "0x40",
579 "EventName": "UOPS_DISPATCHED_PORT.PORT_2", 662 "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
580 "SampleAfterValue": "2000003", 663 "SampleAfterValue": "2000003",
581 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", 664 "BriefDescription": "Cycles per thread when uops are dispatched to port 4",
582 "CounterHTOff": "0,1,2,3,4,5,6,7" 665 "CounterHTOff": "0,1,2,3,4,5,6,7"
583 }, 666 },
584 { 667 {
585 "PublicDescription": "Cycles which a Uop is dispatched on port 3.", 668 "PublicDescription": "Cycles per core when uops are dispatched to port 4.",
586 "EventCode": "0xA1", 669 "EventCode": "0xA1",
587 "Counter": "0,1,2,3", 670 "Counter": "0,1,2,3",
588 "UMask": "0x30", 671 "UMask": "0x40",
589 "EventName": "UOPS_DISPATCHED_PORT.PORT_3", 672 "AnyThread": "1",
673 "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
590 "SampleAfterValue": "2000003", 674 "SampleAfterValue": "2000003",
591 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", 675 "BriefDescription": "Cycles per core when uops are dispatched to port 4",
592 "CounterHTOff": "0,1,2,3,4,5,6,7" 676 "CounterHTOff": "0,1,2,3,4,5,6,7"
593 }, 677 },
594 { 678 {
679 "PublicDescription": "Cycles which a Uop is dispatched on port 5.",
595 "EventCode": "0xA1", 680 "EventCode": "0xA1",
596 "Counter": "0,1,2,3", 681 "Counter": "0,1,2,3",
597 "UMask": "0xc", 682 "UMask": "0x80",
598 "AnyThread": "1", 683 "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
599 "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
600 "SampleAfterValue": "2000003", 684 "SampleAfterValue": "2000003",
601 "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", 685 "BriefDescription": "Cycles per thread when uops are dispatched to port 5",
602 "CounterHTOff": "0,1,2,3,4,5,6,7" 686 "CounterHTOff": "0,1,2,3,4,5,6,7"
603 }, 687 },
604 { 688 {
605 "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", 689 "PublicDescription": "Cycles per core when uops are dispatched to port 5.",
606 "EventCode": "0xA1", 690 "EventCode": "0xA1",
607 "Counter": "0,1,2,3", 691 "Counter": "0,1,2,3",
608 "UMask": "0x30", 692 "UMask": "0x80",
609 "AnyThread": "1", 693 "AnyThread": "1",
610 "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", 694 "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
611 "SampleAfterValue": "2000003", 695 "SampleAfterValue": "2000003",
612 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", 696 "BriefDescription": "Cycles per core when uops are dispatched to port 5",
613 "CounterHTOff": "0,1,2,3,4,5,6,7" 697 "CounterHTOff": "0,1,2,3,4,5,6,7"
614 }, 698 },
615 { 699 {
@@ -662,15 +746,14 @@
662 "CounterHTOff": "0,1,2,3,4,5,6,7" 746 "CounterHTOff": "0,1,2,3,4,5,6,7"
663 }, 747 },
664 { 748 {
665 "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.",
666 "EventCode": "0xA3", 749 "EventCode": "0xA3",
667 "Counter": "2", 750 "Counter": "0,1,2,3",
668 "UMask": "0x8", 751 "UMask": "0x1",
669 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", 752 "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
670 "SampleAfterValue": "2000003", 753 "SampleAfterValue": "2000003",
671 "BriefDescription": "Cycles with pending L1 cache miss loads.", 754 "BriefDescription": "Cycles while L2 cache miss load* is outstanding.",
672 "CounterMask": "8", 755 "CounterMask": "1",
673 "CounterHTOff": "2" 756 "CounterHTOff": "0,1,2,3,4,5,6,7"
674 }, 757 },
675 { 758 {
676 "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", 759 "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.",
@@ -684,13 +767,33 @@
684 "CounterHTOff": "0,1,2,3" 767 "CounterHTOff": "0,1,2,3"
685 }, 768 },
686 { 769 {
770 "EventCode": "0xA3",
771 "Counter": "0,1,2,3",
772 "UMask": "0x2",
773 "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
774 "SampleAfterValue": "2000003",
775 "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
776 "CounterMask": "2",
777 "CounterHTOff": "0,1,2,3"
778 },
779 {
687 "PublicDescription": "Total execution stalls.", 780 "PublicDescription": "Total execution stalls.",
688 "EventCode": "0xA3", 781 "EventCode": "0xA3",
689 "Counter": "0,1,2,3", 782 "Counter": "0,1,2,3",
690 "UMask": "0x4", 783 "UMask": "0x4",
691 "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", 784 "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
692 "SampleAfterValue": "2000003", 785 "SampleAfterValue": "2000003",
693 "BriefDescription": "Total execution stalls", 786 "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
787 "CounterMask": "4",
788 "CounterHTOff": "0,1,2,3"
789 },
790 {
791 "EventCode": "0xA3",
792 "Counter": "0,1,2,3",
793 "UMask": "0x4",
794 "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
795 "SampleAfterValue": "2000003",
796 "BriefDescription": "Total execution stalls.",
694 "CounterMask": "4", 797 "CounterMask": "4",
695 "CounterHTOff": "0,1,2,3" 798 "CounterHTOff": "0,1,2,3"
696 }, 799 },
@@ -708,6 +811,16 @@
708 { 811 {
709 "EventCode": "0xA3", 812 "EventCode": "0xA3",
710 "Counter": "0,1,2,3", 813 "Counter": "0,1,2,3",
814 "UMask": "0x5",
815 "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
816 "SampleAfterValue": "2000003",
817 "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",
818 "CounterMask": "5",
819 "CounterHTOff": "0,1,2,3"
820 },
821 {
822 "EventCode": "0xA3",
823 "Counter": "0,1,2,3",
711 "UMask": "0x6", 824 "UMask": "0x6",
712 "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", 825 "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
713 "SampleAfterValue": "2000003", 826 "SampleAfterValue": "2000003",
@@ -716,6 +829,37 @@
716 "CounterHTOff": "0,1,2,3" 829 "CounterHTOff": "0,1,2,3"
717 }, 830 },
718 { 831 {
832 "EventCode": "0xA3",
833 "Counter": "0,1,2,3",
834 "UMask": "0x6",
835 "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
836 "SampleAfterValue": "2000003",
837 "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
838 "CounterMask": "6",
839 "CounterHTOff": "0,1,2,3"
840 },
841 {
842 "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.",
843 "EventCode": "0xA3",
844 "Counter": "2",
845 "UMask": "0x8",
846 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
847 "SampleAfterValue": "2000003",
848 "BriefDescription": "Cycles with pending L1 cache miss loads.",
849 "CounterMask": "8",
850 "CounterHTOff": "2"
851 },
852 {
853 "EventCode": "0xA3",
854 "Counter": "2",
855 "UMask": "0x8",
856 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
857 "SampleAfterValue": "2000003",
858 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
859 "CounterMask": "8",
860 "CounterHTOff": "2"
861 },
862 {
719 "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", 863 "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.",
720 "EventCode": "0xA3", 864 "EventCode": "0xA3",
721 "Counter": "2", 865 "Counter": "2",
@@ -727,6 +871,16 @@
727 "CounterHTOff": "2" 871 "CounterHTOff": "2"
728 }, 872 },
729 { 873 {
874 "EventCode": "0xA3",
875 "Counter": "2",
876 "UMask": "0xc",
877 "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
878 "SampleAfterValue": "2000003",
879 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
880 "CounterMask": "12",
881 "CounterHTOff": "2"
882 },
883 {
730 "EventCode": "0xA8", 884 "EventCode": "0xA8",
731 "Counter": "0,1,2,3", 885 "Counter": "0,1,2,3",
732 "UMask": "0x1", 886 "UMask": "0x1",
@@ -747,6 +901,17 @@
747 "CounterHTOff": "0,1,2,3,4,5,6,7" 901 "CounterHTOff": "0,1,2,3,4,5,6,7"
748 }, 902 },
749 { 903 {
904 "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
905 "EventCode": "0xA8",
906 "Counter": "0,1,2,3",
907 "UMask": "0x1",
908 "EventName": "LSD.CYCLES_4_UOPS",
909 "SampleAfterValue": "2000003",
910 "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
911 "CounterMask": "4",
912 "CounterHTOff": "0,1,2,3,4,5,6,7"
913 },
914 {
750 "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", 915 "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.",
751 "EventCode": "0xB1", 916 "EventCode": "0xB1",
752 "Counter": "0,1,2,3", 917 "Counter": "0,1,2,3",
@@ -757,6 +922,61 @@
757 "CounterHTOff": "0,1,2,3,4,5,6,7" 922 "CounterHTOff": "0,1,2,3,4,5,6,7"
758 }, 923 },
759 { 924 {
925 "EventCode": "0xB1",
926 "Invert": "1",
927 "Counter": "0,1,2,3",
928 "UMask": "0x1",
929 "EventName": "UOPS_EXECUTED.STALL_CYCLES",
930 "SampleAfterValue": "2000003",
931 "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
932 "CounterMask": "1",
933 "CounterHTOff": "0,1,2,3"
934 },
935 {
936 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
937 "EventCode": "0xB1",
938 "Counter": "0,1,2,3",
939 "UMask": "0x1",
940 "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
941 "SampleAfterValue": "2000003",
942 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
943 "CounterMask": "1",
944 "CounterHTOff": "0,1,2,3,4,5,6,7"
945 },
946 {
947 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
948 "EventCode": "0xB1",
949 "Counter": "0,1,2,3",
950 "UMask": "0x1",
951 "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
952 "SampleAfterValue": "2000003",
953 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
954 "CounterMask": "2",
955 "CounterHTOff": "0,1,2,3,4,5,6,7"
956 },
957 {
958 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
959 "EventCode": "0xB1",
960 "Counter": "0,1,2,3",
961 "UMask": "0x1",
962 "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
963 "SampleAfterValue": "2000003",
964 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
965 "CounterMask": "3",
966 "CounterHTOff": "0,1,2,3,4,5,6,7"
967 },
968 {
969 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
970 "EventCode": "0xB1",
971 "Counter": "0,1,2,3",
972 "UMask": "0x1",
973 "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
974 "SampleAfterValue": "2000003",
975 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
976 "CounterMask": "4",
977 "CounterHTOff": "0,1,2,3,4,5,6,7"
978 },
979 {
760 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", 980 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
761 "EventCode": "0xB1", 981 "EventCode": "0xB1",
762 "Counter": "0,1,2,3", 982 "Counter": "0,1,2,3",
@@ -767,15 +987,59 @@
767 "CounterHTOff": "0,1,2,3,4,5,6,7" 987 "CounterHTOff": "0,1,2,3,4,5,6,7"
768 }, 988 },
769 { 989 {
990 "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
770 "EventCode": "0xB1", 991 "EventCode": "0xB1",
771 "Invert": "1",
772 "Counter": "0,1,2,3", 992 "Counter": "0,1,2,3",
773 "UMask": "0x1", 993 "UMask": "0x2",
774 "EventName": "UOPS_EXECUTED.STALL_CYCLES", 994 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
775 "SampleAfterValue": "2000003", 995 "SampleAfterValue": "2000003",
776 "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", 996 "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
777 "CounterMask": "1", 997 "CounterMask": "1",
778 "CounterHTOff": "0,1,2,3" 998 "CounterHTOff": "0,1,2,3,4,5,6,7"
999 },
1000 {
1001 "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1002 "EventCode": "0xB1",
1003 "Counter": "0,1,2,3",
1004 "UMask": "0x2",
1005 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
1006 "SampleAfterValue": "2000003",
1007 "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
1008 "CounterMask": "2",
1009 "CounterHTOff": "0,1,2,3,4,5,6,7"
1010 },
1011 {
1012 "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1013 "EventCode": "0xB1",
1014 "Counter": "0,1,2,3",
1015 "UMask": "0x2",
1016 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
1017 "SampleAfterValue": "2000003",
1018 "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
1019 "CounterMask": "3",
1020 "CounterHTOff": "0,1,2,3,4,5,6,7"
1021 },
1022 {
1023 "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1024 "EventCode": "0xB1",
1025 "Counter": "0,1,2,3",
1026 "UMask": "0x2",
1027 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
1028 "SampleAfterValue": "2000003",
1029 "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
1030 "CounterMask": "4",
1031 "CounterHTOff": "0,1,2,3,4,5,6,7"
1032 },
1033 {
1034 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1035 "EventCode": "0xB1",
1036 "Invert": "1",
1037 "Counter": "0,1,2,3",
1038 "UMask": "0x2",
1039 "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
1040 "SampleAfterValue": "2000003",
1041 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
1042 "CounterHTOff": "0,1,2,3,4,5,6,7"
779 }, 1043 },
780 { 1044 {
781 "PublicDescription": "Number of instructions at retirement.", 1045 "PublicDescription": "Number of instructions at retirement.",
@@ -809,24 +1073,12 @@
809 }, 1073 },
810 { 1074 {
811 "PEBS": "1", 1075 "PEBS": "1",
812 "PublicDescription": "Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles.",
813 "EventCode": "0xC2", 1076 "EventCode": "0xC2",
814 "Counter": "0,1,2,3", 1077 "Counter": "0,1,2,3",
815 "UMask": "0x1", 1078 "UMask": "0x1",
816 "EventName": "UOPS_RETIRED.ALL", 1079 "EventName": "UOPS_RETIRED.ALL",
817 "SampleAfterValue": "2000003", 1080 "SampleAfterValue": "2000003",
818 "BriefDescription": "Actually retired uops. ", 1081 "BriefDescription": "Retired uops.",
819 "CounterHTOff": "0,1,2,3,4,5,6,7"
820 },
821 {
822 "PEBS": "1",
823 "PublicDescription": "Counts the number of retirement slots used each cycle.",
824 "EventCode": "0xC2",
825 "Counter": "0,1,2,3",
826 "UMask": "0x2",
827 "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
828 "SampleAfterValue": "2000003",
829 "BriefDescription": "Retirement slots used. ",
830 "CounterHTOff": "0,1,2,3,4,5,6,7" 1082 "CounterHTOff": "0,1,2,3,4,5,6,7"
831 }, 1083 },
832 { 1084 {
@@ -864,6 +1116,27 @@
864 "CounterHTOff": "0,1,2,3" 1116 "CounterHTOff": "0,1,2,3"
865 }, 1117 },
866 { 1118 {
1119 "PEBS": "1",
1120 "EventCode": "0xC2",
1121 "Counter": "0,1,2,3",
1122 "UMask": "0x2",
1123 "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
1124 "SampleAfterValue": "2000003",
1125 "BriefDescription": "Retirement slots used.",
1126 "CounterHTOff": "0,1,2,3,4,5,6,7"
1127 },
1128 {
1129 "EventCode": "0xC3",
1130 "Counter": "0,1,2,3",
1131 "UMask": "0x1",
1132 "EdgeDetect": "1",
1133 "EventName": "MACHINE_CLEARS.COUNT",
1134 "SampleAfterValue": "100003",
1135 "BriefDescription": "Number of machine clears (nukes) of any type.",
1136 "CounterMask": "1",
1137 "CounterHTOff": "0,1,2,3,4,5,6,7"
1138 },
1139 {
867 "PublicDescription": "Number of self-modifying-code machine clears detected.", 1140 "PublicDescription": "Number of self-modifying-code machine clears detected.",
868 "EventCode": "0xC3", 1141 "EventCode": "0xC3",
869 "Counter": "0,1,2,3", 1142 "Counter": "0,1,2,3",
@@ -880,50 +1153,67 @@
880 "UMask": "0x20", 1153 "UMask": "0x20",
881 "EventName": "MACHINE_CLEARS.MASKMOV", 1154 "EventName": "MACHINE_CLEARS.MASKMOV",
882 "SampleAfterValue": "100003", 1155 "SampleAfterValue": "100003",
883 "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ", 1156 "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
1157 "CounterHTOff": "0,1,2,3,4,5,6,7"
1158 },
1159 {
1160 "PublicDescription": "Branch instructions at retirement.",
1161 "EventCode": "0xC4",
1162 "Counter": "0,1,2,3",
1163 "UMask": "0x0",
1164 "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
1165 "SampleAfterValue": "400009",
1166 "BriefDescription": "All (macro) branch instructions retired.",
884 "CounterHTOff": "0,1,2,3,4,5,6,7" 1167 "CounterHTOff": "0,1,2,3,4,5,6,7"
885 }, 1168 },
886 { 1169 {
887 "PEBS": "1", 1170 "PEBS": "1",
888 "PublicDescription": "Counts the number of conditional branch instructions retired.",
889 "EventCode": "0xC4", 1171 "EventCode": "0xC4",
890 "Counter": "0,1,2,3", 1172 "Counter": "0,1,2,3",
891 "UMask": "0x1", 1173 "UMask": "0x1",
892 "EventName": "BR_INST_RETIRED.CONDITIONAL", 1174 "EventName": "BR_INST_RETIRED.CONDITIONAL",
893 "SampleAfterValue": "400009", 1175 "SampleAfterValue": "400009",
894 "BriefDescription": "Conditional branch instructions retired. ", 1176 "BriefDescription": "Conditional branch instructions retired.",
895 "CounterHTOff": "0,1,2,3,4,5,6,7" 1177 "CounterHTOff": "0,1,2,3,4,5,6,7"
896 }, 1178 },
897 { 1179 {
898 "PEBS": "1", 1180 "PEBS": "1",
899 "PublicDescription": "Direct and indirect near call instructions retired.",
900 "EventCode": "0xC4", 1181 "EventCode": "0xC4",
901 "Counter": "0,1,2,3", 1182 "Counter": "0,1,2,3",
902 "UMask": "0x2", 1183 "UMask": "0x2",
903 "EventName": "BR_INST_RETIRED.NEAR_CALL", 1184 "EventName": "BR_INST_RETIRED.NEAR_CALL",
904 "SampleAfterValue": "100007", 1185 "SampleAfterValue": "100007",
905 "BriefDescription": "Direct and indirect near call instructions retired. ", 1186 "BriefDescription": "Direct and indirect near call instructions retired.",
906 "CounterHTOff": "0,1,2,3,4,5,6,7" 1187 "CounterHTOff": "0,1,2,3,4,5,6,7"
907 }, 1188 },
908 { 1189 {
909 "PublicDescription": "Branch instructions at retirement.", 1190 "PEBS": "1",
910 "EventCode": "0xC4", 1191 "EventCode": "0xC4",
911 "Counter": "0,1,2,3", 1192 "Counter": "0,1,2,3",
912 "UMask": "0x0", 1193 "UMask": "0x2",
913 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 1194 "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
1195 "SampleAfterValue": "100007",
1196 "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
1197 "CounterHTOff": "0,1,2,3,4,5,6,7"
1198 },
1199 {
1200 "PEBS": "2",
1201 "EventCode": "0xC4",
1202 "Counter": "0,1,2,3",
1203 "UMask": "0x4",
1204 "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
914 "SampleAfterValue": "400009", 1205 "SampleAfterValue": "400009",
915 "BriefDescription": "All (macro) branch instructions retired.", 1206 "BriefDescription": "All (macro) branch instructions retired.",
916 "CounterHTOff": "0,1,2,3,4,5,6,7" 1207 "CounterHTOff": "0,1,2,3"
917 }, 1208 },
918 { 1209 {
919 "PEBS": "1", 1210 "PEBS": "1",
920 "PublicDescription": "Counts the number of near return instructions retired.",
921 "EventCode": "0xC4", 1211 "EventCode": "0xC4",
922 "Counter": "0,1,2,3", 1212 "Counter": "0,1,2,3",
923 "UMask": "0x8", 1213 "UMask": "0x8",
924 "EventName": "BR_INST_RETIRED.NEAR_RETURN", 1214 "EventName": "BR_INST_RETIRED.NEAR_RETURN",
925 "SampleAfterValue": "100007", 1215 "SampleAfterValue": "100007",
926 "BriefDescription": "Return instructions retired. ", 1216 "BriefDescription": "Return instructions retired.",
927 "CounterHTOff": "0,1,2,3,4,5,6,7" 1217 "CounterHTOff": "0,1,2,3,4,5,6,7"
928 }, 1218 },
929 { 1219 {
@@ -933,18 +1223,17 @@
933 "UMask": "0x10", 1223 "UMask": "0x10",
934 "EventName": "BR_INST_RETIRED.NOT_TAKEN", 1224 "EventName": "BR_INST_RETIRED.NOT_TAKEN",
935 "SampleAfterValue": "400009", 1225 "SampleAfterValue": "400009",
936 "BriefDescription": "Not taken branch instructions retired. ", 1226 "BriefDescription": "Not taken branch instructions retired.",
937 "CounterHTOff": "0,1,2,3,4,5,6,7" 1227 "CounterHTOff": "0,1,2,3,4,5,6,7"
938 }, 1228 },
939 { 1229 {
940 "PEBS": "1", 1230 "PEBS": "1",
941 "PublicDescription": "Number of near taken branches retired.",
942 "EventCode": "0xC4", 1231 "EventCode": "0xC4",
943 "Counter": "0,1,2,3", 1232 "Counter": "0,1,2,3",
944 "UMask": "0x20", 1233 "UMask": "0x20",
945 "EventName": "BR_INST_RETIRED.NEAR_TAKEN", 1234 "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
946 "SampleAfterValue": "400009", 1235 "SampleAfterValue": "400009",
947 "BriefDescription": "Taken branch instructions retired. ", 1236 "BriefDescription": "Taken branch instructions retired.",
948 "CounterHTOff": "0,1,2,3,4,5,6,7" 1237 "CounterHTOff": "0,1,2,3,4,5,6,7"
949 }, 1238 },
950 { 1239 {
@@ -954,28 +1243,7 @@
954 "UMask": "0x40", 1243 "UMask": "0x40",
955 "EventName": "BR_INST_RETIRED.FAR_BRANCH", 1244 "EventName": "BR_INST_RETIRED.FAR_BRANCH",
956 "SampleAfterValue": "100007", 1245 "SampleAfterValue": "100007",
957 "BriefDescription": "Far branch instructions retired. ", 1246 "BriefDescription": "Far branch instructions retired.",
958 "CounterHTOff": "0,1,2,3,4,5,6,7"
959 },
960 {
961 "PEBS": "2",
962 "EventCode": "0xC4",
963 "Counter": "0,1,2,3",
964 "UMask": "0x4",
965 "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
966 "SampleAfterValue": "400009",
967 "BriefDescription": "All (macro) branch instructions retired.",
968 "CounterHTOff": "0,1,2,3"
969 },
970 {
971 "PEBS": "1",
972 "PublicDescription": "Mispredicted conditional branch instructions retired.",
973 "EventCode": "0xC5",
974 "Counter": "0,1,2,3",
975 "UMask": "0x1",
976 "EventName": "BR_MISP_RETIRED.CONDITIONAL",
977 "SampleAfterValue": "400009",
978 "BriefDescription": "Mispredicted conditional branch instructions retired. ",
979 "CounterHTOff": "0,1,2,3,4,5,6,7" 1247 "CounterHTOff": "0,1,2,3,4,5,6,7"
980 }, 1248 },
981 { 1249 {
@@ -990,13 +1258,12 @@
990 }, 1258 },
991 { 1259 {
992 "PEBS": "1", 1260 "PEBS": "1",
993 "PublicDescription": "Mispredicted taken branch instructions retired.",
994 "EventCode": "0xC5", 1261 "EventCode": "0xC5",
995 "Counter": "0,1,2,3", 1262 "Counter": "0,1,2,3",
996 "UMask": "0x20", 1263 "UMask": "0x1",
997 "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", 1264 "EventName": "BR_MISP_RETIRED.CONDITIONAL",
998 "SampleAfterValue": "400009", 1265 "SampleAfterValue": "400009",
999 "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. ", 1266 "BriefDescription": "Mispredicted conditional branch instructions retired.",
1000 "CounterHTOff": "0,1,2,3,4,5,6,7" 1267 "CounterHTOff": "0,1,2,3,4,5,6,7"
1001 }, 1268 },
1002 { 1269 {
@@ -1010,6 +1277,16 @@
1010 "CounterHTOff": "0,1,2,3" 1277 "CounterHTOff": "0,1,2,3"
1011 }, 1278 },
1012 { 1279 {
1280 "PEBS": "1",
1281 "EventCode": "0xC5",
1282 "Counter": "0,1,2,3",
1283 "UMask": "0x20",
1284 "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
1285 "SampleAfterValue": "400009",
1286 "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
1287 "CounterHTOff": "0,1,2,3,4,5,6,7"
1288 },
1289 {
1013 "PublicDescription": "Count cases of saving new LBR records by hardware.", 1290 "PublicDescription": "Count cases of saving new LBR records by hardware.",
1014 "EventCode": "0xCC", 1291 "EventCode": "0xCC",
1015 "Counter": "0,1,2,3", 1292 "Counter": "0,1,2,3",
@@ -1028,280 +1305,5 @@
1028 "SampleAfterValue": "100003", 1305 "SampleAfterValue": "100003",
1029 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 1306 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
1030 "CounterHTOff": "0,1,2,3,4,5,6,7" 1307 "CounterHTOff": "0,1,2,3,4,5,6,7"
1031 },
1032 {
1033 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1034 "EventCode": "0xB1",
1035 "Counter": "0,1,2,3",
1036 "UMask": "0x1",
1037 "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
1038 "SampleAfterValue": "2000003",
1039 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1040 "CounterMask": "1",
1041 "CounterHTOff": "0,1,2,3,4,5,6,7"
1042 },
1043 {
1044 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1045 "EventCode": "0xB1",
1046 "Counter": "0,1,2,3",
1047 "UMask": "0x1",
1048 "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
1049 "SampleAfterValue": "2000003",
1050 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1051 "CounterMask": "2",
1052 "CounterHTOff": "0,1,2,3,4,5,6,7"
1053 },
1054 {
1055 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1056 "EventCode": "0xB1",
1057 "Counter": "0,1,2,3",
1058 "UMask": "0x1",
1059 "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
1060 "SampleAfterValue": "2000003",
1061 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1062 "CounterMask": "3",
1063 "CounterHTOff": "0,1,2,3,4,5,6,7"
1064 },
1065 {
1066 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1067 "EventCode": "0xB1",
1068 "Counter": "0,1,2,3",
1069 "UMask": "0x1",
1070 "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
1071 "SampleAfterValue": "2000003",
1072 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1073 "CounterMask": "4",
1074 "CounterHTOff": "0,1,2,3,4,5,6,7"
1075 },
1076 {
1077 "EventCode": "0x5E",
1078 "Invert": "1",
1079 "Counter": "0,1,2,3",
1080 "UMask": "0x1",
1081 "EdgeDetect": "1",
1082 "EventName": "RS_EVENTS.EMPTY_END",
1083 "SampleAfterValue": "200003",
1084 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
1085 "CounterMask": "1",
1086 "CounterHTOff": "0,1,2,3,4,5,6,7"
1087 },
1088 {
1089 "EventCode": "0xC3",
1090 "Counter": "0,1,2,3",
1091 "UMask": "0x1",
1092 "EdgeDetect": "1",
1093 "EventName": "MACHINE_CLEARS.COUNT",
1094 "SampleAfterValue": "100003",
1095 "BriefDescription": "Number of machine clears (nukes) of any type.",
1096 "CounterMask": "1",
1097 "CounterHTOff": "0,1,2,3,4,5,6,7"
1098 },
1099 {
1100 "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
1101 "EventCode": "0xA8",
1102 "Counter": "0,1,2,3",
1103 "UMask": "0x1",
1104 "EventName": "LSD.CYCLES_4_UOPS",
1105 "SampleAfterValue": "2000003",
1106 "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
1107 "CounterMask": "4",
1108 "CounterHTOff": "0,1,2,3,4,5,6,7"
1109 },
1110 {
1111 "EventCode": "0xA3",
1112 "Counter": "2",
1113 "UMask": "0x8",
1114 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
1115 "SampleAfterValue": "2000003",
1116 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
1117 "CounterMask": "8",
1118 "CounterHTOff": "2"
1119 },
1120 {
1121 "EventCode": "0xA3",
1122 "Counter": "0,1,2,3",
1123 "UMask": "0x1",
1124 "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
1125 "SampleAfterValue": "2000003",
1126 "BriefDescription": "Cycles while L2 cache miss load* is outstanding.",
1127 "CounterMask": "1",
1128 "CounterHTOff": "0,1,2,3,4,5,6,7"
1129 },
1130 {
1131 "EventCode": "0xA3",
1132 "Counter": "0,1,2,3",
1133 "UMask": "0x2",
1134 "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
1135 "SampleAfterValue": "2000003",
1136 "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
1137 "CounterMask": "2",
1138 "CounterHTOff": "0,1,2,3"
1139 },
1140 {
1141 "EventCode": "0xA3",
1142 "Counter": "0,1,2,3",
1143 "UMask": "0x4",
1144 "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
1145 "SampleAfterValue": "2000003",
1146 "BriefDescription": "Total execution stalls.",
1147 "CounterMask": "4",
1148 "CounterHTOff": "0,1,2,3"
1149 },
1150 {
1151 "EventCode": "0xA3",
1152 "Counter": "2",
1153 "UMask": "0xc",
1154 "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
1155 "SampleAfterValue": "2000003",
1156 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
1157 "CounterMask": "12",
1158 "CounterHTOff": "2"
1159 },
1160 {
1161 "EventCode": "0xA3",
1162 "Counter": "0,1,2,3",
1163 "UMask": "0x5",
1164 "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
1165 "SampleAfterValue": "2000003",
1166 "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",
1167 "CounterMask": "5",
1168 "CounterHTOff": "0,1,2,3"
1169 },
1170 {
1171 "EventCode": "0xA3",
1172 "Counter": "0,1,2,3",
1173 "UMask": "0x6",
1174 "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
1175 "SampleAfterValue": "2000003",
1176 "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
1177 "CounterMask": "6",
1178 "CounterHTOff": "0,1,2,3"
1179 },
1180 {
1181 "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
1182 "EventCode": "0x00",
1183 "Counter": "Fixed counter 2",
1184 "UMask": "0x2",
1185 "AnyThread": "1",
1186 "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
1187 "SampleAfterValue": "2000003",
1188 "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
1189 "CounterHTOff": "Fixed counter 2"
1190 },
1191 {
1192 "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
1193 "EventCode": "0x3C",
1194 "Counter": "0,1,2,3",
1195 "UMask": "0x0",
1196 "AnyThread": "1",
1197 "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
1198 "SampleAfterValue": "2000003",
1199 "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
1200 "CounterHTOff": "0,1,2,3,4,5,6,7"
1201 },
1202 {
1203 "EventCode": "0x3C",
1204 "Counter": "0,1,2,3",
1205 "UMask": "0x1",
1206 "AnyThread": "1",
1207 "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
1208 "SampleAfterValue": "2000003",
1209 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
1210 "CounterHTOff": "0,1,2,3,4,5,6,7"
1211 },
1212 {
1213 "EventCode": "0x0D",
1214 "Counter": "0,1,2,3",
1215 "UMask": "0x3",
1216 "AnyThread": "1",
1217 "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
1218 "SampleAfterValue": "2000003",
1219 "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
1220 "CounterMask": "1",
1221 "CounterHTOff": "0,1,2,3,4,5,6,7"
1222 },
1223 {
1224 "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1225 "EventCode": "0xB1",
1226 "Counter": "0,1,2,3",
1227 "UMask": "0x2",
1228 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
1229 "SampleAfterValue": "2000003",
1230 "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
1231 "CounterMask": "1",
1232 "CounterHTOff": "0,1,2,3,4,5,6,7"
1233 },
1234 {
1235 "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1236 "EventCode": "0xB1",
1237 "Counter": "0,1,2,3",
1238 "UMask": "0x2",
1239 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
1240 "SampleAfterValue": "2000003",
1241 "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
1242 "CounterMask": "2",
1243 "CounterHTOff": "0,1,2,3,4,5,6,7"
1244 },
1245 {
1246 "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1247 "EventCode": "0xB1",
1248 "Counter": "0,1,2,3",
1249 "UMask": "0x2",
1250 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
1251 "SampleAfterValue": "2000003",
1252 "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
1253 "CounterMask": "3",
1254 "CounterHTOff": "0,1,2,3,4,5,6,7"
1255 },
1256 {
1257 "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1258 "EventCode": "0xB1",
1259 "Counter": "0,1,2,3",
1260 "UMask": "0x2",
1261 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
1262 "SampleAfterValue": "2000003",
1263 "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
1264 "CounterMask": "4",
1265 "CounterHTOff": "0,1,2,3,4,5,6,7"
1266 },
1267 {
1268 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1269 "EventCode": "0xB1",
1270 "Invert": "1",
1271 "Counter": "0,1,2,3",
1272 "UMask": "0x2",
1273 "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
1274 "SampleAfterValue": "2000003",
1275 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
1276 "CounterHTOff": "0,1,2,3,4,5,6,7"
1277 },
1278 {
1279 "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
1280 "EventCode": "0x3C",
1281 "Counter": "0,1,2,3",
1282 "UMask": "0x1",
1283 "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
1284 "SampleAfterValue": "2000003",
1285 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
1286 "CounterHTOff": "0,1,2,3,4,5,6,7"
1287 },
1288 {
1289 "EventCode": "0x3C",
1290 "Counter": "0,1,2,3",
1291 "UMask": "0x1",
1292 "AnyThread": "1",
1293 "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
1294 "SampleAfterValue": "2000003",
1295 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
1296 "CounterHTOff": "0,1,2,3,4,5,6,7"
1297 },
1298 {
1299 "EventCode": "0x3C",
1300 "Counter": "0,1,2,3",
1301 "UMask": "0x2",
1302 "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
1303 "SampleAfterValue": "2000003",
1304 "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
1305 "CounterHTOff": "0,1,2,3,4,5,6,7"
1306 } 1308 }
1307] \ No newline at end of file 1309] \ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
index c8de548b78fa..4645e9d3f460 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
@@ -1,5 +1,15 @@
1[ 1[
2 { 2 {
3 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.",
4 "EventCode": "0x08",
5 "Counter": "0,1,2,3",
6 "UMask": "0x81",
7 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
8 "SampleAfterValue": "100003",
9 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
11 },
12 {
3 "EventCode": "0x08", 13 "EventCode": "0x08",
4 "Counter": "0,1,2,3", 14 "Counter": "0,1,2,3",
5 "UMask": "0x82", 15 "UMask": "0x82",
@@ -9,6 +19,16 @@
9 "CounterHTOff": "0,1,2,3,4,5,6,7" 19 "CounterHTOff": "0,1,2,3,4,5,6,7"
10 }, 20 },
11 { 21 {
22 "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.",
23 "EventCode": "0x08",
24 "Counter": "0,1,2,3",
25 "UMask": "0x82",
26 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
27 "SampleAfterValue": "100003",
28 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
29 "CounterHTOff": "0,1,2,3,4,5,6,7"
30 },
31 {
12 "EventCode": "0x08", 32 "EventCode": "0x08",
13 "Counter": "0,1,2,3", 33 "Counter": "0,1,2,3",
14 "UMask": "0x84", 34 "UMask": "0x84",
@@ -18,6 +38,16 @@
18 "CounterHTOff": "0,1,2,3,4,5,6,7" 38 "CounterHTOff": "0,1,2,3,4,5,6,7"
19 }, 39 },
20 { 40 {
41 "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
42 "EventCode": "0x08",
43 "Counter": "0,1,2,3",
44 "UMask": "0x84",
45 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
46 "SampleAfterValue": "2000003",
47 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
48 "CounterHTOff": "0,1,2,3,4,5,6,7"
49 },
50 {
21 "EventCode": "0x08", 51 "EventCode": "0x08",
22 "Counter": "0,1,2,3", 52 "Counter": "0,1,2,3",
23 "UMask": "0x88", 53 "UMask": "0x88",
@@ -164,35 +194,5 @@
164 "SampleAfterValue": "100007", 194 "SampleAfterValue": "100007",
165 "BriefDescription": "STLB flush attempts", 195 "BriefDescription": "STLB flush attempts",
166 "CounterHTOff": "0,1,2,3,4,5,6,7" 196 "CounterHTOff": "0,1,2,3,4,5,6,7"
167 },
168 {
169 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.",
170 "EventCode": "0x08",
171 "Counter": "0,1,2,3",
172 "UMask": "0x81",
173 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
174 "SampleAfterValue": "100003",
175 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
176 "CounterHTOff": "0,1,2,3,4,5,6,7"
177 },
178 {
179 "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.",
180 "EventCode": "0x08",
181 "Counter": "0,1,2,3",
182 "UMask": "0x82",
183 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
184 "SampleAfterValue": "100003",
185 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
186 "CounterHTOff": "0,1,2,3,4,5,6,7"
187 },
188 {
189 "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
190 "EventCode": "0x08",
191 "Counter": "0,1,2,3",
192 "UMask": "0x84",
193 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
194 "SampleAfterValue": "2000003",
195 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
196 "CounterHTOff": "0,1,2,3,4,5,6,7"
197 } 197 }
198] \ No newline at end of file 198] \ No newline at end of file
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-25 22:45:47 -0400