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path: root/tools/perf/scripts/python/exported-sql-viewer.py

/*
 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
 *
 * Based on skelton.c by Donald Becker.
 *
 * This driver is a replacement of older and less maintained version.
 * This is a header of the older version:
 *	-----<snip>-----
 *	Copyright 2001 MontaVista Software Inc.
 *	Author: MontaVista Software, Inc.
 *		ahennessy@mvista.com
 *	Copyright (C) 2000-2001 Toshiba Corporation
 *	static const char *version =
 *		"tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
 *	-----<snip>-----
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * (C) Copyright TOSHIBA CORPORATION 2004-2005
 * All Rights Reserved.
 */

#ifdef TC35815_NAPI
#define DRV_VERSION	"1.37-NAPI"
#else
#define DRV_VERSION	"1.37"
#endif
static const char *version = "tc35815.c:v" DRV_VERSION "\n";
#define MODNAME			"tc35815"

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/in.h>
#include <linux/if_vlan.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/phy.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/byteorder.h>

/* First, a few definitions that the brave might change. */

#define GATHER_TXINT	/* On-Demand Tx Interrupt */
#define WORKAROUND_LOSTCAR
#define WORKAROUND_100HALF_PROMISC
/* #define TC35815_USE_PACKEDBUFFER */

enum tc35815_chiptype {
	TC35815CF = 0,
	TC35815_NWU,
	TC35815_TX4939,
};

/* indexed by tc35815_chiptype, above */
static const struct {
	const char *name;
} chip_info[] __devinitdata = {
	{ "TOSHIBA TC35815CF 10/100BaseTX" },
	{ "TOSHIBA TC35815 with Wake on LAN" },
	{ "TOSHIBA TC35815/TX4939" },
};

static const struct pci_device_id tc35815_pci_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
	{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
	{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
	{0,}
};
MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);

/* see MODULE_PARM_DESC */
static struct tc35815_options {
	int speed;
	int duplex;
} options;

/*
 * Registers
 */
struct tc35815_regs {
	__u32 DMA_Ctl;		/* 0x00 */
	__u32 TxFrmPtr;
	__u32 TxThrsh;
	__u32 TxPollCtr;
	__u32 BLFrmPtr;
	__u32 RxFragSize;
	__u32 Int_En;
	__u32 FDA_Bas;
	__u32 FDA_Lim;		/* 0x20 */
	__u32 Int_Src;
	__u32 unused0[2];
	__u32 PauseCnt;
	__u32 RemPauCnt;
	__u32 TxCtlFrmStat;
	__u32 unused1;
	__u32 MAC_Ctl;		/* 0x40 */
	__u32 CAM_Ctl;
	__u32 Tx_Ctl;
	__u32 Tx_Stat;
	__u32 Rx_Ctl;
	__u32 Rx_Stat;
	__u32 MD_Data;
	__u32 MD_CA;
	__u32 CAM_Adr;		/* 0x60 */
	__u32 CAM_Data;
	__u32 CAM_Ena;
	__u32 PROM_Ctl;
	__u32 PROM_Data;
	__u32 Algn_Cnt;
	__u32 CRC_Cnt;
	__u32 Miss_Cnt;
};

/*
 * Bit assignments
 */
/* DMA_Ctl bit asign ------------------------------------------------------- */
#define DMA_RxAlign	       0x00c00000 /* 1:Reception Alignment	     */
#define DMA_RxAlign_1	       0x00400000
#define DMA_RxAlign_2	       0x00800000
#define DMA_RxAlign_3	       0x00c00000
#define DMA_M66EnStat	       0x00080000 /* 1:66MHz Enable State	     */
#define DMA_IntMask	       0x00040000 /* 1:Interupt mask		     */
#define DMA_SWIntReq	       0x00020000 /* 1:Software Interrupt request    */
#define DMA_TxWakeUp	       0x00010000 /* 1:Transmit Wake Up		     */
#define DMA_RxBigE	       0x00008000 /* 1:Receive Big Endian	     */
#define DMA_TxBigE	       0x00004000 /* 1:Transmit Big Endian	     */
#define DMA_TestMode	       0x00002000 /* 1:Test Mode		     */
#define DMA_PowrMgmnt	       0x00001000 /* 1:Power Management		     */
#define DMA_DmBurst_Mask       0x000001fc /* DMA Burst size		     */

/* RxFragSize bit asign ---------------------------------------------------- */
#define RxFrag_EnPack	       0x00008000 /* 1:Enable Packing		     */
#define RxFrag_MinFragMask     0x00000ffc /* Minimum Fragment		     */

/* MAC_Ctl bit asign ------------------------------------------------------- */
#define MAC_Link10	       0x00008000 /* 1:Link Status 10Mbits	     */
#define MAC_EnMissRoll	       0x00002000 /* 1:Enable Missed Roll	     */
#define MAC_MissRoll	       0x00000400 /* 1:Missed Roll		     */
#define MAC_Loop10	       0x00000080 /* 1:Loop 10 Mbps		     */
#define MAC_Conn_Auto	       0x00000000 /*00:Connection mode (Automatic)   */
#define MAC_Conn_10M	       0x00000020 /*01:		       (10Mbps endec)*/
#define MAC_Conn_Mll	       0x00000040 /*10:		       (Mll clock)   */
#define MAC_MacLoop	       0x00000010 /* 1:MAC Loopback		     */
#define MAC_FullDup	       0x00000008 /* 1:Full Duplex 0:Half Duplex     */
#define MAC_Reset	       0x00000004 /* 1:Software Reset		     */
#define MAC_HaltImm	       0x00000002 /* 1:Halt Immediate		     */
#define MAC_HaltReq	       0x00000001 /* 1:Halt request		     */

/* PROM_Ctl bit asign ------------------------------------------------------ */
#define PROM_Busy	       0x00008000 /* 1:Busy (Start Operation)	     */
#define PROM_Read	       0x00004000 /*10:Read operation		     */
#define PROM_Write	       0x00002000 /*01:Write operation		     */
#define PROM_Erase	       0x00006000 /*11:Erase operation		     */
					  /*00:Enable or Disable Writting,   */
					  /*	  as specified in PROM_Addr. */
#define PROM_Addr_Ena	       0x00000030 /*11xxxx:PROM Write enable	     */
					  /*00xxxx:	      disable	     */

/* CAM_Ctl bit asign ------------------------------------------------------- */
#define CAM_CompEn	       0x00000010 /* 1:CAM Compare Enable	     */
#define CAM_NegCAM	       0x00000008 /* 1:Reject packets CAM recognizes,*/
					  /*			accept other */
#define CAM_BroadAcc	       0x00000004 /* 1:Broadcast assept		     */
#define CAM_GroupAcc	       0x00000002 /* 1:Multicast assept		     */
#define CAM_StationAcc	       0x00000001 /* 1:unicast accept		     */

/* CAM_Ena bit asign ------------------------------------------------------- */
#define CAM_ENTRY_MAX		       21   /* CAM Data entry max count	     */
#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits)  */
#define CAM_Ena_Bit(index)	(1 << (index))
#define CAM_ENTRY_DESTINATION	0
#define CAM_ENTRY_SOURCE	1
#define CAM_ENTRY_MACCTL	20

/* Tx_Ctl bit asign -------------------------------------------------------- */
#define Tx_En		       0x00000001 /* 1:Transmit enable		     */
#define Tx_TxHalt	       0x00000002 /* 1:Transmit Halt Request	     */
#define Tx_NoPad	       0x00000004 /* 1:Suppress Padding		     */
#define Tx_NoCRC	       0x00000008 /* 1:Suppress Padding		     */
#define Tx_FBack	       0x00000010 /* 1:Fast Back-off		     */
#define Tx_EnUnder	       0x00000100 /* 1:Enable Underrun		     */
#define Tx_EnExDefer	       0x00000200 /* 1:Enable Excessive Deferral     */
#define Tx_EnLCarr	       0x00000400 /* 1:Enable Lost Carrier	     */
#define Tx_EnExColl	       0x00000800 /* 1:Enable Excessive Collision    */
#define Tx_EnLateColl	       0x00001000 /* 1:Enable Late Collision	     */
#define Tx_EnTxPar	       0x00002000 /* 1:Enable Transmit Parity	     */
#define Tx_EnComp	       0x00004000 /* 1:Enable Completion	     */

/* Tx_Stat bit asign ------------------------------------------------------- */
#define Tx_TxColl_MASK	       0x0000000F /* Tx Collision Count		     */
#define Tx_ExColl	       0x00000010 /* Excessive Collision	     */
#define Tx_TXDefer	       0x00000020 /* Transmit Defered		     */
#define Tx_Paused	       0x00000040 /* Transmit Paused		     */
#define Tx_IntTx	       0x00000080 /* Interrupt on Tx		     */
#define Tx_Under	       0x00000100 /* Underrun			     */
#define Tx_Defer	       0x00000200 /* Deferral			     */
#define Tx_NCarr	       0x00000400 /* No Carrier			     */
#define Tx_10Stat	       0x00000800 /* 10Mbps Status		     */
#define Tx_LateColl	       0x00001000 /* Late Collision		     */
#define Tx_TxPar	       0x00002000 /* Tx Parity Error		     */
#define Tx_Comp		       0x00004000 /* Completion			     */
#define Tx_Halted	       0x00008000 /* Tx Halted			     */
#define Tx_SQErr	       0x00010000 /* Signal Quality Error(SQE)	     */

/* Rx_Ctl bit asign -------------------------------------------------------- */
#define Rx_EnGood	       0x00004000 /* 1:Enable Good		     */
#define Rx_EnRxPar	       0x00002000 /* 1:Enable Receive Parity	     */
#define Rx_EnLongErr	       0x00000800 /* 1:Enable Long Error	     */
#define Rx_EnOver	       0x00000400 /* 1:Enable OverFlow		     */
#define Rx_EnCRCErr	       0x00000200 /* 1:Enable CRC Error		     */
#define Rx_EnAlign	       0x00000100 /* 1:Enable Alignment		     */
#define Rx_IgnoreCRC	       0x00000040 /* 1:Ignore CRC Value		     */
#define Rx_StripCRC	       0x00000010 /* 1:Strip CRC Value		     */
#define Rx_ShortEn	       0x00000008 /* 1:Short Enable		     */
#define Rx_LongEn	       0x00000004 /* 1:Long Enable		     */
#define Rx_RxHalt	       0x00000002 /* 1:Receive Halt Request	     */
#define Rx_RxEn		       0x00000001 /* 1:Receive Intrrupt Enable	     */

/* Rx_Stat bit asign ------------------------------------------------------- */
#define Rx_Halted	       0x00008000 /* Rx Halted			     */
#define Rx_Good		       0x00004000 /* Rx Good			     */
#define Rx_RxPar	       0x00002000 /* Rx Parity Error		     */
#define Rx_TypePkt	       0x00001000 /* Rx Type Packet		     */
#define Rx_LongErr	       0x00000800 /* Rx Long Error		     */
#define Rx_Over		       0x00000400 /* Rx Overflow		     */
#define Rx_CRCErr	       0x00000200 /* Rx CRC Error		     */
#define Rx_Align	       0x00000100 /* Rx Alignment Error		     */
#define Rx_10Stat	       0x00000080 /* Rx 10Mbps Status		     */
#define Rx_IntRx	       0x00000040 /* Rx Interrupt		     */
#define Rx_CtlRecd	       0x00000020 /* Rx Control Receive		     */
#define Rx_InLenErr	       0x00000010 /* Rx In Range Frame Length Error  */

#define Rx_Stat_Mask	       0x0000FFF0 /* Rx All Status Mask		     */

/* Int_En bit asign -------------------------------------------------------- */
#define Int_NRAbtEn	       0x00000800 /* 1:Non-recoverable Abort Enable  */
#define Int_TxCtlCmpEn	       0x00000400 /* 1:Transmit Ctl Complete Enable  */
#define Int_DmParErrEn	       0x00000200 /* 1:DMA Parity Error Enable	     */
#define Int_DParDEn	       0x00000100 /* 1:Data Parity Error Enable	     */
#define Int_EarNotEn	       0x00000080 /* 1:Early Notify Enable	     */
#define Int_DParErrEn	       0x00000040 /* 1:Detected Parity Error Enable  */
#define Int_SSysErrEn	       0x00000020 /* 1:Signalled System Error Enable */
#define Int_RMasAbtEn	       0x00000010 /* 1:Received Master Abort Enable  */
#define Int_RTargAbtEn	       0x00000008 /* 1:Received Target Abort Enable  */
#define Int_STargAbtEn	       0x00000004 /* 1:Signalled Target Abort Enable */
#define Int_BLExEn	       0x00000002 /* 1:Buffer List Exhausted Enable  */
#define Int_FDAExEn	       0x00000001 /* 1:Free Descriptor Area	     */
					  /*		   Exhausted Enable  */

/* Int_Src bit asign ------------------------------------------------------- */
#define Int_NRabt	       0x00004000 /* 1:Non Recoverable error	     */
#define Int_DmParErrStat       0x00002000 /* 1:DMA Parity Error & Clear	     */
#define Int_BLEx	       0x00001000 /* 1:Buffer List Empty & Clear     */
#define Int_FDAEx	       0x00000800 /* 1:FDA Empty & Clear	     */
#define Int_IntNRAbt	       0x00000400 /* 1:Non Recoverable Abort	     */
#define Int_IntCmp	       0x00000200 /* 1:MAC control packet complete   */
#define Int_IntExBD	       0x00000100 /* 1:Interrupt Extra BD & Clear    */
#define Int_DmParErr	       0x00000080 /* 1:DMA Parity Error & Clear	     */
#define Int_IntEarNot	       0x00000040 /* 1:Receive Data write & Clear    */
#define Int_SWInt	       0x00000020 /* 1:Software request & Clear	     */
#define Int_IntBLEx	       0x00000010 /* 1:Buffer List Empty & Clear     */
#define Int_IntFDAEx	       0x00000008 /* 1:FDA Empty & Clear	     */
#define Int_IntPCI	       0x00000004 /* 1:PCI controller & Clear	     */
#define Int_IntMacRx	       0x00000002 /* 1:Rx controller & Clear	     */
#define Int_IntMacTx	       0x00000001 /* 1:Tx controller & Clear	     */

/* MD_CA bit asign --------------------------------------------------------- */
#define MD_CA_PreSup	       0x00001000 /* 1:Preamble Supress		     */
#define MD_CA_Busy	       0x00000800 /* 1:Busy (Start Operation)	     */
#define MD_CA_Wr	       0x00000400 /* 1:Write 0:Read		     */


/*
 * Descriptors
 */

/* Frame descripter */
struct FDesc {
	volatile __u32 FDNext;
	volatile __u32 FDSystem;
	volatile __u32 FDStat;
	volatile __u32 FDCtl;
};

/* Buffer descripter */
struct BDesc {
	volatile __u32 BuffData;
	volatile __u32 BDCtl;
};

#define FD_ALIGN	16

/* Frame Descripter bit asign ---------------------------------------------- */
#define FD_FDLength_MASK       0x0000FFFF /* Length MASK		     */
#define FD_BDCnt_MASK	       0x001F0000 /* BD count MASK in FD	     */
#define FD_FrmOpt_MASK	       0x7C000000 /* Frame option MASK		     */
#define FD_FrmOpt_BigEndian    0x40000000 /* Tx/Rx */
#define FD_FrmOpt_IntTx	       0x20000000 /* Tx only */
#define FD_FrmOpt_NoCRC	       0x10000000 /* Tx only */
#define FD_FrmOpt_NoPadding    0x08000000 /* Tx only */
#define FD_FrmOpt_Packing      0x04000000 /* Rx only */
#define FD_CownsFD	       0x80000000 /* FD Controller owner bit	     */
#define FD_Next_EOL	       0x00000001 /* FD EOL indicator		     */
#define FD_BDCnt_SHIFT	       16

/* Buffer Descripter bit asign --------------------------------------------- */
#define BD_BuffLength_MASK     0x0000FFFF /* Recieve Data Size		     */
#define BD_RxBDID_MASK	       0x00FF0000 /* BD ID Number MASK		     */
#define BD_RxBDSeqN_MASK       0x7F000000 /* Rx BD Sequence Number	     */
#define BD_CownsBD	       0x80000000 /* BD Controller owner bit	     */
#define BD_RxBDID_SHIFT	       16
#define BD_RxBDSeqN_SHIFT      24


/* Some useful constants. */
#undef NO_CHECK_CARRIER	/* Does not check No-Carrier with TP */

#ifdef NO_CHECK_CARRIER
#define TX_CTL_CMD	(Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
	Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
	Tx_En)	/* maybe  0x7b01 */
#else
#define TX_CTL_CMD	(Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
	Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
	Tx_En)	/* maybe  0x7b01 */
#endif
#define RX_CTL_CMD	(Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
	| Rx_EnCRCErr | Rx_EnAlign | Rx_StripCRC | Rx_RxEn) /* maybe 0x6f11 */
#define INT_EN_CMD  (Int_NRAbtEn | \
	Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
	Int_SSysErrEn  | Int_RMasAbtEn | Int_RTargAbtEn | \
	Int_STargAbtEn | \
	Int_BLExEn  | Int_FDAExEn) /* maybe 0xb7f*/
#define DMA_CTL_CMD	DMA_BURST_SIZE
#define HAVE_DMA_RXALIGN(lp)	likely((lp)->chiptype != TC35815CF)

/* Tuning parameters */
#define DMA_BURST_SIZE	32
#define TX_THRESHOLD	1024
/* used threshold with packet max byte for low pci transfer ability.*/
#define TX_THRESHOLD_MAX 1536
/* setting threshold max value when overrun error occured this count. */
#define TX_THRESHOLD_KEEP_LIMIT 10

/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
#ifdef TC35815_USE_PACKEDBUFFER
#define FD_PAGE_NUM 2
#define RX_BUF_NUM	8	/* >= 2 */
#define RX_FD_NUM	250	/* >= 32 */
#define TX_FD_NUM	128
#define RX_BUF_SIZE	PAGE_SIZE
#else /* TC35815_USE_PACKEDBUFFER */
#define FD_PAGE_NUM 4
#define RX_BUF_NUM	128	/* < 256 */
#define RX_FD_NUM	256	/* >= 32 */
#define TX_FD_NUM	128
#if RX_CTL_CMD & Rx_LongEn
#define RX_BUF_SIZE	PAGE_SIZE
#elif RX_CTL_CMD & Rx_StripCRC
#define RX_BUF_SIZE	\
	L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
#else
#define RX_BUF_SIZE	\
	L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
#endif
#endif /* TC35815_USE_PACKEDBUFFER */
#define RX_FD_RESERVE	(2 / 2)	/* max 2 BD per RxFD */
#define NAPI_WEIGHT	16

struct TxFD {
	struct FDesc fd;
	struct BDesc bd;
	struct BDesc unused;
};

struct RxFD {
	struct FDesc fd;
	struct BDesc bd[0];	/* variable length */
};

struct FrFD {
	struct FDesc fd;
	struct BDesc bd[RX_BUF_NUM];
};


#define tc_readl(addr)	ioread32(addr)
#define tc_writel(d, addr)	iowrite32(d, addr)

#define TC35815_TX_TIMEOUT  msecs_to_jiffies(400)

/* Information that need to be kept for each controller. */
struct tc35815_local {
	struct pci_dev *pci_dev;

	struct net_device *dev;
	struct napi_struct napi;

	/* statistics */
	struct {
		int max_tx_qlen;
		int tx_ints;
		int rx_ints;
		int tx_underrun;
	} lstats;

	/* Tx control lock.  This protects the transmit buffer ring
	 * state along with the "tx full" state of the driver.  This
	 * means all netif_queue flow control actions are protected
	 * by this lock as well.
	 */
	spinlock_t lock;

	struct mii_bus *mii_bus;
	struct phy_device *phy_dev;
	int duplex;
	int speed;
	int link;
	struct work_struct restart_work;

	/*
	 * Transmitting: Batch Mode.
	 *	1 BD in 1 TxFD.
	 * Receiving: Packing Mode. (TC35815_USE_PACKEDBUFFER)
	 *	1 circular FD for Free Buffer List.
	 *	RX_BUF_NUM BD in Free Buffer FD.
	 *	One Free Buffer BD has PAGE_SIZE data buffer.
	 * Or Non-Packing Mode.
	 *	1 circular FD for Free Buffer List.
	 *	RX_BUF_NUM BD in Free Buffer FD.
	 *	One Free Buffer BD has ETH_FRAME_LEN data buffer.
	 */
	void *fd_buf;	/* for TxFD, RxFD, FrFD */
	dma_addr_t fd_buf_dma;
	struct TxFD *tfd_base;
	unsigned int tfd_start;
	unsigned int tfd_end;
	struct RxFD *rfd_base;
	struct RxFD *rfd_limit;
	struct RxFD *rfd_cur;
	struct FrFD *fbl_ptr;
#ifdef TC35815_USE_PACKEDBUFFER
	unsigned char fbl_curid;
	void *data_buf[RX_BUF_NUM];		/* packing */
	dma_addr_t data_buf_dma[RX_BUF_NUM];
	struct {
		struct sk_buff *skb;
		dma_addr_t skb_dma;
	} tx_skbs[TX_FD_NUM];
#else
	unsigned int fbl_count;
	struct {
		struct sk_buff *skb;
		dma_addr_t skb_dma;
	} tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
#endif
	u32 msg_enable;
	enum tc35815_chiptype chiptype;
};

static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
{
	return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
}
#ifdef DEBUG
static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
{
	return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
}
#endif
#ifdef TC35815_USE_PACKEDBUFFER
static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
{
	int i;
	for (i = 0; i < RX_BUF_NUM; i++) {
		if (bus >= lp->data_buf_dma[i] &&
		    bus < lp->data_buf_dma[i] + PAGE_SIZE)
			return (void *)((u8 *)lp->data_buf[i] +
					(bus - lp->data_buf_dma[i]));
	}
	return NULL;
}

#define TC35815_DMA_SYNC_ONDEMAND
static void *alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
{
#ifdef TC35815_DMA_SYNC_ONDEMAND
	void *buf;
	/* pci_map + pci_dma_sync will be more effective than
	 * pci_alloc_consistent on some archs. */
	buf = (void *)__get_free_page(GFP_ATOMIC);
	if (!buf)
		return NULL;
	*dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
				     PCI_DMA_FROMDEVICE);
	if (pci_dma_mapping_error(hwdev, *dma_handle)) {
		free_page((unsigned long)buf);
		return NULL;
	}
	return buf;
#else
	return pci_alloc_consistent(hwdev, PAGE_SIZE, dma_handle);
#endif
}

static void free_rxbuf_page(struct pci_dev *hwdev, void *buf, dma_addr_t dma_handle)
{
#ifdef TC35815_DMA_SYNC_ONDEMAND
	pci_unmap_single(hwdev, dma_handle, PAGE_SIZE, PCI_DMA_FROMDEVICE);
	free_page((unsigned long)buf);
#else
	pci_free_consistent(hwdev, PAGE_SIZE, buf, dma_handle);
#endif
}
#else /* TC35815_USE_PACKEDBUFFER */
static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
				       struct pci_dev *hwdev,
				       dma_addr_t *dma_handle)
{
	struct sk_buff *skb;
	skb = dev_alloc_skb(RX_BUF_SIZE);
	if (!skb)
		return NULL;
	*dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
				     PCI_DMA_FROMDEVICE);
	if (pci_dma_mapping_error(hwdev, *dma_handle)) {
		dev_kfree_skb_any(skb);
		return NULL;
	}
	skb_reserve(skb, 2);	/* make IP header 4byte aligned */
	return skb;
}

static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
{
	pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
			 PCI_DMA_FROMDEVICE);
	dev_kfree_skb_any(skb);
}
#endif /* TC35815_USE_PACKEDBUFFER */

/* Index to functions, as function prototypes. */

static int	tc35815_open(struct net_device *dev);
static int	tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
static irqreturn_t	tc35815_interrupt(int irq, void *dev_id);
#ifdef TC35815_NAPI
static int	tc35815_rx(struct net_device *dev, int limit);
static int	tc35815_poll(struct napi_struct *napi, int budget);
#else
static void	tc35815_rx(struct net_device *dev);
#endif
static void	tc35815_txdone(struct net_device *dev);
static int	tc35815_close(struct net_device *dev);
static struct	net_device_stats *tc35815_get_stats(struct net_device *dev);
static void	tc35815_set_multicast_list(struct net_device *dev);
static void	tc35815_tx_timeout(struct net_device *dev);
static int	tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
#ifdef CONFIG_NET_POLL_CONTROLLER
static void	tc35815_poll_controller(struct net_device *dev);
#endif
static const struct ethtool_ops tc35815_ethtool_ops;

/* Example routines you must write ;->. */
static void	tc35815_chip_reset(struct net_device *dev);
static void	tc35815_chip_init(struct net_device *dev);

#ifdef DEBUG
static void	panic_queues(struct net_device *dev);
#endif

static void tc35815_restart_work(struct work_struct *work);

static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
{
	struct net_device *dev = bus->priv;
	struct tc35815_regs __iomem *tr =
		(struct tc35815_regs __iomem *)dev->base_addr;
	unsigned long timeout = jiffies + 10;

	tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
	while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
		if (time_after(jiffies, timeout))
			return -EIO;
		cpu_relax();
	}
	return tc_readl(&tr->MD_Data) & 0xffff;
}

static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
{
	struct net_device *dev = bus->priv;
	struct tc35815_regs __iomem *tr =
		(struct tc35815_regs __iomem *)dev->base_addr;
	unsigned long timeout = jiffies + 10;

	tc_writel(val, &tr->MD_Data);
	tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
		  &tr->MD_CA);
	while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
		if (time_after(jiffies, timeout))
			return -EIO;
		cpu_relax();
	}
	return 0;
}

static void tc_handle_link_change(struct net_device *dev)
{
	struct tc35815_local *lp = netdev_priv(dev);
	struct phy_device *phydev = lp->phy_dev;
	unsigned long flags;
	int status_change = 0;

	spin_lock_irqsave(&lp->lock, flags);
	if (phydev->link &&