litmus-rt-ext-res.git - LITMUS^RT with extended reservations for Forbidden Zones paper @ RTAS'20

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/* spr-regs.h: special-purpose registers on the FRV * * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #ifndef _ASM_SPR_REGS_H #define _ASM_SPR_REGS_H /* * PSR - Processor Status Register */ #define PSR_ET 0x00000001 /* enable interrupts/exceptions flag */ #define PSR_PS 0x00000002 /* previous supervisor mode flag */ #define PSR_S 0x00000004 /* supervisor mode flag */ #define PSR_PIL 0x00000078 /* processor external interrupt level */ #define PSR_PIL_0 0x00000000 /* - no interrupt in progress */ #define PSR_PIL_13 0x00000068 /* - debugging only */ #define PSR_PIL_14 0x00000070 /* - debugging in progress */ #define PSR_PIL_15 0x00000078 /* - NMI in progress */ #define PSR_EM 0x00000080 /* enable media operation */ #define PSR_EF 0x00000100 /* enable FPU operation */ #define PSR_BE 0x00001000 /* endianness mode */ #define PSR_BE_LE 0x00000000 /* - little endian mode */ #define PSR_BE_BE 0x00001000 /* - big endian mode */ #define PSR_CM 0x00002000 /* conditional mode */ #define PSR_NEM 0x00004000 /* non-excepting mode */ #define PSR_ICE 0x00010000 /* in-circuit emulation mode */ #define PSR_VERSION_SHIFT 24 /* CPU silicon ID */ #define PSR_IMPLE_SHIFT 28 /* CPU core ID */ #define PSR_VERSION(psr) (((psr) >> PSR_VERSION_SHIFT) & 0xf) #define PSR_IMPLE(psr) (((psr) >> PSR_IMPLE_SHIFT) & 0xf) #define PSR_IMPLE_FR401 0x2 #define PSR_VERSION_FR401_MB93401 0x0 #define PSR_VERSION_FR401_MB93401A 0x1 #define PSR_VERSION_FR401_MB93403 0x2 #define PSR_IMPLE_FR405 0x4 #define PSR_VERSION_FR405_MB93405 0x0 #define PSR_IMPLE_FR451 0x5 #define PSR_VERSION_FR451_MB93451 0x0 #define PSR_IMPLE_FR501 0x1 #define PSR_VERSION_FR501_MB93501 0x1 #define PSR_VERSION_FR501_MB93501A 0x2 #define PSR_IMPLE_FR551 0x3 #define PSR_VERSION_FR551_MB93555 0x1 #define __get_PSR() ({ unsigned long x; asm volatile("movsg psr,%0" : "=r"(x)); x; }) #define __set_PSR(V) do { asm volatile("movgs %0,psr" : : "r"(V)); } while(0) /* * TBR - Trap Base Register */ #define TBR_TT 0x00000ff0 #define TBR_TT_INSTR_MMU_MISS (0x01 << 4) #define TBR_TT_INSTR_ACC_ERROR (0x02 << 4) #define TBR_TT_INSTR_ACC_EXCEP (0x03 << 4) #define TBR_TT_PRIV_INSTR (0x06 << 4) #define TBR_TT_ILLEGAL_INSTR (0x07 << 4) #define TBR_TT_FP_EXCEPTION (0x0d << 4) #define TBR_TT_MP_EXCEPTION (0x0e << 4) #define TBR_TT_DATA_ACC_ERROR (0x11 << 4) #define TBR_TT_DATA_MMU_MISS (0x12 << 4) #define TBR_TT_DATA_ACC_EXCEP (0x13 << 4) #define TBR_TT_DATA_STR_ERROR (0x14 << 4) #define TBR_TT_DIVISION_EXCEP (0x17 << 4) #define TBR_TT_COMMIT_EXCEP (0x19 << 4) #define TBR_TT_INSTR_TLB_MISS (0x1a << 4) #define TBR_TT_DATA_TLB_MISS (0x1b << 4) #define TBR_TT_DATA_DAT_EXCEP (0x1d << 4) #define TBR_TT_DECREMENT_TIMER (0x1f << 4) #define TBR_TT_COMPOUND_EXCEP (0x20 << 4) #define TBR_TT_INTERRUPT_1 (0x21 << 4) #define TBR_TT_INTERRUPT_2 (0x22 << 4) #define TBR_TT_INTERRUPT_3 (0x23 << 4) #define TBR_TT_INTERRUPT_4 (0x24 << 4) #define TBR_TT_INTERRUPT_5 (0x25 << 4) #define TBR_TT_INTERRUPT_6 (0x26 << 4) #define TBR_TT_INTERRUPT_7 (0x27 << 4) #define TBR_TT_INTERRUPT_8 (0x28 << 4) #define TBR_TT_INTERRUPT_9 (0x29 << 4) #define TBR_TT_INTERRUPT_10 (0x2a << 4) #define TBR_TT_INTERRUPT_11 (0x2b << 4) #define TBR_TT_INTERRUPT_12 (0x2c << 4) #define TBR_TT_INTERRUPT_13 (0x2d << 4) #define TBR_TT_INTERRUPT_14 (0x2e << 4) #define TBR_TT_INTERRUPT_15 (0x2f << 4) #define TBR_TT_TRAP0 (0x80 << 4) #define TBR_TT_TRAP1 (0x81 << 4) #define TBR_TT_TRAP2 (0x82 << 4) #define TBR_TT_TRAP3 (0x83 << 4) #define TBR_TT_TRAP120 (0xf8 << 4) #define TBR_TT_TRAP121 (0xf9 << 4) #define TBR_TT_TRAP122 (0xfa << 4) #define TBR_TT_TRAP123 (0xfb << 4) #define TBR_TT_TRAP124 (0xfc << 4) #define TBR_TT_TRAP125 (0xfd << 4) #define TBR_TT_TRAP126 (0xfe << 4) #define TBR_TT_BREAK (0xff << 4) #define TBR_TT_ATOMIC_CMPXCHG32 TBR_TT_TRAP120


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