aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc
diff options
context:
space:
mode:
Diffstat (limited to 'sound/soc')
-rw-r--r--sound/soc/fsl/fsl_asrc.c7
-rw-r--r--sound/soc/fsl/fsl_asrc.h7
-rw-r--r--sound/soc/fsl/fsl_ssi.c24
3 files changed, 37 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
index dd1263b95dc7..c1a0e01cb8e7 100644
--- a/sound/soc/fsl/fsl_asrc.c
+++ b/sound/soc/fsl/fsl_asrc.c
@@ -996,6 +996,9 @@ static int fsl_asrc_suspend(struct device *dev)
996{ 996{
997 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 997 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
998 998
999 regmap_read(asrc_priv->regmap, REG_ASRCFG,
1000 &asrc_priv->regcache_cfg);
1001
999 regcache_cache_only(asrc_priv->regmap, true); 1002 regcache_cache_only(asrc_priv->regmap, true);
1000 regcache_mark_dirty(asrc_priv->regmap); 1003 regcache_mark_dirty(asrc_priv->regmap);
1001 1004
@@ -1016,6 +1019,10 @@ static int fsl_asrc_resume(struct device *dev)
1016 regcache_cache_only(asrc_priv->regmap, false); 1019 regcache_cache_only(asrc_priv->regmap, false);
1017 regcache_sync(asrc_priv->regmap); 1020 regcache_sync(asrc_priv->regmap);
1018 1021
1022 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
1023 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1024 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1025
1019 /* Restart enabled pairs */ 1026 /* Restart enabled pairs */
1020 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1027 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1021 ASRCTR_ASRCEi_ALL_MASK, asrctr); 1028 ASRCTR_ASRCEi_ALL_MASK, asrctr);
diff --git a/sound/soc/fsl/fsl_asrc.h b/sound/soc/fsl/fsl_asrc.h
index 68802cdc3f28..0f163abe4ba3 100644
--- a/sound/soc/fsl/fsl_asrc.h
+++ b/sound/soc/fsl/fsl_asrc.h
@@ -132,10 +132,13 @@
132#define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i)) 132#define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i))
133#define ASRCFG_NDPRi_SHIFT(i) (18 + i) 133#define ASRCFG_NDPRi_SHIFT(i) (18 + i)
134#define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i)) 134#define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i))
135#define ASRCFG_NDPRi_ALL_SHIFT 18
136#define ASRCFG_NDPRi_ALL_MASK (7 << ASRCFG_NDPRi_ALL_SHIFT)
135#define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i)) 137#define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i))
136#define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2)) 138#define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2))
137#define ASRCFG_POSTMODi_WIDTH 2 139#define ASRCFG_POSTMODi_WIDTH 2
138#define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i)) 140#define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
141#define ASRCFG_POSTMODi_ALL_MASK (ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
139#define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i)) 142#define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
140#define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i)) 143#define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i))
141#define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i)) 144#define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i))
@@ -143,6 +146,7 @@
143#define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2)) 146#define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2))
144#define ASRCFG_PREMODi_WIDTH 2 147#define ASRCFG_PREMODi_WIDTH 2
145#define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i)) 148#define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
149#define ASRCFG_PREMODi_ALL_MASK (ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
146#define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i)) 150#define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
147#define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i)) 151#define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i))
148#define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i)) 152#define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i))
@@ -434,6 +438,7 @@ struct fsl_asrc_pair {
434 * @channel_avail: non-occupied channel numbers 438 * @channel_avail: non-occupied channel numbers
435 * @asrc_rate: default sample rate for ASoC Back-Ends 439 * @asrc_rate: default sample rate for ASoC Back-Ends
436 * @asrc_width: default sample width for ASoC Back-Ends 440 * @asrc_width: default sample width for ASoC Back-Ends
441 * @regcache_cfg: store register value of REG_ASRCFG
437 */ 442 */
438struct fsl_asrc { 443struct fsl_asrc {
439 struct snd_dmaengine_dai_dma_data dma_params_rx; 444 struct snd_dmaengine_dai_dma_data dma_params_rx;
@@ -453,6 +458,8 @@ struct fsl_asrc {
453 458
454 int asrc_rate; 459 int asrc_rate;
455 int asrc_width; 460 int asrc_width;
461
462 u32 regcache_cfg;
456}; 463};
457 464
458extern struct snd_soc_platform_driver fsl_asrc_platform; 465extern struct snd_soc_platform_driver fsl_asrc_platform;
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index e3abad5f980a..40dfd8a36484 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -146,6 +146,7 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
146 case CCSR_SSI_SRX1: 146 case CCSR_SSI_SRX1:
147 case CCSR_SSI_SISR: 147 case CCSR_SSI_SISR:
148 case CCSR_SSI_SFCSR: 148 case CCSR_SSI_SFCSR:
149 case CCSR_SSI_SACNT:
149 case CCSR_SSI_SACADD: 150 case CCSR_SSI_SACADD:
150 case CCSR_SSI_SACDAT: 151 case CCSR_SSI_SACDAT:
151 case CCSR_SSI_SATAG: 152 case CCSR_SSI_SATAG:
@@ -156,6 +157,21 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
156 } 157 }
157} 158}
158 159
160static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
161{
162 switch (reg) {
163 case CCSR_SSI_SRX0:
164 case CCSR_SSI_SRX1:
165 case CCSR_SSI_SISR:
166 case CCSR_SSI_SACADD:
167 case CCSR_SSI_SACDAT:
168 case CCSR_SSI_SATAG:
169 return true;
170 default:
171 return false;
172 }
173}
174
159static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 175static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
160{ 176{
161 switch (reg) { 177 switch (reg) {
@@ -178,6 +194,7 @@ static const struct regmap_config fsl_ssi_regconfig = {
178 .num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults), 194 .num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults),
179 .readable_reg = fsl_ssi_readable_reg, 195 .readable_reg = fsl_ssi_readable_reg,
180 .volatile_reg = fsl_ssi_volatile_reg, 196 .volatile_reg = fsl_ssi_volatile_reg,
197 .precious_reg = fsl_ssi_precious_reg,
181 .writeable_reg = fsl_ssi_writeable_reg, 198 .writeable_reg = fsl_ssi_writeable_reg,
182 .cache_type = REGCACHE_RBTREE, 199 .cache_type = REGCACHE_RBTREE,
183}; 200};
@@ -239,8 +256,9 @@ struct fsl_ssi_private {
239 unsigned int baudclk_streams; 256 unsigned int baudclk_streams;
240 unsigned int bitclk_freq; 257 unsigned int bitclk_freq;
241 258
242 /*regcache for SFCSR*/ 259 /* regcache for volatile regs */
243 u32 regcache_sfcsr; 260 u32 regcache_sfcsr;
261 u32 regcache_sacnt;
244 262
245 /* DMA params */ 263 /* DMA params */
246 struct snd_dmaengine_dai_dma_data dma_params_tx; 264 struct snd_dmaengine_dai_dma_data dma_params_tx;
@@ -1587,6 +1605,8 @@ static int fsl_ssi_suspend(struct device *dev)
1587 1605
1588 regmap_read(regs, CCSR_SSI_SFCSR, 1606 regmap_read(regs, CCSR_SSI_SFCSR,
1589 &ssi_private->regcache_sfcsr); 1607 &ssi_private->regcache_sfcsr);
1608 regmap_read(regs, CCSR_SSI_SACNT,
1609 &ssi_private->regcache_sacnt);
1590 1610
1591 regcache_cache_only(regs, true); 1611 regcache_cache_only(regs, true);
1592 regcache_mark_dirty(regs); 1612 regcache_mark_dirty(regs);
@@ -1605,6 +1625,8 @@ static int fsl_ssi_resume(struct device *dev)
1605 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK | 1625 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1606 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK, 1626 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1607 ssi_private->regcache_sfcsr); 1627 ssi_private->regcache_sfcsr);
1628 regmap_write(regs, CCSR_SSI_SACNT,
1629 ssi_private->regcache_sacnt);
1608 1630
1609 return regcache_sync(regs); 1631 return regcache_sync(regs);
1610} 1632}