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-rw-r--r--sound/soc/mxs/Kconfig20
-rw-r--r--sound/soc/mxs/Makefile10
-rw-r--r--sound/soc/mxs/mxs-pcm.c359
-rw-r--r--sound/soc/mxs/mxs-pcm.h43
-rw-r--r--sound/soc/mxs/mxs-saif.c798
-rw-r--r--sound/soc/mxs/mxs-saif.h134
-rw-r--r--sound/soc/mxs/mxs-sgtl5000.c173
7 files changed, 1537 insertions, 0 deletions
diff --git a/sound/soc/mxs/Kconfig b/sound/soc/mxs/Kconfig
new file mode 100644
index 000000000000..e4ba8d5f25fa
--- /dev/null
+++ b/sound/soc/mxs/Kconfig
@@ -0,0 +1,20 @@
1menuconfig SND_MXS_SOC
2 tristate "SoC Audio for Freescale MXS CPUs"
3 depends on ARCH_MXS
4 select SND_PCM
5 help
6 Say Y or M if you want to add support for codecs attached to
7 the MXS SAIF interface.
8
9
10if SND_MXS_SOC
11
12config SND_SOC_MXS_SGTL5000
13 tristate "SoC Audio support for i.MX boards with sgtl5000"
14 depends on I2C
15 select SND_SOC_SGTL5000
16 help
17 Say Y if you want to add support for SoC audio on an MXS board with
18 a sgtl5000 codec.
19
20endif # SND_MXS_SOC
diff --git a/sound/soc/mxs/Makefile b/sound/soc/mxs/Makefile
new file mode 100644
index 000000000000..565b5b51e8b7
--- /dev/null
+++ b/sound/soc/mxs/Makefile
@@ -0,0 +1,10 @@
1# MXS Platform Support
2snd-soc-mxs-objs := mxs-saif.o
3snd-soc-mxs-pcm-objs := mxs-pcm.o
4
5obj-$(CONFIG_SND_MXS_SOC) += snd-soc-mxs.o snd-soc-mxs-pcm.o
6
7# i.MX Machine Support
8snd-soc-mxs-sgtl5000-objs := mxs-sgtl5000.o
9
10obj-$(CONFIG_SND_SOC_MXS_SGTL5000) += snd-soc-mxs-sgtl5000.o
diff --git a/sound/soc/mxs/mxs-pcm.c b/sound/soc/mxs/mxs-pcm.c
new file mode 100644
index 000000000000..dea5aa4aa647
--- /dev/null
+++ b/sound/soc/mxs/mxs-pcm.c
@@ -0,0 +1,359 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Based on sound/soc/imx/imx-pcm-dma-mx2.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30#include <linux/dmaengine.h>
31
32#include <sound/core.h>
33#include <sound/initval.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/soc.h>
37
38#include <mach/dma.h>
39#include "mxs-pcm.h"
40
41static struct snd_pcm_hardware snd_mxs_hardware = {
42 .info = SNDRV_PCM_INFO_MMAP |
43 SNDRV_PCM_INFO_MMAP_VALID |
44 SNDRV_PCM_INFO_PAUSE |
45 SNDRV_PCM_INFO_RESUME |
46 SNDRV_PCM_INFO_INTERLEAVED,
47 .formats = SNDRV_PCM_FMTBIT_S16_LE |
48 SNDRV_PCM_FMTBIT_S20_3LE |
49 SNDRV_PCM_FMTBIT_S24_LE,
50 .channels_min = 2,
51 .channels_max = 2,
52 .period_bytes_min = 32,
53 .period_bytes_max = 8192,
54 .periods_min = 1,
55 .periods_max = 52,
56 .buffer_bytes_max = 64 * 1024,
57 .fifo_size = 32,
58
59};
60
61static void audio_dma_irq(void *data)
62{
63 struct snd_pcm_substream *substream = (struct snd_pcm_substream *)data;
64 struct snd_pcm_runtime *runtime = substream->runtime;
65 struct mxs_pcm_runtime_data *iprtd = runtime->private_data;
66
67 iprtd->offset += iprtd->period_bytes;
68 iprtd->offset %= iprtd->period_bytes * iprtd->periods;
69 snd_pcm_period_elapsed(substream);
70}
71
72static bool filter(struct dma_chan *chan, void *param)
73{
74 struct mxs_pcm_runtime_data *iprtd = param;
75 struct mxs_pcm_dma_params *dma_params = iprtd->dma_params;
76
77 if (!mxs_dma_is_apbx(chan))
78 return false;
79
80 if (chan->chan_id != dma_params->chan_num)
81 return false;
82
83 chan->private = &iprtd->dma_data;
84
85 return true;
86}
87
88static int mxs_dma_alloc(struct snd_pcm_substream *substream,
89 struct snd_pcm_hw_params *params)
90{
91 struct snd_soc_pcm_runtime *rtd = substream->private_data;
92 struct snd_pcm_runtime *runtime = substream->runtime;
93 struct mxs_pcm_runtime_data *iprtd = runtime->private_data;
94 dma_cap_mask_t mask;
95
96 iprtd->dma_params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
97
98 dma_cap_zero(mask);
99 dma_cap_set(DMA_SLAVE, mask);
100 iprtd->dma_data.chan_irq = iprtd->dma_params->chan_irq;
101 iprtd->dma_chan = dma_request_channel(mask, filter, iprtd);
102 if (!iprtd->dma_chan)
103 return -EINVAL;
104
105 return 0;
106}
107
108static int snd_mxs_pcm_hw_params(struct snd_pcm_substream *substream,
109 struct snd_pcm_hw_params *params)
110{
111 struct snd_pcm_runtime *runtime = substream->runtime;
112 struct mxs_pcm_runtime_data *iprtd = runtime->private_data;
113 unsigned long dma_addr;
114 struct dma_chan *chan;
115 int ret;
116
117 ret = mxs_dma_alloc(substream, params);
118 if (ret)
119 return ret;
120 chan = iprtd->dma_chan;
121
122 iprtd->size = params_buffer_bytes(params);
123 iprtd->periods = params_periods(params);
124 iprtd->period_bytes = params_period_bytes(params);
125 iprtd->offset = 0;
126 iprtd->period_time = HZ / (params_rate(params) /
127 params_period_size(params));
128
129 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
130
131 dma_addr = runtime->dma_addr;
132
133 iprtd->buf = substream->dma_buffer.area;
134
135 iprtd->desc = chan->device->device_prep_dma_cyclic(chan, dma_addr,
136 iprtd->period_bytes * iprtd->periods,
137 iprtd->period_bytes,
138 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
139 DMA_TO_DEVICE : DMA_FROM_DEVICE);
140 if (!iprtd->desc) {
141 dev_err(&chan->dev->device, "cannot prepare slave dma\n");
142 return -EINVAL;
143 }
144
145 iprtd->desc->callback = audio_dma_irq;
146 iprtd->desc->callback_param = substream;
147
148 return 0;
149}
150
151static int snd_mxs_pcm_hw_free(struct snd_pcm_substream *substream)
152{
153 struct snd_pcm_runtime *runtime = substream->runtime;
154 struct mxs_pcm_runtime_data *iprtd = runtime->private_data;
155
156 if (iprtd->dma_chan) {
157 dma_release_channel(iprtd->dma_chan);
158 iprtd->dma_chan = NULL;
159 }
160
161 return 0;
162}
163
164static int snd_mxs_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
165{
166 struct snd_pcm_runtime *runtime = substream->runtime;
167 struct mxs_pcm_runtime_data *iprtd = runtime->private_data;
168
169 switch (cmd) {
170 case SNDRV_PCM_TRIGGER_START:
171 case SNDRV_PCM_TRIGGER_RESUME:
172 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
173 dmaengine_submit(iprtd->desc);
174
175 break;
176 case SNDRV_PCM_TRIGGER_STOP:
177 case SNDRV_PCM_TRIGGER_SUSPEND:
178 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
179 dmaengine_terminate_all(iprtd->dma_chan);
180
181 break;
182 default:
183 return -EINVAL;
184 }
185
186 return 0;
187}
188
189static snd_pcm_uframes_t snd_mxs_pcm_pointer(
190 struct snd_pcm_substream *substream)
191{
192 struct snd_pcm_runtime *runtime = substream->runtime;
193 struct mxs_pcm_runtime_data *iprtd = runtime->private_data;
194
195 return bytes_to_frames(substream->runtime, iprtd->offset);
196}
197
198static int snd_mxs_open(struct snd_pcm_substream *substream)
199{
200 struct snd_pcm_runtime *runtime = substream->runtime;
201 struct mxs_pcm_runtime_data *iprtd;
202 int ret;
203
204 iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
205 if (iprtd == NULL)
206 return -ENOMEM;
207 runtime->private_data = iprtd;
208
209 ret = snd_pcm_hw_constraint_integer(substream->runtime,
210 SNDRV_PCM_HW_PARAM_PERIODS);
211 if (ret < 0) {
212 kfree(iprtd);
213 return ret;
214 }
215
216 snd_soc_set_runtime_hwparams(substream, &snd_mxs_hardware);
217
218 return 0;
219}
220
221static int snd_mxs_close(struct snd_pcm_substream *substream)
222{
223 struct snd_pcm_runtime *runtime = substream->runtime;
224 struct mxs_pcm_runtime_data *iprtd = runtime->private_data;
225
226 kfree(iprtd);
227
228 return 0;
229}
230
231static int snd_mxs_pcm_mmap(struct snd_pcm_substream *substream,
232 struct vm_area_struct *vma)
233{
234 struct snd_pcm_runtime *runtime = substream->runtime;
235
236 return dma_mmap_writecombine(substream->pcm->card->dev, vma,
237 runtime->dma_area,
238 runtime->dma_addr,
239 runtime->dma_bytes);
240}
241
242static struct snd_pcm_ops mxs_pcm_ops = {
243 .open = snd_mxs_open,
244 .close = snd_mxs_close,
245 .ioctl = snd_pcm_lib_ioctl,
246 .hw_params = snd_mxs_pcm_hw_params,
247 .hw_free = snd_mxs_pcm_hw_free,
248 .trigger = snd_mxs_pcm_trigger,
249 .pointer = snd_mxs_pcm_pointer,
250 .mmap = snd_mxs_pcm_mmap,
251};
252
253static int mxs_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
254{
255 struct snd_pcm_substream *substream = pcm->streams[stream].substream;
256 struct snd_dma_buffer *buf = &substream->dma_buffer;
257 size_t size = snd_mxs_hardware.buffer_bytes_max;
258
259 buf->dev.type = SNDRV_DMA_TYPE_DEV;
260 buf->dev.dev = pcm->card->dev;
261 buf->private_data = NULL;
262 buf->area = dma_alloc_writecombine(pcm->card->dev, size,
263 &buf->addr, GFP_KERNEL);
264 if (!buf->area)
265 return -ENOMEM;
266 buf->bytes = size;
267
268 return 0;
269}
270
271static u64 mxs_pcm_dmamask = DMA_BIT_MASK(32);
272static int mxs_pcm_new(struct snd_soc_pcm_runtime *rtd)
273{
274 struct snd_card *card = rtd->card->snd_card;
275 struct snd_pcm *pcm = rtd->pcm;
276 int ret = 0;
277
278 if (!card->dev->dma_mask)
279 card->dev->dma_mask = &mxs_pcm_dmamask;
280 if (!card->dev->coherent_dma_mask)
281 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
282
283 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
284 ret = mxs_pcm_preallocate_dma_buffer(pcm,
285 SNDRV_PCM_STREAM_PLAYBACK);
286 if (ret)
287 goto out;
288 }
289
290 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
291 ret = mxs_pcm_preallocate_dma_buffer(pcm,
292 SNDRV_PCM_STREAM_CAPTURE);
293 if (ret)
294 goto out;
295 }
296
297out:
298 return ret;
299}
300
301static void mxs_pcm_free(struct snd_pcm *pcm)
302{
303 struct snd_pcm_substream *substream;
304 struct snd_dma_buffer *buf;
305 int stream;
306
307 for (stream = 0; stream < 2; stream++) {
308 substream = pcm->streams[stream].substream;
309 if (!substream)
310 continue;
311
312 buf = &substream->dma_buffer;
313 if (!buf->area)
314 continue;
315
316 dma_free_writecombine(pcm->card->dev, buf->bytes,
317 buf->area, buf->addr);
318 buf->area = NULL;
319 }
320}
321
322static struct snd_soc_platform_driver mxs_soc_platform = {
323 .ops = &mxs_pcm_ops,
324 .pcm_new = mxs_pcm_new,
325 .pcm_free = mxs_pcm_free,
326};
327
328static int __devinit mxs_soc_platform_probe(struct platform_device *pdev)
329{
330 return snd_soc_register_platform(&pdev->dev, &mxs_soc_platform);
331}
332
333static int __devexit mxs_soc_platform_remove(struct platform_device *pdev)
334{
335 snd_soc_unregister_platform(&pdev->dev);
336
337 return 0;
338}
339
340static struct platform_driver mxs_pcm_driver = {
341 .driver = {
342 .name = "mxs-pcm-audio",
343 .owner = THIS_MODULE,
344 },
345 .probe = mxs_soc_platform_probe,
346 .remove = __devexit_p(mxs_soc_platform_remove),
347};
348
349static int __init snd_mxs_pcm_init(void)
350{
351 return platform_driver_register(&mxs_pcm_driver);
352}
353module_init(snd_mxs_pcm_init);
354
355static void __exit snd_mxs_pcm_exit(void)
356{
357 platform_driver_unregister(&mxs_pcm_driver);
358}
359module_exit(snd_mxs_pcm_exit);
diff --git a/sound/soc/mxs/mxs-pcm.h b/sound/soc/mxs/mxs-pcm.h
new file mode 100644
index 000000000000..f55ac4f7a76a
--- /dev/null
+++ b/sound/soc/mxs/mxs-pcm.h
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef _MXS_PCM_H
20#define _MXS_PCM_H
21
22#include <mach/dma.h>
23
24struct mxs_pcm_dma_params {
25 int chan_irq;
26 int chan_num;
27};
28
29struct mxs_pcm_runtime_data {
30 int period_bytes;
31 int periods;
32 int dma;
33 unsigned long offset;
34 unsigned long size;
35 void *buf;
36 int period_time;
37 struct dma_async_tx_descriptor *desc;
38 struct dma_chan *dma_chan;
39 struct mxs_dma_data dma_data;
40 struct mxs_pcm_dma_params *dma_params;
41};
42
43#endif
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
new file mode 100644
index 000000000000..76dc74d24fc2
--- /dev/null
+++ b/sound/soc/mxs/mxs-saif.c
@@ -0,0 +1,798 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/dma-mapping.h>
24#include <linux/clk.h>
25#include <linux/delay.h>
26#include <linux/time.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/saif.h>
32#include <mach/dma.h>
33#include <asm/mach-types.h>
34#include <mach/hardware.h>
35#include <mach/mxs.h>
36
37#include "mxs-saif.h"
38
39static struct mxs_saif *mxs_saif[2];
40
41/*
42 * SAIF is a little different with other normal SOC DAIs on clock using.
43 *
44 * For MXS, two SAIF modules are instantiated on-chip.
45 * Each SAIF has a set of clock pins and can be operating in master
46 * mode simultaneously if they are connected to different off-chip codecs.
47 * Also, one of the two SAIFs can master or drive the clock pins while the
48 * other SAIF, in slave mode, receives clocking from the master SAIF.
49 * This also means that both SAIFs must operate at the same sample rate.
50 *
51 * We abstract this as each saif has a master, the master could be
52 * himself or other saifs. In the generic saif driver, saif does not need
53 * to know the different clkmux. Saif only needs to know who is his master
54 * and operating his master to generate the proper clock rate for him.
55 * The master id is provided in mach-specific layer according to different
56 * clkmux setting.
57 */
58
59static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
60 int clk_id, unsigned int freq, int dir)
61{
62 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
63
64 switch (clk_id) {
65 case MXS_SAIF_MCLK:
66 saif->mclk = freq;
67 break;
68 default:
69 return -EINVAL;
70 }
71 return 0;
72}
73
74/*
75 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
76 * is provided by other SAIF, we provide a interface here to get its master
77 * from its master_id.
78 * Note that the master could be himself.
79 */
80static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
81{
82 return mxs_saif[saif->master_id];
83}
84
85/*
86 * Set SAIF clock and MCLK
87 */
88static int mxs_saif_set_clk(struct mxs_saif *saif,
89 unsigned int mclk,
90 unsigned int rate)
91{
92 u32 scr;
93 int ret;
94 struct mxs_saif *master_saif;
95
96 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
97
98 /* Set master saif to generate proper clock */
99 master_saif = mxs_saif_get_master(saif);
100 if (!master_saif)
101 return -EINVAL;
102
103 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
104
105 /* Checking if can playback and capture simutaneously */
106 if (master_saif->ongoing && rate != master_saif->cur_rate) {
107 dev_err(saif->dev,
108 "can not change clock, master saif%d(rate %d) is ongoing\n",
109 master_saif->id, master_saif->cur_rate);
110 return -EINVAL;
111 }
112
113 scr = __raw_readl(master_saif->base + SAIF_CTRL);
114 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
115 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
116
117 /*
118 * Set SAIF clock
119 *
120 * The SAIF clock should be either 384*fs or 512*fs.
121 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
122 * For 32x mclk, set saif clk as 512*fs.
123 * For 48x mclk, set saif clk as 384*fs.
124 *
125 * If MCLK is not used, we just set saif clk to 512*fs.
126 */
127 if (master_saif->mclk_in_use) {
128 if (mclk % 32 == 0) {
129 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
130 ret = clk_set_rate(master_saif->clk, 512 * rate);
131 } else if (mclk % 48 == 0) {
132 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
133 ret = clk_set_rate(master_saif->clk, 384 * rate);
134 } else {
135 /* SAIF MCLK should be either 32x or 48x */
136 return -EINVAL;
137 }
138 } else {
139 ret = clk_set_rate(master_saif->clk, 512 * rate);
140 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
141 }
142
143 if (ret)
144 return ret;
145
146 master_saif->cur_rate = rate;
147
148 if (!master_saif->mclk_in_use) {
149 __raw_writel(scr, master_saif->base + SAIF_CTRL);
150 return 0;
151 }
152
153 /*
154 * Program the over-sample rate for MCLK output
155 *
156 * The available MCLK range is 32x, 48x... 512x. The rate
157 * could be from 8kHz to 192kH.
158 */
159 switch (mclk / rate) {
160 case 32:
161 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
162 break;
163 case 64:
164 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
165 break;
166 case 128:
167 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
168 break;
169 case 256:
170 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
171 break;
172 case 512:
173 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
174 break;
175 case 48:
176 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
177 break;
178 case 96:
179 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
180 break;
181 case 192:
182 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
183 break;
184 case 384:
185 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
186 break;
187 default:
188 return -EINVAL;
189 }
190
191 __raw_writel(scr, master_saif->base + SAIF_CTRL);
192
193 return 0;
194}
195
196/*
197 * Put and disable MCLK.
198 */
199int mxs_saif_put_mclk(unsigned int saif_id)
200{
201 struct mxs_saif *saif = mxs_saif[saif_id];
202 u32 stat;
203
204 if (!saif)
205 return -EINVAL;
206
207 stat = __raw_readl(saif->base + SAIF_STAT);
208 if (stat & BM_SAIF_STAT_BUSY) {
209 dev_err(saif->dev, "error: busy\n");
210 return -EBUSY;
211 }
212
213 clk_disable(saif->clk);
214
215 /* disable MCLK output */
216 __raw_writel(BM_SAIF_CTRL_CLKGATE,
217 saif->base + SAIF_CTRL + MXS_SET_ADDR);
218 __raw_writel(BM_SAIF_CTRL_RUN,
219 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
220
221 saif->mclk_in_use = 0;
222 return 0;
223}
224
225/*
226 * Get MCLK and set clock rate, then enable it
227 *
228 * This interface is used for codecs who are using MCLK provided
229 * by saif.
230 */
231int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
232 unsigned int rate)
233{
234 struct mxs_saif *saif = mxs_saif[saif_id];
235 u32 stat;
236 int ret;
237 struct mxs_saif *master_saif;
238
239 if (!saif)
240 return -EINVAL;
241
242 /* Clear Reset */
243 __raw_writel(BM_SAIF_CTRL_SFTRST,
244 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
245
246 /* FIXME: need clear clk gate for register r/w */
247 __raw_writel(BM_SAIF_CTRL_CLKGATE,
248 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
249
250 master_saif = mxs_saif_get_master(saif);
251 if (saif != master_saif) {
252 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
253 return -EINVAL;
254 }
255
256 stat = __raw_readl(saif->base + SAIF_STAT);
257 if (stat & BM_SAIF_STAT_BUSY) {
258 dev_err(saif->dev, "error: busy\n");
259 return -EBUSY;
260 }
261
262 saif->mclk_in_use = 1;
263 ret = mxs_saif_set_clk(saif, mclk, rate);
264 if (ret)
265 return ret;
266
267 ret = clk_enable(saif->clk);
268 if (ret)
269 return ret;
270
271 /* enable MCLK output */
272 __raw_writel(BM_SAIF_CTRL_RUN,
273 saif->base + SAIF_CTRL + MXS_SET_ADDR);
274
275 return 0;
276}
277
278/*
279 * SAIF DAI format configuration.
280 * Should only be called when port is inactive.
281 */
282static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
283{
284 u32 scr, stat;
285 u32 scr0;
286 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
287
288 stat = __raw_readl(saif->base + SAIF_STAT);
289 if (stat & BM_SAIF_STAT_BUSY) {
290 dev_err(cpu_dai->dev, "error: busy\n");
291 return -EBUSY;
292 }
293
294 scr0 = __raw_readl(saif->base + SAIF_CTRL);
295 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
296 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
297 scr = 0;
298
299 /* DAI mode */
300 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
301 case SND_SOC_DAIFMT_I2S:
302 /* data frame low 1clk before data */
303 scr |= BM_SAIF_CTRL_DELAY;
304 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
305 break;
306 case SND_SOC_DAIFMT_LEFT_J:
307 /* data frame high with data */
308 scr &= ~BM_SAIF_CTRL_DELAY;
309 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
310 scr &= ~BM_SAIF_CTRL_JUSTIFY;
311 break;
312 default:
313 return -EINVAL;
314 }
315
316 /* DAI clock inversion */
317 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
318 case SND_SOC_DAIFMT_IB_IF:
319 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
320 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
321 break;
322 case SND_SOC_DAIFMT_IB_NF:
323 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
324 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
325 break;
326 case SND_SOC_DAIFMT_NB_IF:
327 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
328 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
329 break;
330 case SND_SOC_DAIFMT_NB_NF:
331 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
332 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
333 break;
334 }
335
336 /*
337 * Note: We simply just support master mode since SAIF TX can only
338 * work as master.
339 * Here the master is relative to codec side.
340 * Saif internally could be slave when working on EXTMASTER mode.
341 * We just hide this to machine driver.
342 */
343 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
344 case SND_SOC_DAIFMT_CBS_CFS:
345 if (saif->id == saif->master_id)
346 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
347 else
348 scr |= BM_SAIF_CTRL_SLAVE_MODE;
349
350 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
351 break;
352 default:
353 return -EINVAL;
354 }
355
356 return 0;
357}
358
359static int mxs_saif_startup(struct snd_pcm_substream *substream,
360 struct snd_soc_dai *cpu_dai)
361{
362 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
363 snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param);
364
365 /* clear error status to 0 for each re-open */
366 saif->fifo_underrun = 0;
367 saif->fifo_overrun = 0;
368
369 /* Clear Reset for normal operations */
370 __raw_writel(BM_SAIF_CTRL_SFTRST,
371 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
372
373 /* clear clock gate */
374 __raw_writel(BM_SAIF_CTRL_CLKGATE,
375 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
376
377 return 0;
378}
379
380/*
381 * Should only be called when port is inactive.
382 * although can be called multiple times by upper layers.
383 */
384static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
385 struct snd_pcm_hw_params *params,
386 struct snd_soc_dai *cpu_dai)
387{
388 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
389 u32 scr, stat;
390 int ret;
391
392 /* mclk should already be set */
393 if (!saif->mclk && saif->mclk_in_use) {
394 dev_err(cpu_dai->dev, "set mclk first\n");
395 return -EINVAL;
396 }
397
398 stat = __raw_readl(saif->base + SAIF_STAT);
399 if (stat & BM_SAIF_STAT_BUSY) {
400 dev_err(cpu_dai->dev, "error: busy\n");
401 return -EBUSY;
402 }
403
404 /*
405 * Set saif clk based on sample rate.
406 * If mclk is used, we also set mclk, if not, saif->mclk is
407 * default 0, means not used.
408 */
409 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
410 if (ret) {
411 dev_err(cpu_dai->dev, "unable to get proper clk\n");
412 return ret;
413 }
414
415 scr = __raw_readl(saif->base + SAIF_CTRL);
416
417 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
418 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
419 switch (params_format(params)) {
420 case SNDRV_PCM_FORMAT_S16_LE:
421 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
422 break;
423 case SNDRV_PCM_FORMAT_S20_3LE:
424 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
425 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
426 break;
427 case SNDRV_PCM_FORMAT_S24_LE:
428 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
429 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
430 break;
431 default:
432 return -EINVAL;
433 }
434
435 /* Tx/Rx config */
436 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
437 /* enable TX mode */
438 scr &= ~BM_SAIF_CTRL_READ_MODE;
439 } else {
440 /* enable RX mode */
441 scr |= BM_SAIF_CTRL_READ_MODE;
442 }
443
444 __raw_writel(scr, saif->base + SAIF_CTRL);
445 return 0;
446}
447
448static int mxs_saif_prepare(struct snd_pcm_substream *substream,
449 struct snd_soc_dai *cpu_dai)
450{
451 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
452
453 /* enable FIFO error irqs */
454 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
455 saif->base + SAIF_CTRL + MXS_SET_ADDR);
456
457 return 0;
458}
459
460static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
461 struct snd_soc_dai *cpu_dai)
462{
463 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
464 struct mxs_saif *master_saif;
465 u32 delay;
466
467 master_saif = mxs_saif_get_master(saif);
468 if (!master_saif)
469 return -EINVAL;
470
471 switch (cmd) {
472 case SNDRV_PCM_TRIGGER_START:
473 case SNDRV_PCM_TRIGGER_RESUME:
474 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
475 dev_dbg(cpu_dai->dev, "start\n");
476
477 clk_enable(master_saif->clk);
478 if (!master_saif->mclk_in_use)
479 __raw_writel(BM_SAIF_CTRL_RUN,
480 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
481
482 /*
483 * If the saif's master is not himself, we also need to enable
484 * itself clk for its internal basic logic to work.
485 */
486 if (saif != master_saif) {
487 clk_enable(saif->clk);
488 __raw_writel(BM_SAIF_CTRL_RUN,
489 saif->base + SAIF_CTRL + MXS_SET_ADDR);
490 }
491
492 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
493 /*
494 * write a data to saif data register to trigger
495 * the transfer
496 */
497 __raw_writel(0, saif->base + SAIF_DATA);
498 } else {
499 /*
500 * read a data from saif data register to trigger
501 * the receive
502 */
503 __raw_readl(saif->base + SAIF_DATA);
504 }
505
506 master_saif->ongoing = 1;
507
508 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
509 __raw_readl(saif->base + SAIF_CTRL),
510 __raw_readl(saif->base + SAIF_STAT));
511
512 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
513 __raw_readl(master_saif->base + SAIF_CTRL),
514 __raw_readl(master_saif->base + SAIF_STAT));
515 break;
516 case SNDRV_PCM_TRIGGER_SUSPEND:
517 case SNDRV_PCM_TRIGGER_STOP:
518 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
519 dev_dbg(cpu_dai->dev, "stop\n");
520
521 /* wait a while for the current sample to complete */
522 delay = USEC_PER_SEC / master_saif->cur_rate;
523
524 if (!master_saif->mclk_in_use) {
525 __raw_writel(BM_SAIF_CTRL_RUN,
526 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
527 udelay(delay);
528 }
529 clk_disable(master_saif->clk);
530
531 if (saif != master_saif) {
532 __raw_writel(BM_SAIF_CTRL_RUN,
533 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
534 udelay(delay);
535 clk_disable(saif->clk);
536 }
537
538 master_saif->ongoing = 0;
539
540 break;
541 default:
542 return -EINVAL;
543 }
544
545 return 0;
546}
547
548#define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
549#define MXS_SAIF_FORMATS \
550 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
551 SNDRV_PCM_FMTBIT_S24_LE)
552
553static struct snd_soc_dai_ops mxs_saif_dai_ops = {
554 .startup = mxs_saif_startup,
555 .trigger = mxs_saif_trigger,
556 .prepare = mxs_saif_prepare,
557 .hw_params = mxs_saif_hw_params,
558 .set_sysclk = mxs_saif_set_dai_sysclk,
559 .set_fmt = mxs_saif_set_dai_fmt,
560};
561
562static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
563{
564 struct mxs_saif *saif = dev_get_drvdata(dai->dev);
565
566 snd_soc_dai_set_drvdata(dai, saif);
567
568 return 0;
569}
570
571static struct snd_soc_dai_driver mxs_saif_dai = {
572 .name = "mxs-saif",
573 .probe = mxs_saif_dai_probe,
574 .playback = {
575 .channels_min = 2,
576 .channels_max = 2,
577 .rates = MXS_SAIF_RATES,
578 .formats = MXS_SAIF_FORMATS,
579 },
580 .capture = {
581 .channels_min = 2,
582 .channels_max = 2,
583 .rates = MXS_SAIF_RATES,
584 .formats = MXS_SAIF_FORMATS,
585 },
586 .ops = &mxs_saif_dai_ops,
587};
588
589static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
590{
591 struct mxs_saif *saif = dev_id;
592 unsigned int stat;
593
594 stat = __raw_readl(saif->base + SAIF_STAT);
595 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
596 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
597 return IRQ_NONE;
598
599 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
600 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
601 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
602 saif->base + SAIF_STAT + MXS_CLR_ADDR);
603 }
604
605 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
606 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
607 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
608 saif->base + SAIF_STAT + MXS_CLR_ADDR);
609 }
610
611 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
612 __raw_readl(saif->base + SAIF_CTRL),
613 __raw_readl(saif->base + SAIF_STAT));
614
615 return IRQ_HANDLED;
616}
617
618static int mxs_saif_probe(struct platform_device *pdev)
619{
620 struct resource *iores, *dmares;
621 struct mxs_saif *saif;
622 struct mxs_saif_platform_data *pdata;
623 int ret = 0;
624
625 if (pdev->id >= ARRAY_SIZE(mxs_saif))
626 return -EINVAL;
627
628 pdata = pdev->dev.platform_data;
629 if (pdata && pdata->init) {
630 ret = pdata->init();
631 if (ret)
632 return ret;
633 }
634
635 saif = kzalloc(sizeof(*saif), GFP_KERNEL);
636 if (!saif)
637 return -ENOMEM;
638
639 mxs_saif[pdev->id] = saif;
640 saif->id = pdev->id;
641
642 saif->master_id = saif->id;
643 if (pdata && pdata->get_master_id) {
644 saif->master_id = pdata->get_master_id(saif->id);
645 if (saif->master_id < 0 ||
646 saif->master_id >= ARRAY_SIZE(mxs_saif))
647 return -EINVAL;
648 }
649
650 saif->clk = clk_get(&pdev->dev, NULL);
651 if (IS_ERR(saif->clk)) {
652 ret = PTR_ERR(saif->clk);
653 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
654 ret);
655 goto failed_clk;
656 }
657
658 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
659 if (!iores) {
660 ret = -ENODEV;
661 dev_err(&pdev->dev, "failed to get io resource: %d\n",
662 ret);
663 goto failed_get_resource;
664 }
665
666 if (!request_mem_region(iores->start, resource_size(iores),
667 "mxs-saif")) {
668 dev_err(&pdev->dev, "request_mem_region failed\n");
669 ret = -EBUSY;
670 goto failed_get_resource;
671 }
672
673 saif->base = ioremap(iores->start, resource_size(iores));
674 if (!saif->base) {
675 dev_err(&pdev->dev, "ioremap failed\n");
676 ret = -ENODEV;
677 goto failed_ioremap;
678 }
679
680 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
681 if (!dmares) {
682 ret = -ENODEV;
683 dev_err(&pdev->dev, "failed to get dma resource: %d\n",
684 ret);
685 goto failed_ioremap;
686 }
687 saif->dma_param.chan_num = dmares->start;
688
689 saif->irq = platform_get_irq(pdev, 0);
690 if (saif->irq < 0) {
691 ret = saif->irq;
692 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
693 ret);
694 goto failed_get_irq1;
695 }
696
697 saif->dev = &pdev->dev;
698 ret = request_irq(saif->irq, mxs_saif_irq, 0, "mxs-saif", saif);
699 if (ret) {
700 dev_err(&pdev->dev, "failed to request irq\n");
701 goto failed_get_irq1;
702 }
703
704 saif->dma_param.chan_irq = platform_get_irq(pdev, 1);
705 if (saif->dma_param.chan_irq < 0) {
706 ret = saif->dma_param.chan_irq;
707 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
708 ret);
709 goto failed_get_irq2;
710 }
711
712 platform_set_drvdata(pdev, saif);
713
714 ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai);
715 if (ret) {
716 dev_err(&pdev->dev, "register DAI failed\n");
717 goto failed_register;
718 }
719
720 saif->soc_platform_pdev = platform_device_alloc(
721 "mxs-pcm-audio", pdev->id);
722 if (!saif->soc_platform_pdev) {
723 ret = -ENOMEM;
724 goto failed_pdev_alloc;
725 }
726
727 platform_set_drvdata(saif->soc_platform_pdev, saif);
728 ret = platform_device_add(saif->soc_platform_pdev);
729 if (ret) {
730 dev_err(&pdev->dev, "failed to add soc platform device\n");
731 goto failed_pdev_add;
732 }
733
734 return 0;
735
736failed_pdev_add:
737 platform_device_put(saif->soc_platform_pdev);
738failed_pdev_alloc:
739 snd_soc_unregister_dai(&pdev->dev);
740failed_register:
741failed_get_irq2:
742 free_irq(saif->irq, saif);
743failed_get_irq1:
744 iounmap(saif->base);
745failed_ioremap:
746 release_mem_region(iores->start, resource_size(iores));
747failed_get_resource:
748 clk_put(saif->clk);
749failed_clk:
750 kfree(saif);
751
752 return ret;
753}
754
755static int __devexit mxs_saif_remove(struct platform_device *pdev)
756{
757 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
758 struct mxs_saif *saif = platform_get_drvdata(pdev);
759
760 platform_device_unregister(saif->soc_platform_pdev);
761
762 snd_soc_unregister_dai(&pdev->dev);
763
764 iounmap(saif->base);
765 release_mem_region(res->start, resource_size(res));
766 free_irq(saif->irq, saif);
767
768 clk_put(saif->clk);
769 kfree(saif);
770
771 return 0;
772}
773
774static struct platform_driver mxs_saif_driver = {
775 .probe = mxs_saif_probe,
776 .remove = __devexit_p(mxs_saif_remove),
777
778 .driver = {
779 .name = "mxs-saif",
780 .owner = THIS_MODULE,
781 },
782};
783
784static int __init mxs_saif_init(void)
785{
786 return platform_driver_register(&mxs_saif_driver);
787}
788
789static void __exit mxs_saif_exit(void)
790{
791 platform_driver_unregister(&mxs_saif_driver);
792}
793
794module_init(mxs_saif_init);
795module_exit(mxs_saif_exit);
796MODULE_AUTHOR("Freescale Semiconductor, Inc.");
797MODULE_DESCRIPTION("MXS ASoC SAIF driver");
798MODULE_LICENSE("GPL");
diff --git a/sound/soc/mxs/mxs-saif.h b/sound/soc/mxs/mxs-saif.h
new file mode 100644
index 000000000000..12c91e4eb941
--- /dev/null
+++ b/sound/soc/mxs/mxs-saif.h
@@ -0,0 +1,134 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19
20#ifndef _MXS_SAIF_H
21#define _MXS_SAIF_H
22
23#define SAIF_CTRL 0x0
24#define SAIF_STAT 0x10
25#define SAIF_DATA 0x20
26#define SAIF_VERSION 0X30
27
28/* SAIF_CTRL */
29#define BM_SAIF_CTRL_SFTRST 0x80000000
30#define BM_SAIF_CTRL_CLKGATE 0x40000000
31#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27
32#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
33#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \
34 (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
35#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
36#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
37#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
38#define BP_SAIF_CTRL_RSRVD2 21
39#define BM_SAIF_CTRL_RSRVD2 0x00E00000
40
41#define BP_SAIF_CTRL_DMAWAIT_COUNT 16
42#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000
43#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \
44 (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
45#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
46#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000
47#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \
48 (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
49#define BM_SAIF_CTRL_LRCLK_PULSE 0x00002000
50#define BM_SAIF_CTRL_BIT_ORDER 0x00001000
51#define BM_SAIF_CTRL_DELAY 0x00000800
52#define BM_SAIF_CTRL_JUSTIFY 0x00000400
53#define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200
54#define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100
55#define BP_SAIF_CTRL_WORD_LENGTH 4
56#define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0
57#define BF_SAIF_CTRL_WORD_LENGTH(v) \
58 (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
59#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008
60#define BM_SAIF_CTRL_SLAVE_MODE 0x00000004
61#define BM_SAIF_CTRL_READ_MODE 0x00000002
62#define BM_SAIF_CTRL_RUN 0x00000001
63
64/* SAIF_STAT */
65#define BM_SAIF_STAT_PRESENT 0x80000000
66#define BP_SAIF_STAT_RSRVD2 17
67#define BM_SAIF_STAT_RSRVD2 0x7FFE0000
68#define BF_SAIF_STAT_RSRVD2(v) \
69 (((v) << 17) & BM_SAIF_STAT_RSRVD2)
70#define BM_SAIF_STAT_DMA_PREQ 0x00010000
71#define BP_SAIF_STAT_RSRVD1 7
72#define BM_SAIF_STAT_RSRVD1 0x0000FF80
73#define BF_SAIF_STAT_RSRVD1(v) \
74 (((v) << 7) & BM_SAIF_STAT_RSRVD1)
75
76#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040
77#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020
78#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010
79#define BP_SAIF_STAT_RSRVD0 1
80#define BM_SAIF_STAT_RSRVD0 0x0000000E
81#define BF_SAIF_STAT_RSRVD0(v) \
82 (((v) << 1) & BM_SAIF_STAT_RSRVD0)
83#define BM_SAIF_STAT_BUSY 0x00000001
84
85/* SAFI_DATA */
86#define BP_SAIF_DATA_PCM_RIGHT 16
87#define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000
88#define BF_SAIF_DATA_PCM_RIGHT(v) \
89 (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)
90#define BP_SAIF_DATA_PCM_LEFT 0
91#define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF
92#define BF_SAIF_DATA_PCM_LEFT(v) \
93 (((v) << 0) & BM_SAIF_DATA_PCM_LEFT)
94
95/* SAIF_VERSION */
96#define BP_SAIF_VERSION_MAJOR 24
97#define BM_SAIF_VERSION_MAJOR 0xFF000000
98#define BF_SAIF_VERSION_MAJOR(v) \
99 (((v) << 24) & BM_SAIF_VERSION_MAJOR)
100#define BP_SAIF_VERSION_MINOR 16
101#define BM_SAIF_VERSION_MINOR 0x00FF0000
102#define BF_SAIF_VERSION_MINOR(v) \
103 (((v) << 16) & BM_SAIF_VERSION_MINOR)
104#define BP_SAIF_VERSION_STEP 0
105#define BM_SAIF_VERSION_STEP 0x0000FFFF
106#define BF_SAIF_VERSION_STEP(v) \
107 (((v) << 0) & BM_SAIF_VERSION_STEP)
108
109#define MXS_SAIF_MCLK 0
110
111#include "mxs-pcm.h"
112
113struct mxs_saif {
114 struct device *dev;
115 struct clk *clk;
116 unsigned int mclk;
117 unsigned int mclk_in_use;
118 void __iomem *base;
119 int irq;
120 struct mxs_pcm_dma_params dma_param;
121 unsigned int id;
122 unsigned int master_id;
123 unsigned int cur_rate;
124 unsigned int ongoing;
125
126 struct platform_device *soc_platform_pdev;
127 u32 fifo_underrun;
128 u32 fifo_overrun;
129};
130
131extern int mxs_saif_put_mclk(unsigned int saif_id);
132extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
133 unsigned int rate);
134#endif
diff --git a/sound/soc/mxs/mxs-sgtl5000.c b/sound/soc/mxs/mxs-sgtl5000.c
new file mode 100644
index 000000000000..7fbeaec06eb4
--- /dev/null
+++ b/sound/soc/mxs/mxs-sgtl5000.c
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/module.h>
20#include <linux/device.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/soc.h>
24#include <sound/jack.h>
25#include <sound/soc-dapm.h>
26#include <asm/mach-types.h>
27
28#include "../codecs/sgtl5000.h"
29#include "mxs-saif.h"
30
31static int mxs_sgtl5000_hw_params(struct snd_pcm_substream *substream,
32 struct snd_pcm_hw_params *params)
33{
34 struct snd_soc_pcm_runtime *rtd = substream->private_data;
35 struct snd_soc_dai *codec_dai = rtd->codec_dai;
36 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
37 unsigned int rate = params_rate(params);
38 u32 dai_format, mclk;
39 int ret;
40
41 /* sgtl5000 does not support 512*rate when in 96000 fs */
42 switch (rate) {
43 case 96000:
44 mclk = 256 * rate;
45 break;
46 default:
47 mclk = 512 * rate;
48 break;
49 }
50
51 /* Sgtl5000 sysclk should be >= 8MHz and <= 27M */
52 if (mclk < 8000000 || mclk > 27000000)
53 return -EINVAL;
54
55 /* Set SGTL5000's SYSCLK (provided by SAIF MCLK) */
56 ret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, mclk, 0);
57 if (ret)
58 return ret;
59
60 /* The SAIF MCLK should be the same as SGTL5000_SYSCLK */
61 ret = snd_soc_dai_set_sysclk(cpu_dai, MXS_SAIF_MCLK, mclk, 0);
62 if (ret)
63 return ret;
64
65 /* set codec to slave mode */
66 dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
67 SND_SOC_DAIFMT_CBS_CFS;
68
69 /* set codec DAI configuration */
70 ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
71 if (ret)
72 return ret;
73
74 /* set cpu DAI configuration */
75 ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);
76 if (ret)
77 return ret;
78
79 return 0;
80}
81
82static struct snd_soc_ops mxs_sgtl5000_hifi_ops = {
83 .hw_params = mxs_sgtl5000_hw_params,
84};
85
86static struct snd_soc_dai_link mxs_sgtl5000_dai[] = {
87 {
88 .name = "HiFi Tx",
89 .stream_name = "HiFi Playback",
90 .codec_dai_name = "sgtl5000",
91 .codec_name = "sgtl5000.0-000a",
92 .cpu_dai_name = "mxs-saif.0",
93 .platform_name = "mxs-pcm-audio.0",
94 .ops = &mxs_sgtl5000_hifi_ops,
95 }, {
96 .name = "HiFi Rx",
97 .stream_name = "HiFi Capture",
98 .codec_dai_name = "sgtl5000",
99 .codec_name = "sgtl5000.0-000a",
100 .cpu_dai_name = "mxs-saif.1",
101 .platform_name = "mxs-pcm-audio.1",
102 .ops = &mxs_sgtl5000_hifi_ops,
103 },
104};
105
106static struct snd_soc_card mxs_sgtl5000 = {
107 .name = "mxs_sgtl5000",
108 .dai_link = mxs_sgtl5000_dai,
109 .num_links = ARRAY_SIZE(mxs_sgtl5000_dai),
110};
111
112static int __devinit mxs_sgtl5000_probe(struct platform_device *pdev)
113{
114 struct snd_soc_card *card = &mxs_sgtl5000;
115 int ret;
116
117 /*
118 * Set an init clock(11.28Mhz) for sgtl5000 initialization(i2c r/w).
119 * The Sgtl5000 sysclk is derived from saif0 mclk and it's range
120 * should be >= 8MHz and <= 27M.
121 */
122 ret = mxs_saif_get_mclk(0, 44100 * 256, 44100);
123 if (ret)
124 return ret;
125
126 card->dev = &pdev->dev;
127 platform_set_drvdata(pdev, card);
128
129 ret = snd_soc_register_card(card);
130 if (ret) {
131 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
132 ret);
133 return ret;
134 }
135
136 return 0;
137}
138
139static int __devexit mxs_sgtl5000_remove(struct platform_device *pdev)
140{
141 struct snd_soc_card *card = platform_get_drvdata(pdev);
142
143 mxs_saif_put_mclk(0);
144
145 snd_soc_unregister_card(card);
146
147 return 0;
148}
149
150static struct platform_driver mxs_sgtl5000_audio_driver = {
151 .driver = {
152 .name = "mxs-sgtl5000",
153 .owner = THIS_MODULE,
154 },
155 .probe = mxs_sgtl5000_probe,
156 .remove = __devexit_p(mxs_sgtl5000_remove),
157};
158
159static int __init mxs_sgtl5000_init(void)
160{
161 return platform_driver_register(&mxs_sgtl5000_audio_driver);
162}
163module_init(mxs_sgtl5000_init);
164
165static void __exit mxs_sgtl5000_exit(void)
166{
167 platform_driver_unregister(&mxs_sgtl5000_audio_driver);
168}
169module_exit(mxs_sgtl5000_exit);
170
171MODULE_AUTHOR("Freescale Semiconductor, Inc.");
172MODULE_DESCRIPTION("MXS ALSA SoC Machine driver");
173MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-10 03:54:54 -0500