1 files changed, 807 insertions, 0 deletions

diff --git a/samples/vfio-mdev/mdpy.c b/samples/vfio-mdev/mdpy.c
new file mode 100644
index 000000000000..96e7969c473a
--- /dev/null
+++ b/samples/vfio-mdev/mdpy.c
@@ -0,0 +1,807 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediated virtual PCI display host device driver
+ *
+ * See mdpy-defs.h for device specs
+ *
+ *   (c) Gerd Hoffmann <kraxel@redhat.com>
+ *
+ * based on mtty driver which is:
+ *   Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *       Author: Neo Jia <cjia@nvidia.com>
+ *               Kirti Wankhede <kwankhede@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/cdev.h>
+#include <linux/vfio.h>
+#include <linux/iommu.h>
+#include <linux/sysfs.h>
+#include <linux/mdev.h>
+#include <linux/pci.h>
+#include <drm/drm_fourcc.h>
+#include "mdpy-defs.h"
+
+#define MDPY_NAME               "mdpy"
+#define MDPY_CLASS_NAME         "mdpy"
+
+#define MDPY_CONFIG_SPACE_SIZE  0xff
+#define MDPY_MEMORY_BAR_OFFSET  PAGE_SIZE
+#define MDPY_DISPLAY_REGION     16
+
+#define STORE_LE16(addr, val)   (*(u16 *)addr = val)
+#define STORE_LE32(addr, val)   (*(u32 *)addr = val)
+
+
+MODULE_LICENSE("GPL v2");
+
+static int max_devices = 4;
+module_param_named(count, max_devices, int, 0444);
+MODULE_PARM_DESC(count, "number of " MDPY_NAME " devices");
+
+
+#define MDPY_TYPE_1 "vga"
+#define MDPY_TYPE_2 "xga"
+#define MDPY_TYPE_3 "hd"
+
+static const struct mdpy_type {
+        const char *name;
+        u32 format;
+        u32 bytepp;
+        u32 width;
+        u32 height;
+} mdpy_types[] = {
+        {
+                .name   = MDPY_CLASS_NAME "-" MDPY_TYPE_1,
+                .format = DRM_FORMAT_XRGB8888,
+                .bytepp = 4,
+                .width  = 640,
+                .height = 480,
+        }, {
+                .name   = MDPY_CLASS_NAME "-" MDPY_TYPE_2,
+                .format = DRM_FORMAT_XRGB8888,
+                .bytepp = 4,
+                .width  = 1024,
+                .height = 768,
+        }, {
+                .name   = MDPY_CLASS_NAME "-" MDPY_TYPE_3,
+                .format = DRM_FORMAT_XRGB8888,
+                .bytepp = 4,
+                .width  = 1920,
+                .height = 1080,
+        },
+};
+
+static dev_t            mdpy_devt;
+static struct class     *mdpy_class;
+static struct cdev      mdpy_cdev;
+static struct device    mdpy_dev;
+static u32              mdpy_count;
+
+/* State of each mdev device */
+struct mdev_state {
+        u8 *vconfig;
+        u32 bar_mask;
+        struct mutex ops_lock;
+        struct mdev_device *mdev;
+        struct vfio_device_info dev_info;
+
+        const struct mdpy_type *type;
+        u32 memsize;
+        void *memblk;
+};
+
+static const struct mdpy_type *mdpy_find_type(struct kobject *kobj)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(mdpy_types); i++)
+                if (strcmp(mdpy_types[i].name, kobj->name) == 0)
+                        return mdpy_types + i;
+        return NULL;
+}
+
+static void mdpy_create_config_space(struct mdev_state *mdev_state)
+{
+        STORE_LE16((u16 *) &mdev_state->vconfig[PCI_VENDOR_ID],
+                   MDPY_PCI_VENDOR_ID);
+        STORE_LE16((u16 *) &mdev_state->vconfig[PCI_DEVICE_ID],
+                   MDPY_PCI_DEVICE_ID);
+        STORE_LE16((u16 *) &mdev_state->vconfig[PCI_SUBSYSTEM_VENDOR_ID],
+                   MDPY_PCI_SUBVENDOR_ID);
+        STORE_LE16((u16 *) &mdev_state->vconfig[PCI_SUBSYSTEM_ID],
+                   MDPY_PCI_SUBDEVICE_ID);
+
+        STORE_LE16((u16 *) &mdev_state->vconfig[PCI_COMMAND],
+                   PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+        STORE_LE16((u16 *) &mdev_state->vconfig[PCI_STATUS],
+                   PCI_STATUS_CAP_LIST);
+        STORE_LE16((u16 *) &mdev_state->vconfig[PCI_CLASS_DEVICE],
+                   PCI_CLASS_DISPLAY_OTHER);
+        mdev_state->vconfig[PCI_CLASS_REVISION] =  0x01;
+
+        STORE_LE32((u32 *) &mdev_state->vconfig[PCI_BASE_ADDRESS_0],
+                   PCI_BASE_ADDRESS_SPACE_MEMORY |
+                   PCI_BASE_ADDRESS_MEM_TYPE_32  |
+                   PCI_BASE_ADDRESS_MEM_PREFETCH);
+        mdev_state->bar_mask = ~(mdev_state->memsize) + 1;
+
+        /* vendor specific capability for the config registers */
+        mdev_state->vconfig[PCI_CAPABILITY_LIST]       = MDPY_VENDORCAP_OFFSET;
+        mdev_state->vconfig[MDPY_VENDORCAP_OFFSET + 0] = 0x09; /* vendor cap */
+        mdev_state->vconfig[MDPY_VENDORCAP_OFFSET + 1] = 0x00; /* next ptr */
+        mdev_state->vconfig[MDPY_VENDORCAP_OFFSET + 2] = MDPY_VENDORCAP_SIZE;
+        STORE_LE32((u32 *) &mdev_state->vconfig[MDPY_FORMAT_OFFSET],
+                   mdev_state->type->format);
+        STORE_LE32((u32 *) &mdev_state->vconfig[MDPY_WIDTH_OFFSET],
+                   mdev_state->type->width);
+        STORE_LE32((u32 *) &mdev_state->vconfig[MDPY_HEIGHT_OFFSET],
+                   mdev_state->type->height);
+}
+
+static void handle_pci_cfg_write(struct mdev_state *mdev_state, u16 offset,
+                                 char *buf, u32 count)
+{
+        struct device *dev = mdev_dev(mdev_state->mdev);
+        u32 cfg_addr;
+
+        switch (offset) {
+        case PCI_BASE_ADDRESS_0:
+                cfg_addr = *(u32 *)buf;
+
+                if (cfg_addr == 0xffffffff) {
+                        cfg_addr = (cfg_addr & mdev_state->bar_mask);
+                } else {
+                        cfg_addr &= PCI_BASE_ADDRESS_MEM_MASK;
+                        if (cfg_addr)
+                                dev_info(dev, "BAR0 @ 0x%x\n", cfg_addr);
+                }
+
+                cfg_addr |= (mdev_state->vconfig[offset] &
+                             ~PCI_BASE_ADDRESS_MEM_MASK);
+                STORE_LE32(&mdev_state->vconfig[offset], cfg_addr);
+                break;
+        }
+}
+
+static ssize_t mdev_access(struct mdev_device *mdev, char *buf, size_t count,
+                           loff_t pos, bool is_write)
+{
+        struct mdev_state *mdev_state = mdev_get_drvdata(mdev);
+        struct device *dev = mdev_dev(mdev);
+        int ret = 0;
+
+        mutex_lock(&mdev_state->ops_lock);
+
+        if (pos < MDPY_CONFIG_SPACE_SIZE) {
+                if (is_write)
+                        handle_pci_cfg_write(mdev_state, pos, buf, count);
+                else
+                        memcpy(buf, (mdev_state->vconfig + pos), count);
+
+        } else if ((pos >= MDPY_MEMORY_BAR_OFFSET) &&
+                   (pos + count <=
+                    MDPY_MEMORY_BAR_OFFSET + mdev_state->memsize)) {
+                pos -= MDPY_MEMORY_BAR_OFFSET;
+                if (is_write)
+                        memcpy(mdev_state->memblk, buf, count);
+                else
+                        memcpy(buf, mdev_state->memblk, count);
+
+        } else {
+                dev_info(dev, "%s: %s @0x%llx (unhandled)\n",
+                         __func__, is_write ? "WR" : "RD", pos);
+                ret = -1;
+                goto accessfailed;
+        }
+
+        ret = count;
+
+
+accessfailed:
+        mutex_unlock(&mdev_state->ops_lock);
+
+        return ret;
+}
+
+static int mdpy_reset(struct mdev_device *mdev)
+{
+        struct mdev_state *mdev_state = mdev_get_drvdata(mdev);