diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/drm/i915_pciids.h | 1 | ||||
-rw-r--r-- | include/uapi/drm/i915_drm.h | 22 |
2 files changed, 23 insertions, 0 deletions
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index fbf5cfc9b352..fd965ffbb92e 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h | |||
@@ -386,6 +386,7 @@ | |||
386 | INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ | 386 | INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ |
387 | INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ | 387 | INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ |
388 | INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \ | 388 | INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \ |
389 | INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \ | ||
389 | INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ | 390 | INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ |
390 | 391 | ||
391 | /* CFL H */ | 392 | /* CFL H */ |
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 7f5634ce8e88..a4446f452040 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h | |||
@@ -529,6 +529,28 @@ typedef struct drm_i915_irq_wait { | |||
529 | */ | 529 | */ |
530 | #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 | 530 | #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 |
531 | 531 | ||
532 | /* | ||
533 | * Once upon a time we supposed that writes through the GGTT would be | ||
534 | * immediately in physical memory (once flushed out of the CPU path). However, | ||
535 | * on a few different processors and chipsets, this is not necessarily the case | ||
536 | * as the writes appear to be buffered internally. Thus a read of the backing | ||
537 | * storage (physical memory) via a different path (with different physical tags | ||
538 | * to the indirect write via the GGTT) will see stale values from before | ||
539 | * the GGTT write. Inside the kernel, we can for the most part keep track of | ||
540 | * the different read/write domains in use (e.g. set-domain), but the assumption | ||
541 | * of coherency is baked into the ABI, hence reporting its true state in this | ||
542 | * parameter. | ||
543 | * | ||
544 | * Reports true when writes via mmap_gtt are immediately visible following an | ||
545 | * lfence to flush the WCB. | ||
546 | * | ||
547 | * Reports false when writes via mmap_gtt are indeterminately delayed in an in | ||
548 | * internal buffer and are _not_ immediately visible to third parties accessing | ||
549 | * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC | ||
550 | * communications channel when reporting false is strongly disadvised. | ||
551 | */ | ||
552 | #define I915_PARAM_MMAP_GTT_COHERENT 52 | ||
553 | |||
532 | typedef struct drm_i915_getparam { | 554 | typedef struct drm_i915_getparam { |
533 | __s32 param; | 555 | __s32 param; |
534 | /* | 556 | /* |