10 files changed, 314 insertions, 11 deletions

diff --git a/include/dt-bindings/genpd/k2g.h b/include/dt-bindings/genpd/k2g.h
new file mode 100644
index 000000000000..1f31f17e19eb
--- /dev/null
+++ b/include/dt-bindings/genpd/k2g.h
@@ -0,0 +1,90 @@
+/*
+ * TI K2G SoC Device definitions
+ *
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_GENPD_K2G_H
+#define _DT_BINDINGS_GENPD_K2G_H
+
+/* Documented in http://processors.wiki.ti.com/index.php/TISCI */
+
+#define K2G_DEV_PMMC0                   0x0000
+#define K2G_DEV_MLB0                    0x0001
+#define K2G_DEV_DSS0                    0x0002
+#define K2G_DEV_MCBSP0                  0x0003
+#define K2G_DEV_MCASP0                  0x0004
+#define K2G_DEV_MCASP1                  0x0005
+#define K2G_DEV_MCASP2                  0x0006
+#define K2G_DEV_DCAN0                   0x0008
+#define K2G_DEV_DCAN1                   0x0009
+#define K2G_DEV_EMIF0                   0x000a
+#define K2G_DEV_MMCHS0                  0x000b
+#define K2G_DEV_MMCHS1                  0x000c
+#define K2G_DEV_GPMC0                   0x000d
+#define K2G_DEV_ELM0                    0x000e
+#define K2G_DEV_SPI0                    0x0010
+#define K2G_DEV_SPI1                    0x0011
+#define K2G_DEV_SPI2                    0x0012
+#define K2G_DEV_SPI3                    0x0013
+#define K2G_DEV_ICSS0                   0x0014
+#define K2G_DEV_ICSS1                   0x0015
+#define K2G_DEV_USB0                    0x0016
+#define K2G_DEV_USB1                    0x0017
+#define K2G_DEV_NSS0                    0x0018
+#define K2G_DEV_PCIE0                   0x0019
+#define K2G_DEV_GPIO0                   0x001b
+#define K2G_DEV_GPIO1                   0x001c
+#define K2G_DEV_TIMER64_0               0x001d
+#define K2G_DEV_TIMER64_1               0x001e
+#define K2G_DEV_TIMER64_2               0x001f
+#define K2G_DEV_TIMER64_3               0x0020
+#define K2G_DEV_TIMER64_4               0x0021
+#define K2G_DEV_TIMER64_5               0x0022
+#define K2G_DEV_TIMER64_6               0x0023
+#define K2G_DEV_MSGMGR0                 0x0025
+#define K2G_DEV_BOOTCFG0                0x0026
+#define K2G_DEV_ARM_BOOTROM0            0x0027
+#define K2G_DEV_DSP_BOOTROM0            0x0029
+#define K2G_DEV_DEBUGSS0                0x002b
+#define K2G_DEV_UART0                   0x002c
+#define K2G_DEV_UART1                   0x002d
+#define K2G_DEV_UART2                   0x002e
+#define K2G_DEV_EHRPWM0                 0x002f
+#define K2G_DEV_EHRPWM1                 0x0030
+#define K2G_DEV_EHRPWM2                 0x0031
+#define K2G_DEV_EHRPWM3                 0x0032
+#define K2G_DEV_EHRPWM4                 0x0033
+#define K2G_DEV_EHRPWM5                 0x0034
+#define K2G_DEV_EQEP0                   0x0035
+#define K2G_DEV_EQEP1                   0x0036
+#define K2G_DEV_EQEP2                   0x0037
+#define K2G_DEV_ECAP0                   0x0038
+#define K2G_DEV_ECAP1                   0x0039
+#define K2G_DEV_I2C0                    0x003a
+#define K2G_DEV_I2C1                    0x003b
+#define K2G_DEV_I2C2                    0x003c
+#define K2G_DEV_EDMA0                   0x003f
+#define K2G_DEV_SEMAPHORE0              0x0040
+#define K2G_DEV_INTC0                   0x0041
+#define K2G_DEV_GIC0                    0x0042
+#define K2G_DEV_QSPI0                   0x0043
+#define K2G_DEV_ARM_64B_COUNTER0        0x0044
+#define K2G_DEV_TETRIS0                 0x0045
+#define K2G_DEV_CGEM0                   0x0046
+#define K2G_DEV_MSMC0                   0x0047
+#define K2G_DEV_CBASS0                  0x0049
+#define K2G_DEV_BOARD0                  0x004c
+#define K2G_DEV_EDMA1                   0x004f
+
+#endif
diff --git a/include/dt-bindings/power/imx7-power.h b/include/dt-bindings/power/imx7-power.h
new file mode 100644
index 000000000000..3a181e410517
--- /dev/null
+++ b/include/dt-bindings/power/imx7-power.h
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 2017 Impinj
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_IMX7_POWER_H__
+#define __DT_BINDINGS_IMX7_POWER_H__
+
+#define IMX7_POWER_DOMAIN_MIPI_PHY              0
+#define IMX7_POWER_DOMAIN_PCIE_PHY              1
+#define IMX7_POWER_DOMAIN_USB_HSIC_PHY          2
+
+#endif
diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h
index ee2e26ba605e..ad679eeda137 100644
--- a/include/dt-bindings/power/r8a7795-sysc.h
+++ b/include/dt-bindings/power/r8a7795-sysc.h
@@ -33,7 +33,7 @@
 #define R8A7795_PD_CA53_SCU             21
 #define R8A7795_PD_3DG_E                22
 #define R8A7795_PD_A3IR                 24
-#define R8A7795_PD_A2VC0                25
+#define R8A7795_PD_A2VC0                25      /* ES1.x only */
 #define R8A7795_PD_A2VC1                26
 
 /* Always-on power area */
diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10sr.h b/include/dt-bindings/reset/altr,rst-mgr-a10sr.h
new file mode 100644
index 000000000000..9855925e5256
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10sr.h
@@ -0,0 +1,33 @@
+/*
+ *  Copyright Intel Corporation (C) 2017. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from altr,rst-mgr-a10.h
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
+
+/* Peripheral PHY resets */
+#define A10SR_RESET_ENET_HPS    0
+#define A10SR_RESET_PCIE        1
+#define A10SR_RESET_FILE        2
+#define A10SR_RESET_BQSPI       3
+#define A10SR_RESET_USB         4
+
+#define A10SR_RESET_NUM         5
+
+#endif
diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h
new file mode 100644
index 000000000000..63948170c7b2
--- /dev/null
+++ b/include/dt-bindings/reset/imx7-reset.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2017 Impinj, Inc.
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_BINDING_RESET_IMX7_H
+#define DT_BINDING_RESET_IMX7_H
+
+#define IMX7_RESET_A7_CORE_POR_RESET0   0
+#define IMX7_RESET_A7_CORE_POR_RESET1   1
+#define IMX7_RESET_A7_CORE_RESET0       2
+#define IMX7_RESET_A7_CORE_RESET1       3
+#define IMX7_RESET_A7_DBG_RESET0        4
+#define IMX7_RESET_A7_DBG_RESET1        5
+#define IMX7_RESET_A7_ETM_RESET0        6
+#define IMX7_RESET_A7_ETM_RESET1        7
+#define IMX7_RESET_A7_SOC_DBG_RESET     8
+#define IMX7_RESET_A7_L2RESET           9
+#define IMX7_RESET_SW_M4C_RST           10
+#define IMX7_RESET_SW_M4P_RST           11
+#define IMX7_RESET_EIM_RST              12
+#define IMX7_RESET_HSICPHY_PORT_RST     13
+#define IMX7_RESET_USBPHY1_POR          14
+#define IMX7_RESET_USBPHY1_PORT_RST     15
+#define IMX7_RESET_USBPHY2_POR          16
+#define IMX7_RESET_USBPHY2_PORT_RST     17
+#define IMX7_RESET_MIPI_PHY_MRST        18
+#define IMX7_RESET_MIPI_PHY_SRST        19
+
+/*
+ * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
+ * and PCIEPHY_G_RST
+ */
+#define IMX7_RESET_PCIEPHY              20
+#define IMX7_RESET_PCIEPHY_PERST        21
+
+/*
+ * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
+ * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
+ * of as one
+ */
+#define IMX7_RESET_PCIE_CTRL_APPS_EN    22
+#define IMX7_RESET_DDRC_PRST            23
+#define IMX7_RESET_DDRC_CORE_RST        24
+
+#define IMX7_RESET_NUM                  25
+
+#endif
+
diff --git a/include/linux/firmware/meson/meson_sm.h b/include/linux/firmware/meson/meson_sm.h
index 8e953c6f394a..37a5eaea69dd 100644
--- a/include/linux/firmware/meson/meson_sm.h
+++ b/include/linux/firmware/meson/meson_sm.h
@@ -25,7 +25,7 @@ int meson_sm_call(unsigned int cmd_index, u32 *ret, u32 arg0, u32 arg1,
                   u32 arg2, u32 arg3, u32 arg4);
 int meson_sm_call_write(void *buffer, unsigned int b_size, unsigned int cmd_index,
                         u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
-int meson_sm_call_read(void *buffer, unsigned int cmd_index, u32 arg0, u32 arg1,
-                       u32 arg2, u32 arg3, u32 arg4);
+int meson_sm_call_read(void *buffer, unsigned int bsize, unsigned int cmd_index,
+                       u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
 
 #endif /* _MESON_SM_FW_H_ */
diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
index 9b6abe632587..b7803a251044 100644
--- a/include/linux/pm_domain.h
+++ b/include/linux/pm_domain.h
@@ -118,6 +118,7 @@ struct generic_pm_domain_data {
         struct pm_domain_data base;
         struct gpd_timing_data td;
         struct notifier_block nb;
+        void *data;
 };
 
 #ifdef CONFIG_PM_GENERIC_DOMAINS
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index d32f6f1a5225..e5380471c2cd 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -40,6 +40,9 @@ extern int qcom_scm_pas_shutdown(u32 peripheral);
 extern void qcom_scm_cpu_power_down(u32 flags);
 extern u32 qcom_scm_get_version(void);
 extern int qcom_scm_set_remote_state(u32 state, u32 id);
+extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
+extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
+extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
 #else
 static inline
 int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
@@ -67,5 +70,8 @@ static inline void qcom_scm_cpu_power_down(u32 flags) {}
 static inline u32 qcom_scm_get_version(void) { return 0; }
 static inline u32
 qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
+static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
+static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
+static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
 #endif
 #endif
diff --git a/include/soc/tegra/flowctrl.h b/include/soc/tegra/flowctrl.h
new file mode 100644
index 000000000000..8f86aea4024b
--- /dev/null
+++ b/include/soc/tegra/flowctrl.h
@@ -0,0 +1,82 @@
+/*
+ * Functions and macros to control the flowcontroller
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_TEGRA_FLOWCTRL_H__
+#define __SOC_TEGRA_FLOWCTRL_H__
+
+#define FLOW_CTRL_HALT_CPU0_EVENTS      0x0
+#define FLOW_CTRL_WAITEVENT             (2 << 29)
+#define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
+#define FLOW_CTRL_JTAG_RESUME           (1 << 28)
+#define FLOW_CTRL_SCLK_RESUME           (1 << 27)
+#define FLOW_CTRL_HALT_CPU_IRQ          (1 << 10)
+#define FLOW_CTRL_HALT_CPU_FIQ          (1 << 8)
+#define FLOW_CTRL_HALT_LIC_IRQ          (1 << 11)
+#define FLOW_CTRL_HALT_LIC_FIQ          (1 << 10)
+#define FLOW_CTRL_HALT_GIC_IRQ          (1 << 9)
+#define FLOW_CTRL_HALT_GIC_FIQ          (1 << 8)
+#define FLOW_CTRL_CPU0_CSR              0x8
+#define FLOW_CTRL_CSR_INTR_FLAG         (1 << 15)
+#define FLOW_CTRL_CSR_EVENT_FLAG        (1 << 14)
+#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL  (1 << 13)
+#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU   (1 << 12)
+#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
+                FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
+                FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
+#define FLOW_CTRL_CSR_ENABLE            (1 << 0)
+#define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
+#define FLOW_CTRL_CPU1_CSR              0x18
+
+#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0          (1 << 4)
+#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP        (3 << 4)
+#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP        0
+
+#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0          (1 << 8)
+#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP        (0xF << 4)
+#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP        (0xF << 8)
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
+u32 flowctrl_read_cpu_csr(unsigned int cpuid);
+void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
+void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
+
+void flowctrl_cpu_suspend_enter(unsigned int cpuid);
+void flowctrl_cpu_suspend_exit(unsigned int cpuid);
+#else
+static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
+{
+        return 0;
+}
+
+static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
+{
+}
+
+static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
+
+static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
+{
+}
+
+static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
+{
+}
+#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
+#endif /* __ASSEMBLY */
+#endif /* __SOC_TEGRA_FLOWCTRL_H__ */
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index 2f271d1b9cea..1c3982bc558f 100644
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -26,12 +26,6 @@
 struct clk;
 struct reset_control;
 
-#ifdef CONFIG_PM_SLEEP
-enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
-void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
-void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
-#endif /* CONFIG_PM_SLEEP */
-
 #ifdef CONFIG_SMP
 bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
 int tegra_pmc_cpu_power_on(unsigned int cpuid);
@@ -144,7 +138,7 @@ enum tegra_io_pad_voltage {
         TEGRA_IO_PAD_3300000UV,
 };
 
-#ifdef CONFIG_ARCH_TEGRA
+#ifdef CONFIG_SOC_TEGRA_PMC
 int tegra_powergate_is_powered(unsigned int id);
 int tegra_powergate_power_on(unsigned int id);
 int tegra_powergate_power_off(unsigned int id);
@@ -163,6 +157,11 @@ int tegra_io_pad_get_voltage(enum tegra_io_pad id);
 /* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
 int tegra_io_rail_power_on(unsigned int id);
 int tegra_io_rail_power_off(unsigned int id);
+
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
+void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
+
 #else
 static inline int tegra_powergate_is_powered(unsigned int id)
 {
@@ -221,6 +220,20 @@ static inline int tegra_io_rail_power_off(unsigned int id)
 {
         return -ENOSYS;
 }
-#endif /* CONFIG_ARCH_TEGRA */
+
+static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
+{
+        return TEGRA_SUSPEND_NONE;
+}
+
+static inline void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
+{
+}
+
+static inline void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
+{
+}
+
+#endif /* CONFIG_SOC_TEGRA_PMC */
 
 #endif /* __SOC_TEGRA_PMC_H__ */