7 files changed, 217 insertions, 69 deletions

diff --git a/include/uapi/linux/cm4000_cs.h b/include/uapi/linux/cm4000_cs.h
index bc51f77db918..1217f751a1bc 100644
--- a/include/uapi/linux/cm4000_cs.h
+++ b/include/uapi/linux/cm4000_cs.h
@@ -2,6 +2,7 @@
 #define _UAPI_CM4000_H_
 
 #include <linux/types.h>
+#include <linux/ioctl.h>
 
 #define MAX_ATR                 33
 
diff --git a/include/uapi/linux/ip.h b/include/uapi/linux/ip.h
index 6cf06bfd841b..2fee45bdec0a 100644
--- a/include/uapi/linux/ip.h
+++ b/include/uapi/linux/ip.h
@@ -133,4 +133,38 @@ struct ip_beet_phdr {
         __u8 reserved;
 };
 
+/* index values for the variables in ipv4_devconf */
+enum
+{
+        IPV4_DEVCONF_FORWARDING=1,
+        IPV4_DEVCONF_MC_FORWARDING,
+        IPV4_DEVCONF_PROXY_ARP,
+        IPV4_DEVCONF_ACCEPT_REDIRECTS,
+        IPV4_DEVCONF_SECURE_REDIRECTS,
+        IPV4_DEVCONF_SEND_REDIRECTS,
+        IPV4_DEVCONF_SHARED_MEDIA,
+        IPV4_DEVCONF_RP_FILTER,
+        IPV4_DEVCONF_ACCEPT_SOURCE_ROUTE,
+        IPV4_DEVCONF_BOOTP_RELAY,
+        IPV4_DEVCONF_LOG_MARTIANS,
+        IPV4_DEVCONF_TAG,
+        IPV4_DEVCONF_ARPFILTER,
+        IPV4_DEVCONF_MEDIUM_ID,
+        IPV4_DEVCONF_NOXFRM,
+        IPV4_DEVCONF_NOPOLICY,
+        IPV4_DEVCONF_FORCE_IGMP_VERSION,
+        IPV4_DEVCONF_ARP_ANNOUNCE,
+        IPV4_DEVCONF_ARP_IGNORE,
+        IPV4_DEVCONF_PROMOTE_SECONDARIES,
+        IPV4_DEVCONF_ARP_ACCEPT,
+        IPV4_DEVCONF_ARP_NOTIFY,
+        IPV4_DEVCONF_ACCEPT_LOCAL,
+        IPV4_DEVCONF_SRC_VMARK,
+        IPV4_DEVCONF_PROXY_ARP_PVLAN,
+        IPV4_DEVCONF_ROUTE_LOCALNET,
+        __IPV4_DEVCONF_MAX
+};
+
+#define IPV4_DEVCONF_MAX (__IPV4_DEVCONF_MAX - 1)
+
 #endif /* _UAPI_LINUX_IP_H */
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index c3cc01d474b0..baa7852468ef 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -421,24 +421,24 @@
 #define  PCI_EXP_TYPE_ROOT_PORT 0x4     /* Root Port */
 #define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
-#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
-#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIE Bridge */
+#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCIe to PCI/PCI-X Bridge */
+#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIe Bridge */
 #define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
 #define  PCI_EXP_TYPE_RC_EC     0xa     /* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP          4       /* Device capabilities */
-#define  PCI_EXP_DEVCAP_PAYLOAD 0x07    /* Max_Payload_Size */
-#define  PCI_EXP_DEVCAP_PHANTOM 0x18    /* Phantom functions */
-#define  PCI_EXP_DEVCAP_EXT_TAG 0x20    /* Extended tags */
-#define  PCI_EXP_DEVCAP_L0S     0x1c0   /* L0s Acceptable Latency */
-#define  PCI_EXP_DEVCAP_L1      0xe00   /* L1 Acceptable Latency */
-#define  PCI_EXP_DEVCAP_ATN_BUT 0x1000  /* Attention Button Present */
-#define  PCI_EXP_DEVCAP_ATN_IND 0x2000  /* Attention Indicator Present */
-#define  PCI_EXP_DEVCAP_PWR_IND 0x4000  /* Power Indicator Present */
-#define  PCI_EXP_DEVCAP_RBER    0x8000  /* Role-Based Error Reporting */
-#define  PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
-#define  PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
+#define  PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
+#define  PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
+#define  PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */
+#define  PCI_EXP_DEVCAP_L0S     0x000001c0 /* L0s Acceptable Latency */
+#define  PCI_EXP_DEVCAP_L1      0x00000e00 /* L1 Acceptable Latency */
+#define  PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */
+#define  PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */
+#define  PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */
+#define  PCI_EXP_DEVCAP_RBER    0x00008000 /* Role-Based Error Reporting */
+#define  PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */
+#define  PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */
 #define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL          8       /* Device Control */
 #define  PCI_EXP_DEVCTL_CERE    0x0001  /* Correctable Error Reporting En. */
@@ -454,16 +454,16 @@
 #define  PCI_EXP_DEVCTL_READRQ  0x7000  /* Max_Read_Request_Size */
 #define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 #define PCI_EXP_DEVSTA          10      /* Device Status */
-#define  PCI_EXP_DEVSTA_CED     0x01    /* Correctable Error Detected */
-#define  PCI_EXP_DEVSTA_NFED    0x02    /* Non-Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_FED     0x04    /* Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_URD     0x08    /* Unsupported Request Detected */
-#define  PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
-#define  PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
+#define  PCI_EXP_DEVSTA_CED     0x0001  /* Correctable Error Detected */
+#define  PCI_EXP_DEVSTA_NFED    0x0002  /* Non-Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_FED     0x0004  /* Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_URD     0x0008  /* Unsupported Request Detected */
+#define  PCI_EXP_DEVSTA_AUXPD   0x0010  /* AUX Power Detected */
+#define  PCI_EXP_DEVSTA_TRPND   0x0020  /* Transactions Pending */
 #define PCI_EXP_LNKCAP          12      /* Link Capabilities */
 #define  PCI_EXP_LNKCAP_SLS     0x0000000f /* Supported Link Speeds */
-#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x1   /* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */
-#define  PCI_EXP_LNKCAP_SLS_5_0GB 0x2   /* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */
+#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
+#define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
 #define  PCI_EXP_LNKCAP_MLW     0x000003f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */
 #define  PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
@@ -475,21 +475,21 @@
 #define  PCI_EXP_LNKCAP_PN      0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL          16      /* Link Control */
 #define  PCI_EXP_LNKCTL_ASPMC   0x0003  /* ASPM Control */
-#define  PCI_EXP_LNKCTL_ASPM_L0S  0x01  /* L0s Enable */
-#define  PCI_EXP_LNKCTL_ASPM_L1   0x02  /* L1 Enable */
+#define  PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */
+#define  PCI_EXP_LNKCTL_ASPM_L1  0x0002 /* L1 Enable */
 #define  PCI_EXP_LNKCTL_RCB     0x0008  /* Read Completion Boundary */
 #define  PCI_EXP_LNKCTL_LD      0x0010  /* Link Disable */
 #define  PCI_EXP_LNKCTL_RL      0x0020  /* Retrain Link */
 #define  PCI_EXP_LNKCTL_CCC     0x0040  /* Common Clock Configuration */
 #define  PCI_EXP_LNKCTL_ES      0x0080  /* Extended Synch */
-#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
+#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
 #define  PCI_EXP_LNKCTL_HAWD    0x0200  /* Hardware Autonomous Width Disable */
 #define  PCI_EXP_LNKCTL_LBMIE   0x0400  /* Link Bandwidth Management Interrupt Enable */
 #define  PCI_EXP_LNKCTL_LABIE   0x0800  /* Lnk Autonomous Bandwidth Interrupt Enable */
 #define PCI_EXP_LNKSTA          18      /* Link Status */
 #define  PCI_EXP_LNKSTA_CLS     0x000f  /* Current Link Speed */
-#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x01  /* Current Link Speed 2.5GT/s */
-#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x02  /* Current Link Speed 5.0GT/s */
+#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
+#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
 #define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Nogotiated Link Width */
 #define  PCI_EXP_LNKSTA_NLW_SHIFT 4     /* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_LT      0x0800  /* Link Training */
@@ -534,44 +534,49 @@
 #define  PCI_EXP_SLTSTA_EIS     0x0080  /* Electromechanical Interlock Status */
 #define  PCI_EXP_SLTSTA_DLLSC   0x0100  /* Data Link Layer State Changed */
 #define PCI_EXP_RTCTL           28      /* Root Control */
-#define  PCI_EXP_RTCTL_SECEE    0x01    /* System Error on Correctable Error */
-#define  PCI_EXP_RTCTL_SENFEE   0x02    /* System Error on Non-Fatal Error */
-#define  PCI_EXP_RTCTL_SEFEE    0x04    /* System Error on Fatal Error */
-#define  PCI_EXP_RTCTL_PMEIE    0x08    /* PME Interrupt Enable */
-#define  PCI_EXP_RTCTL_CRSSVE   0x10    /* CRS Software Visibility Enable */
+#define  PCI_EXP_RTCTL_SECEE    0x0001  /* System Error on Correctable Error */
+#define  PCI_EXP_RTCTL_SENFEE   0x0002  /* System Error on Non-Fatal Error */
+#define  PCI_EXP_RTCTL_SEFEE    0x0004  /* System Error on Fatal Error */
+#define  PCI_EXP_RTCTL_PMEIE    0x0008  /* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_CRSSVE   0x0010  /* CRS Software Visibility Enable */
 #define PCI_EXP_RTCAP           30      /* Root Capabilities */
 #define PCI_EXP_RTSTA           32      /* Root Status */
-#define PCI_EXP_RTSTA_PME       0x10000 /* PME status */
-#define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */
+#define PCI_EXP_RTSTA_PME       0x00010000 /* PME status */
+#define PCI_EXP_RTSTA_PENDING   0x00020000 /* PME pending */
 /*
- * Note that the following PCI Express 'Capability Structure' registers
- * were introduced with 'Capability Version' 0x2 (v2).  These registers
- * do not exist on devices with Capability Version 1.  Use pci_pcie_cap2()
+ * The Device Capabilities 2, Device Status 2, Device Control 2,
+ * Link Capabilities 2, Link Status 2, Link Control 2,
+ * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers