2 files changed, 62 insertions, 10 deletions

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 3ecc07d0da77..c56988ac63f7 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -500,13 +500,14 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
  *
  * Clock with adjustable fractional divider affecting its output frequency.
  */
-
 struct clk_fractional_divider {
         struct clk_hw   hw;
         void __iomem    *reg;
         u8              mshift;
+        u8              mwidth;
         u32             mmask;
         u8              nshift;
+        u8              nwidth;
         u32             nmask;
         u8              flags;
         spinlock_t      *lock;
@@ -518,6 +519,41 @@ struct clk *clk_register_fractional_divider(struct device *dev,
                 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
                 u8 clk_divider_flags, spinlock_t *lock);
 
+/**
+ * struct clk_multiplier - adjustable multiplier clock
+ *
+ * @hw:         handle between common and hardware-specific interfaces
+ * @reg:        register containing the multiplier
+ * @shift:      shift to the multiplier bit field
+ * @width:      width of the multiplier bit field
+ * @lock:       register lock
+ *
+ * Clock with an adjustable multiplier affecting its output frequency.
+ * Implements .recalc_rate, .set_rate and .round_rate
+ *
+ * Flags:
+ * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
+ *      from the register, with 0 being a valid value effectively
+ *      zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
+ *      set, then a null multiplier will be considered as a bypass,
+ *      leaving the parent rate unmodified.
+ * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
+ *      rounded to the closest integer instead of the down one.
+ */
+struct clk_multiplier {
+        struct clk_hw   hw;
+        void __iomem    *reg;
+        u8              shift;
+        u8              width;
+        u8              flags;
+        spinlock_t      *lock;
+};
+
+#define CLK_MULTIPLIER_ZERO_BYPASS              BIT(0)
+#define CLK_MULTIPLIER_ROUND_CLOSEST    BIT(1)
+
+extern const struct clk_ops clk_multiplier_ops;
+
 /***
  * struct clk_composite - aggregate clock of mux, divider and gate clocks
  *
@@ -606,7 +642,7 @@ void clk_unregister(struct clk *clk);
 void devm_clk_unregister(struct device *dev, struct clk *clk);
 
 /* helper functions */
-const char *__clk_get_name(struct clk *clk);
+const char *__clk_get_name(const struct clk *clk);
 const char *clk_hw_get_name(const struct clk_hw *hw);
 struct clk_hw *__clk_get_hw(struct clk *clk);
 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
@@ -618,6 +654,7 @@ unsigned long clk_hw_get_rate(const struct clk_hw *hw);
 unsigned long __clk_get_flags(struct clk *clk);
 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
 bool clk_hw_is_prepared(const struct clk_hw *hw);
+bool clk_hw_is_enabled(const struct clk_hw *hw);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
 int __clk_mux_determine_rate(struct clk_hw *hw,
@@ -690,6 +727,15 @@ static inline struct clk *of_clk_src_onecell_get(
 {
         return ERR_PTR(-ENOENT);
 }
+static inline int of_clk_get_parent_count(struct device_node *np)
+{
+        return 0;
+}
+static inline int of_clk_parent_fill(struct device_node *np,
+                                     const char **parents, unsigned int size)
+{
+        return 0;
+}
 static inline const char *of_clk_get_parent_name(struct device_node *np,
                                                  int index)
 {
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 7669f7618f39..1e6932222e11 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -164,6 +164,7 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_MOSCSELS       (1 << 16)               /* Main Oscillator Selection [some SAM9] */
 #define         AT91_PMC_MOSCRCS        (1 << 17)               /* Main On-Chip RC [some SAM9] */
 #define         AT91_PMC_CFDEV          (1 << 18)               /* Clock Failure Detector Event [some SAM9] */
+#define         AT91_PMC_GCKRDY         (1 << 24)               /* Generated Clocks */
 #define AT91_PMC_IMR            0x6c                    /* Interrupt Mask Register */
 
 #define AT91_PMC_PLLICPR        0x80                    /* PLL Charge Pump Current Register */
@@ -182,13 +183,18 @@ extern void __iomem *at91_pmc_base;
 #define AT91_PMC_PCSR1          0x108                   /* Peripheral Clock Enable Register 1 */
 
 #define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9 and SAMA5] */
-#define         AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
-#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command (read=0, write=1) */
-#define         AT91_PMC_PCR_DIV(n)     ((n)  <<  16)           /* Divisor Value */
-#define                 AT91_PMC_PCR_DIV0       0x0                     /* Peripheral clock is MCK */
-#define                 AT91_PMC_PCR_DIV2       0x1                     /* Peripheral clock is MCK/2 */
-#define                 AT91_PMC_PCR_DIV4       0x2                     /* Peripheral clock is MCK/4 */
-#define                 AT91_PMC_PCR_DIV8       0x3                     /* Peripheral clock is MCK/8 */
-#define         AT91_PMC_PCR_EN         (0x1  <<  28)           /* Enable */
+#define         AT91_PMC_PCR_PID_MASK           0x3f
+#define         AT91_PMC_PCR_GCKCSS_OFFSET      8
+#define         AT91_PMC_PCR_GCKCSS_MASK        (0x7  << AT91_PMC_PCR_GCKCSS_OFFSET)
+#define         AT91_PMC_PCR_GCKCSS(n)          ((n)  << AT91_PMC_PCR_GCKCSS_OFFSET)    /* GCK Clock Source Selection */
+#define         AT91_PMC_PCR_CMD                (0x1  <<  12)                           /* Command (read=0, write=1) */
+#define         AT91_PMC_PCR_DIV_OFFSET         16
+#define         AT91_PMC_PCR_DIV_MASK           (0x3  << AT91_PMC_PCR_DIV_OFFSET)
+#define         AT91_PMC_PCR_DIV(n)             ((n)  << AT91_PMC_PCR_DIV_OFFSET)       /* Divisor Value */
+#define         AT91_PMC_PCR_GCKDIV_OFFSET      20
+#define         AT91_PMC_PCR_GCKDIV_MASK        (0xff  << AT91_PMC_PCR_GCKDIV_OFFSET)
+#define         AT91_PMC_PCR_GCKDIV(n)          ((n)  << AT91_PMC_PCR_GCKDIV_OFFSET)    /* Generated Clock Divisor Value */
+#define         AT91_PMC_PCR_EN                 (0x1  <<  28)                           /* Enable */
+#define         AT91_PMC_PCR_GCKEN              (0x1  <<  29)                           /* GCK Enable */
 
 #endif