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-rw-r--r--include/linux/mlx4/device.h17
1 files changed, 15 insertions, 2 deletions
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 39890cddc5fa..25c791e295fd 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -117,6 +117,14 @@ enum {
117 MLX4_STEERING_MODE_DEVICE_MANAGED 117 MLX4_STEERING_MODE_DEVICE_MANAGED
118}; 118};
119 119
120enum {
121 MLX4_STEERING_DMFS_A0_DEFAULT,
122 MLX4_STEERING_DMFS_A0_DYNAMIC,
123 MLX4_STEERING_DMFS_A0_STATIC,
124 MLX4_STEERING_DMFS_A0_DISABLE,
125 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
126};
127
120static inline const char *mlx4_steering_mode_str(int steering_mode) 128static inline const char *mlx4_steering_mode_str(int steering_mode)
121{ 129{
122 switch (steering_mode) { 130 switch (steering_mode) {
@@ -191,7 +199,8 @@ enum {
191 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 199 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
192 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 200 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
193 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 201 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
194 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18 202 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
203 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19
195}; 204};
196 205
197enum { 206enum {
@@ -225,7 +234,8 @@ enum {
225 234
226enum { 235enum {
227 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 236 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
228 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1 237 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
238 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
229}; 239};
230 240
231 241
@@ -482,6 +492,7 @@ struct mlx4_caps {
482 int reserved_mcgs; 492 int reserved_mcgs;
483 int num_qp_per_mgm; 493 int num_qp_per_mgm;
484 int steering_mode; 494 int steering_mode;
495 int dmfs_high_steer_mode;
485 int fs_log_max_ucast_qp_range_size; 496 int fs_log_max_ucast_qp_range_size;
486 int num_pds; 497 int num_pds;
487 int reserved_pds; 498 int reserved_pds;
@@ -522,6 +533,8 @@ struct mlx4_caps {
522 int tunnel_offload_mode; 533 int tunnel_offload_mode;
523 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 534 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
524 u8 alloc_res_qp_mask; 535 u8 alloc_res_qp_mask;
536 u32 dmfs_high_rate_qpn_base;
537 u32 dmfs_high_rate_qpn_range;
525}; 538};
526 539
527struct mlx4_buf_list { 540struct mlx4_buf_list {