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-rw-r--r--include/linux/fsl/guts.h125
-rw-r--r--include/linux/mfd/tmio.h5
-rw-r--r--include/linux/mmc/card.h14
-rw-r--r--include/linux/mmc/core.h16
-rw-r--r--include/linux/mmc/dw_mmc.h6
-rw-r--r--include/linux/mmc/host.h17
-rw-r--r--include/linux/mmc/mmc.h17
-rw-r--r--include/linux/mmc/slot-gpio.h1
-rw-r--r--include/linux/sys_soc.h9
9 files changed, 139 insertions, 71 deletions
diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h
index 649e9171a9b3..3efa3b861d44 100644
--- a/include/linux/fsl/guts.h
+++ b/include/linux/fsl/guts.h
@@ -29,83 +29,112 @@
29 * #ifdefs. 29 * #ifdefs.
30 */ 30 */
31struct ccsr_guts { 31struct ccsr_guts {
32 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ 32 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
33 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ 33 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
34 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ 34 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
35 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ 35 * Control Register
36 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ 36 */
37 __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */ 37 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
38 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
39 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
38 u8 res018[0x20 - 0x18]; 40 u8 res018[0x20 - 0x18];
39 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ 41 u32 porcir; /* 0x.0020 - POR Configuration Information
42 * Register
43 */
40 u8 res024[0x30 - 0x24]; 44 u8 res024[0x30 - 0x24];
41 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ 45 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
42 u8 res034[0x40 - 0x34]; 46 u8 res034[0x40 - 0x34];
43 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ 47 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
48 * Register
49 */
44 u8 res044[0x50 - 0x44]; 50 u8 res044[0x50 - 0x44];
45 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ 51 u32 gpindr; /* 0x.0050 - General-Purpose Input Data
52 * Register
53 */
46 u8 res054[0x60 - 0x54]; 54 u8 res054[0x60 - 0x54];
47 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ 55 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
48 __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */ 56 * Multiplex Control
49 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ 57 */
58 u32 pmuxcr2; /* 0x.0064 - Alternate function signal
59 * multiplex control 2
60 */
61 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
50 u8 res06c[0x70 - 0x6c]; 62 u8 res06c[0x70 - 0x6c];
51 __be32 devdisr; /* 0x.0070 - Device Disable Control */ 63 u32 devdisr; /* 0x.0070 - Device Disable Control */
52#define CCSR_GUTS_DEVDISR_TB1 0x00001000 64#define CCSR_GUTS_DEVDISR_TB1 0x00001000
53#define CCSR_GUTS_DEVDISR_TB0 0x00004000 65#define CCSR_GUTS_DEVDISR_TB0 0x00004000
54 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ 66 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
55 u8 res078[0x7c - 0x78]; 67 u8 res078[0x7c - 0x78];
56 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */ 68 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
57 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ 69 * Register
58 __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */ 70 */
59 __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */ 71 u32 powmgtcsr; /* 0x.0080 - Power Management Status and
60 __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */ 72 * Control Register
61 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ 73 */
62 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ 74 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
63 __be32 ectrstcr; /* 0x.0098 - Exception reset control register */ 75 * Configuration Register
64 __be32 autorstsr; /* 0x.009c - Automatic reset status register */ 76 */
65 __be32 pvr; /* 0x.00a0 - Processor Version Register */ 77 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
66 __be32 svr; /* 0x.00a4 - System Version Register */ 78 * Configuration Register
79 */
80 u32 pmcdr; /* 0x.008c - 4Power management clock disable
81 * register
82 */
83 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
84 u32 rstrscr; /* 0x.0094 - Reset Request Status and
85 * Control Register
86 */
87 u32 ectrstcr; /* 0x.0098 - Exception reset control register */
88 u32 autorstsr; /* 0x.009c - Automatic reset status register */
89 u32 pvr; /* 0x.00a0 - Processor Version Register */
90 u32 svr; /* 0x.00a4 - System Version Register */
67 u8 res0a8[0xb0 - 0xa8]; 91 u8 res0a8[0xb0 - 0xa8];
68 __be32 rstcr; /* 0x.00b0 - Reset Control Register */ 92 u32 rstcr; /* 0x.00b0 - Reset Control Register */
69 u8 res0b4[0xc0 - 0xb4]; 93 u8 res0b4[0xc0 - 0xb4];
70 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register 94 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
71 Called 'elbcvselcr' on 86xx SOCs */ 95 Called 'elbcvselcr' on 86xx SOCs */
72 u8 res0c4[0x100 - 0xc4]; 96 u8 res0c4[0x100 - 0xc4];
73 __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers 97 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
74 There are 16 registers */ 98 There are 16 registers */
75 u8 res140[0x224 - 0x140]; 99 u8 res140[0x224 - 0x140];
76 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ 100 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
77 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ 101 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
78 u8 res22c[0x604 - 0x22c]; 102 u8 res22c[0x604 - 0x22c];
79 __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ 103 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
80 u8 res608[0x800 - 0x608]; 104 u8 res608[0x800 - 0x608];
81 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ 105 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
82 u8 res804[0x900 - 0x804]; 106 u8 res804[0x900 - 0x804];
83 __be32 ircr; /* 0x.0900 - Infrared Control Register */ 107 u32 ircr; /* 0x.0900 - Infrared Control Register */
84 u8 res904[0x908 - 0x904]; 108 u8 res904[0x908 - 0x904];
85 __be32 dmacr; /* 0x.0908 - DMA Control Register */ 109 u32 dmacr; /* 0x.0908 - DMA Control Register */
86 u8 res90c[0x914 - 0x90c]; 110 u8 res90c[0x914 - 0x90c];
87 __be32 elbccr; /* 0x.0914 - eLBC Control Register */ 111 u32 elbccr; /* 0x.0914 - eLBC Control Register */
88 u8 res918[0xb20 - 0x918]; 112 u8 res918[0xb20 - 0x918];
89 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ 113 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
90 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ 114 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
91 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ 115 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
92 u8 resb2c[0xe00 - 0xb2c]; 116 u8 resb2c[0xe00 - 0xb2c];
93 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ 117 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
94 u8 rese04[0xe10 - 0xe04]; 118 u8 rese04[0xe10 - 0xe04];
95 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ 119 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
96 u8 rese14[0xe20 - 0xe14]; 120 u8 rese14[0xe20 - 0xe14];
97 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ 121 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
98 __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */ 122 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
123 * register
124 */
99 u8 rese28[0xf04 - 0xe28]; 125 u8 rese28[0xf04 - 0xe28];
100 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ 126 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
101 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ 127 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
102 u8 resf0c[0xf2c - 0xf0c]; 128 u8 resf0c[0xf2c - 0xf0c];
103 __be32 itcr; /* 0x.0f2c - Internal transaction control register */ 129 u32 itcr; /* 0x.0f2c - Internal transaction control
130 * register
131 */
104 u8 resf30[0xf40 - 0xf30]; 132 u8 resf30[0xf40 - 0xf30];
105 __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ 133 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
106 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ 134 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
107} __attribute__ ((packed)); 135} __attribute__ ((packed));
108 136
137u32 fsl_guts_get_svr(void);
109 138
110/* Alternate function signal multiplex control */ 139/* Alternate function signal multiplex control */
111#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) 140#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index 7a26286db895..fba44abd05ba 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -100,6 +100,11 @@
100#define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8) 100#define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8)
101 101
102/* 102/*
103 * Some controllers have a 32-bit wide data port register
104 */
105#define TMIO_MMC_32BIT_DATA_PORT (1 << 9)
106
107/*
103 * Some controllers allows to set SDx actual clock 108 * Some controllers allows to set SDx actual clock
104 */ 109 */
105#define TMIO_MMC_CLK_ACTUAL (1 << 10) 110#define TMIO_MMC_CLK_ACTUAL (1 << 10)
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 73fad83acbcb..95d69d498296 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -89,6 +89,8 @@ struct mmc_ext_csd {
89 unsigned int boot_ro_lock; /* ro lock support */ 89 unsigned int boot_ro_lock; /* ro lock support */
90 bool boot_ro_lockable; 90 bool boot_ro_lockable;
91 bool ffu_capable; /* Firmware upgrade support */ 91 bool ffu_capable; /* Firmware upgrade support */
92 bool cmdq_support; /* Command Queue supported */
93 unsigned int cmdq_depth; /* Command Queue depth */
92#define MMC_FIRMWARE_LEN 8 94#define MMC_FIRMWARE_LEN 8
93 u8 fwrev[MMC_FIRMWARE_LEN]; /* FW version */ 95 u8 fwrev[MMC_FIRMWARE_LEN]; /* FW version */
94 u8 raw_exception_status; /* 54 */ 96 u8 raw_exception_status; /* 54 */
@@ -207,18 +209,6 @@ struct sdio_func_tuple;
207 209
208#define SDIO_MAX_FUNCS 7 210#define SDIO_MAX_FUNCS 7
209 211
210enum mmc_blk_status {
211 MMC_BLK_SUCCESS = 0,
212 MMC_BLK_PARTIAL,
213 MMC_BLK_CMD_ERR,
214 MMC_BLK_RETRY,
215 MMC_BLK_ABORT,
216 MMC_BLK_DATA_ERR,
217 MMC_BLK_ECC_ERR,
218 MMC_BLK_NOMEDIUM,
219 MMC_BLK_NEW_REQUEST,
220};
221
222/* The number of MMC physical partitions. These consist of: 212/* The number of MMC physical partitions. These consist of:
223 * boot partitions (2), general purpose partitions (4) and 213 * boot partitions (2), general purpose partitions (4) and
224 * RPMB partition (1) in MMC v4.4. 214 * RPMB partition (1) in MMC v4.4.
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 2b953eb8ceae..e33cc748dcfe 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -15,6 +15,18 @@ struct request;
15struct mmc_data; 15struct mmc_data;
16struct mmc_request; 16struct mmc_request;
17 17
18enum mmc_blk_status {
19 MMC_BLK_SUCCESS = 0,
20 MMC_BLK_PARTIAL,
21 MMC_BLK_CMD_ERR,
22 MMC_BLK_RETRY,
23 MMC_BLK_ABORT,
24 MMC_BLK_DATA_ERR,
25 MMC_BLK_ECC_ERR,
26 MMC_BLK_NOMEDIUM,
27 MMC_BLK_NEW_REQUEST,
28};
29
18struct mmc_command { 30struct mmc_command {
19 u32 opcode; 31 u32 opcode;
20 u32 arg; 32 u32 arg;
@@ -150,7 +162,8 @@ struct mmc_async_req;
150extern int mmc_stop_bkops(struct mmc_card *); 162extern int mmc_stop_bkops(struct mmc_card *);
151extern int mmc_read_bkops_status(struct mmc_card *); 163extern int mmc_read_bkops_status(struct mmc_card *);
152extern struct mmc_async_req *mmc_start_req(struct mmc_host *, 164extern struct mmc_async_req *mmc_start_req(struct mmc_host *,
153 struct mmc_async_req *, int *); 165 struct mmc_async_req *,
166 enum mmc_blk_status *);
154extern int mmc_interrupt_hpi(struct mmc_card *); 167extern int mmc_interrupt_hpi(struct mmc_card *);
155extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *); 168extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
156extern void mmc_wait_for_req_done(struct mmc_host *host, 169extern void mmc_wait_for_req_done(struct mmc_host *host,
@@ -163,6 +176,7 @@ extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
163extern void mmc_start_bkops(struct mmc_card *card, bool from_exception); 176extern void mmc_start_bkops(struct mmc_card *card, bool from_exception);
164extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int); 177extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int);
165extern int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); 178extern int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error);
179extern int mmc_abort_tuning(struct mmc_host *host, u32 opcode);
166extern int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd); 180extern int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd);
167 181
168#define MMC_ERASE_ARG 0x00000000 182#define MMC_ERASE_ARG 0x00000000
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index f5af2bd35e7f..15db6f83f53f 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -39,6 +39,12 @@ enum {
39 EVENT_DATA_ERROR, 39 EVENT_DATA_ERROR,
40}; 40};
41 41
42enum dw_mci_cookie {
43 COOKIE_UNMAPPED,
44 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
45 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
46};
47
42struct mmc_data; 48struct mmc_data;
43 49
44enum { 50enum {
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 0b2439441cc8..8bc884121465 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -93,8 +93,7 @@ struct mmc_host_ops {
93 */ 93 */
94 void (*post_req)(struct mmc_host *host, struct mmc_request *req, 94 void (*post_req)(struct mmc_host *host, struct mmc_request *req,
95 int err); 95 int err);
96 void (*pre_req)(struct mmc_host *host, struct mmc_request *req, 96 void (*pre_req)(struct mmc_host *host, struct mmc_request *req);
97 bool is_first_req);
98 void (*request)(struct mmc_host *host, struct mmc_request *req); 97 void (*request)(struct mmc_host *host, struct mmc_request *req);
99 98
100 /* 99 /*
@@ -173,7 +172,7 @@ struct mmc_async_req {
173 * Check error status of completed mmc request. 172 * Check error status of completed mmc request.
174 * Returns 0 if success otherwise non zero. 173 * Returns 0 if success otherwise non zero.
175 */ 174 */
176 int (*err_check) (struct mmc_card *, struct mmc_async_req *); 175 enum mmc_blk_status (*err_check)(struct mmc_card *, struct mmc_async_req *);
177}; 176};
178 177
179/** 178/**
@@ -198,14 +197,12 @@ struct mmc_slot {
198 * @is_new_req wake up reason was new request 197 * @is_new_req wake up reason was new request
199 * @is_waiting_last_req mmc context waiting for single running request 198 * @is_waiting_last_req mmc context waiting for single running request
200 * @wait wait queue 199 * @wait wait queue
201 * @lock lock to protect data fields
202 */ 200 */
203struct mmc_context_info { 201struct mmc_context_info {
204 bool is_done_rcv; 202 bool is_done_rcv;
205 bool is_new_req; 203 bool is_new_req;
206 bool is_waiting_last_req; 204 bool is_waiting_last_req;
207 wait_queue_head_t wait; 205 wait_queue_head_t wait;
208 spinlock_t lock;
209}; 206};
210 207
211struct regulator; 208struct regulator;
@@ -495,11 +492,6 @@ static inline int mmc_host_uhs(struct mmc_host *host)
495 MMC_CAP_UHS_DDR50); 492 MMC_CAP_UHS_DDR50);
496} 493}
497 494
498static inline int mmc_host_packed_wr(struct mmc_host *host)
499{
500 return host->caps2 & MMC_CAP2_PACKED_WR;
501}
502
503static inline int mmc_card_hs(struct mmc_card *card) 495static inline int mmc_card_hs(struct mmc_card *card)
504{ 496{
505 return card->host->ios.timing == MMC_TIMING_SD_HS || 497 return card->host->ios.timing == MMC_TIMING_SD_HS ||
@@ -546,6 +538,11 @@ static inline void mmc_retune_recheck(struct mmc_host *host)
546 host->retune_now = 1; 538 host->retune_now = 1;
547} 539}
548 540
541static inline bool mmc_can_retune(struct mmc_host *host)
542{
543 return host->can_retune == 1;
544}
545
549void mmc_retune_pause(struct mmc_host *host); 546void mmc_retune_pause(struct mmc_host *host);
550void mmc_retune_unpause(struct mmc_host *host); 547void mmc_retune_unpause(struct mmc_host *host);
551 548
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index c376209c70ef..672730acc705 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -84,6 +84,13 @@
84#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ 84#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
85#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ 85#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
86 86
87 /* class 11 */
88#define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
89#define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */
90#define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */
91#define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */
92#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
93
87static inline bool mmc_op_multi(u32 opcode) 94static inline bool mmc_op_multi(u32 opcode)
88{ 95{
89 return opcode == MMC_WRITE_MULTIPLE_BLOCK || 96 return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
@@ -272,6 +279,7 @@ struct _mmc_csd {
272 * EXT_CSD fields 279 * EXT_CSD fields
273 */ 280 */
274 281
282#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
275#define EXT_CSD_FLUSH_CACHE 32 /* W */ 283#define EXT_CSD_FLUSH_CACHE 32 /* W */
276#define EXT_CSD_CACHE_CTRL 33 /* R/W */ 284#define EXT_CSD_CACHE_CTRL 33 /* R/W */
277#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ 285#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
@@ -331,6 +339,8 @@ struct _mmc_csd {
331#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ 339#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
332#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ 340#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
333#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ 341#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
342#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
343#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
334#define EXT_CSD_SUPPORTED_MODE 493 /* RO */ 344#define EXT_CSD_SUPPORTED_MODE 493 /* RO */
335#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ 345#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
336#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ 346#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
@@ -438,6 +448,13 @@ struct _mmc_csd {
438#define EXT_CSD_MANUAL_BKOPS_MASK 0x01 448#define EXT_CSD_MANUAL_BKOPS_MASK 0x01
439 449
440/* 450/*
451 * Command Queue
452 */
453#define EXT_CSD_CMDQ_MODE_ENABLED BIT(0)
454#define EXT_CSD_CMDQ_DEPTH_MASK GENMASK(4, 0)
455#define EXT_CSD_CMDQ_SUPPORTED BIT(0)
456
457/*
441 * MMC_SWITCH access modes 458 * MMC_SWITCH access modes
442 */ 459 */
443 460
diff --git a/include/linux/mmc/slot-gpio.h b/include/linux/mmc/slot-gpio.h
index 3945a8c9d3cb..a7972cd3bc14 100644
--- a/include/linux/mmc/slot-gpio.h
+++ b/include/linux/mmc/slot-gpio.h
@@ -29,5 +29,6 @@ int mmc_gpiod_request_ro(struct mmc_host *host, const char *con_id,
29void mmc_gpio_set_cd_isr(struct mmc_host *host, 29void mmc_gpio_set_cd_isr(struct mmc_host *host,
30 irqreturn_t (*isr)(int irq, void *dev_id)); 30 irqreturn_t (*isr)(int irq, void *dev_id));
31void mmc_gpiod_request_cd_irq(struct mmc_host *host); 31void mmc_gpiod_request_cd_irq(struct mmc_host *host);
32bool mmc_can_gpio_cd(struct mmc_host *host);
32 33
33#endif 34#endif
diff --git a/include/linux/sys_soc.h b/include/linux/sys_soc.h
index 2739ccb69571..bed223b70217 100644
--- a/include/linux/sys_soc.h
+++ b/include/linux/sys_soc.h
@@ -13,6 +13,7 @@ struct soc_device_attribute {
13 const char *family; 13 const char *family;
14 const char *revision; 14 const char *revision;
15 const char *soc_id; 15 const char *soc_id;
16 const void *data;
16}; 17};
17 18
18/** 19/**
@@ -34,4 +35,12 @@ void soc_device_unregister(struct soc_device *soc_dev);
34 */ 35 */
35struct device *soc_device_to_device(struct soc_device *soc); 36struct device *soc_device_to_device(struct soc_device *soc);
36 37
38#ifdef CONFIG_SOC_BUS
39const struct soc_device_attribute *soc_device_match(
40 const struct soc_device_attribute *matches);
41#else
42static inline const struct soc_device_attribute *soc_device_match(
43 const struct soc_device_attribute *matches) { return NULL; }
44#endif
45
37#endif /* __SOC_BUS_H */ 46#endif /* __SOC_BUS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-06-02 18:29:19 -0400