diff options
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/pxa2xx_ssp.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h index 2d6f0c39ed68..a0522328d7aa 100644 --- a/include/linux/pxa2xx_ssp.h +++ b/include/linux/pxa2xx_ssp.h | |||
| @@ -90,9 +90,9 @@ | |||
| 90 | #define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */ | 90 | #define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */ |
| 91 | 91 | ||
| 92 | #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ | 92 | #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ |
| 93 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ | 93 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ |
| 94 | #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ | 94 | #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ |
| 95 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ | 95 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ |
| 96 | 96 | ||
| 97 | #define RX_THRESH_CE4100_DFLT 2 | 97 | #define RX_THRESH_CE4100_DFLT 2 |
| 98 | #define TX_THRESH_CE4100_DFLT 2 | 98 | #define TX_THRESH_CE4100_DFLT 2 |
| @@ -106,9 +106,9 @@ | |||
| 106 | #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ | 106 | #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ |
| 107 | 107 | ||
| 108 | /* QUARK_X1000 SSCR0 bit definition */ | 108 | /* QUARK_X1000 SSCR0 bit definition */ |
| 109 | #define QUARK_X1000_SSCR0_DSS (0x1F) /* Data Size Select (mask) */ | 109 | #define QUARK_X1000_SSCR0_DSS (0x1F << 0) /* Data Size Select (mask) */ |
| 110 | #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */ | 110 | #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */ |
| 111 | #define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */ | 111 | #define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */ |
| 112 | #define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */ | 112 | #define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */ |
| 113 | 113 | ||
| 114 | #define RX_THRESH_QUARK_X1000_DFLT 1 | 114 | #define RX_THRESH_QUARK_X1000_DFLT 1 |
| @@ -121,8 +121,8 @@ | |||
| 121 | #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */ | 121 | #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */ |
| 122 | #define QUARK_X1000_SSCR1_RFT (0x1F << 11) /* Receive FIFO Threshold (mask) */ | 122 | #define QUARK_X1000_SSCR1_RFT (0x1F << 11) /* Receive FIFO Threshold (mask) */ |
| 123 | #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */ | 123 | #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */ |
| 124 | #define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */ | 124 | #define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */ |
| 125 | #define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */ | 125 | #define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */ |
| 126 | 126 | ||
| 127 | /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ | 127 | /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ |
| 128 | #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ | 128 | #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ |