3 files changed, 155 insertions, 7 deletions

diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
index 379c02648ab3..64d25941b329 100644
--- a/include/linux/mlx4/cmd.h
+++ b/include/linux/mlx4/cmd.h
@@ -67,6 +67,8 @@ enum {
         MLX4_CMD_MAP_ICM_AUX     = 0xffc,
         MLX4_CMD_UNMAP_ICM_AUX   = 0xffb,
         MLX4_CMD_SET_ICM_SIZE    = 0xffd,
+        MLX4_CMD_ACCESS_REG      = 0x3b,
+
         /*master notify fw on finish for slave's flr*/
         MLX4_CMD_INFORM_FLR_DONE = 0x5b,
         MLX4_CMD_GET_OP_REQ      = 0x59,
@@ -197,6 +199,33 @@ enum {
         MLX4_CMD_NATIVE
 };
 
+/*
+ * MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP -
+ * Receive checksum value is reported in CQE also for non TCP/UDP packets.
+ *
+ * MLX4_RX_CSUM_MODE_L4 -
+ * L4_CSUM bit in CQE, which indicates whether or not L4 checksum
+ * was validated correctly, is supported.
+ *
+ * MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP -
+ * IP_OK CQE's field is supported also for non TCP/UDP IP packets.
+ *
+ * MLX4_RX_CSUM_MODE_MULTI_VLAN -
+ * Receive Checksum offload is supported for packets with more than 2 vlan headers.
+ */
+enum mlx4_rx_csum_mode {
+        MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP               = 1UL << 0,
+        MLX4_RX_CSUM_MODE_L4                            = 1UL << 1,
+        MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP          = 1UL << 2,
+        MLX4_RX_CSUM_MODE_MULTI_VLAN                    = 1UL << 3
+};
+
+struct mlx4_config_dev_params {
+        u16     vxlan_udp_dport;
+        u8      rx_csum_flags_port_1;
+        u8      rx_csum_flags_port_2;
+};
+
 struct mlx4_dev;
 
 struct mlx4_cmd_mailbox {
@@ -248,6 +277,8 @@ int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos);
 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting);
 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf);
 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state);
+int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
+                              struct mlx4_config_dev_params *params);
 /*
  * mlx4_get_slave_default_vlan -
  * return true if VST ( default vlan)
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 37e4404d0227..25c791e295fd 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -95,7 +95,7 @@ enum {
 
 enum {
         MLX4_MAX_NUM_PF         = 16,
-        MLX4_MAX_NUM_VF         = 64,
+        MLX4_MAX_NUM_VF         = 126,
         MLX4_MAX_NUM_VF_P_PORT  = 64,
         MLX4_MFUNC_MAX          = 80,
         MLX4_MAX_EQ_NUM         = 1024,
@@ -117,6 +117,14 @@ enum {
         MLX4_STEERING_MODE_DEVICE_MANAGED
 };
 
+enum {
+        MLX4_STEERING_DMFS_A0_DEFAULT,
+        MLX4_STEERING_DMFS_A0_DYNAMIC,
+        MLX4_STEERING_DMFS_A0_STATIC,
+        MLX4_STEERING_DMFS_A0_DISABLE,
+        MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
+};
+
 static inline const char *mlx4_steering_mode_str(int steering_mode)
 {
         switch (steering_mode) {
@@ -186,7 +194,31 @@ enum {
         MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS       = 1LL <<  10,
         MLX4_DEV_CAP_FLAG2_MAD_DEMUX            = 1LL <<  11,
         MLX4_DEV_CAP_FLAG2_CQE_STRIDE           = 1LL <<  12,
-        MLX4_DEV_CAP_FLAG2_EQE_STRIDE           = 1LL <<  13
+        MLX4_DEV_CAP_FLAG2_EQE_STRIDE           = 1LL <<  13,
+        MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL        = 1LL <<  14,
+        MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP    = 1LL <<  15,
+        MLX4_DEV_CAP_FLAG2_CONFIG_DEV           = 1LL <<  16,
+        MLX4_DEV_CAP_FLAG2_SYS_EQS              = 1LL <<  17,
+        MLX4_DEV_CAP_FLAG2_80_VFS               = 1LL <<  18,
+        MLX4_DEV_CAP_FLAG2_FS_A0                = 1LL <<  19
+};
+
+enum {
+        MLX4_QUERY_FUNC_FLAGS_BF_RES_QP         = 1LL << 0,
+        MLX4_QUERY_FUNC_FLAGS_A0_RES_QP         = 1LL << 1
+};
+
+/* bit enums for an 8-bit flags field indicating special use
+ * QPs which require special handling in qp_reserve_range.
+ * Currently, this only includes QPs used by the ETH interface,
+ * where we expect to use blueflame.  These QPs must not have
+ * bits 6 and 7 set in their qp number.
+ *
+ * This enum may use only bits 0..7.
+ */
+enum {
+        MLX4_RESERVE_A0_QP      = 1 << 6,
+        MLX4_RESERVE_ETH_BF_QP  = 1 << 7,
 };
 
 enum {
@@ -202,7 +234,8 @@ enum {
 
 enum {
         MLX4_FUNC_CAP_64B_EQE_CQE       = 1L << 0,
-        MLX4_FUNC_CAP_EQE_CQE_STRIDE    = 1L << 1
+        MLX4_FUNC_CAP_EQE_CQE_STRIDE    = 1L << 1,
+        MLX4_FUNC_CAP_DMFS_A0_STATIC    = 1L << 2
 };
 
 
@@ -328,6 +361,8 @@ enum {
 
 enum mlx4_qp_region {
         MLX4_QP_REGION_FW = 0,
+        MLX4_QP_REGION_RSS_RAW_ETH,
+        MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
         MLX4_QP_REGION_ETH_ADDR,
         MLX4_QP_REGION_FC_ADDR,
         MLX4_QP_REGION_FC_EXCH,
@@ -379,6 +414,13 @@ enum {
 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
                              MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
 
+enum mlx4_module_id {
+        MLX4_MODULE_ID_SFP              = 0x3,
+        MLX4_MODULE_ID_QSFP             = 0xC,
+        MLX4_MODULE_ID_QSFP_PLUS        = 0xD,
+        MLX4_MODULE_ID_QSFP28           = 0x11,
+};
+
 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
 {
         return (major << 32) | (minor << 16) | subminor;
@@ -433,6 +475,7 @@ struct mlx4_caps {
         int                     num_cqs;
         int                     max_cqes;
         int                     reserved_cqs;
+        int                     num_sys_eqs;
         int                     num_eqs;
         int                     reserved_eqs;
         int                     num_comp_vectors;
@@ -449,6 +492,7 @@ struct mlx4_caps {
         int                     reserved_mcgs;
         int                     num_qp_per_mgm;
         int                     steering_mode;
+        int                     dmfs_high_steer_mode;
         int                     fs_log_max_ucast_qp_range_size;
         int                     num_pds;
         int                     reserved_pds;
@@ -487,6 +531,10 @@ struct mlx4_caps {
         u16                     hca_core_clock;
         u64                     phys_port_id[MLX4_MAX_PORTS + 1];
         int                     tunnel_offload_mode;
+        u8                      rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
+        u8                      alloc_res_qp_mask;
+        u32                     dmfs_high_rate_qpn_base;
+        u32                     dmfs_high_rate_qpn_range;
 };
 
 struct mlx4_buf_list {
@@ -607,6 +655,11 @@ struct mlx4_cq {
 
         atomic_t                refcount;
         struct completion       free;