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-rw-r--r--include/linux/mfd/88pm80x.h2
-rw-r--r--include/linux/mfd/abx500.h34
-rw-r--r--include/linux/mfd/abx500/ab8500.h4
-rw-r--r--include/linux/mfd/arizona/core.h4
-rw-r--r--include/linux/mfd/arizona/pdata.h6
-rw-r--r--include/linux/mfd/arizona/registers.h17
-rw-r--r--include/linux/mfd/as3711.h126
-rw-r--r--include/linux/mfd/da9052/da9052.h10
-rw-r--r--include/linux/mfd/da9055/core.h2
-rw-r--r--include/linux/mfd/da9055/pdata.h29
-rw-r--r--include/linux/mfd/da9055/reg.h2
-rw-r--r--include/linux/mfd/db8500-prcmu.h4
-rw-r--r--include/linux/mfd/dbx500-prcmu.h10
-rw-r--r--include/linux/mfd/lp8788.h8
-rw-r--r--include/linux/mfd/max8997-private.h1
-rw-r--r--include/linux/mfd/max8997.h1
-rw-r--r--include/linux/mfd/menelaus.h47
-rw-r--r--include/linux/mfd/pm8xxx/irq.h8
-rw-r--r--include/linux/mfd/rc5t583.h3
-rw-r--r--include/linux/mfd/retu.h22
-rw-r--r--include/linux/mfd/rtsx_common.h48
-rw-r--r--include/linux/mfd/rtsx_pci.h794
-rw-r--r--include/linux/mfd/sta2x11-mfd.h198
-rw-r--r--include/linux/mfd/stmpe.h4
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h152
-rw-r--r--include/linux/mfd/tps65090.h104
-rw-r--r--include/linux/mfd/tps6586x.h4
-rw-r--r--include/linux/mfd/tps65910.h145
-rw-r--r--include/linux/mfd/tps80031.h637
-rw-r--r--include/linux/mfd/twl6040.h10
-rw-r--r--include/linux/mfd/viperboard.h110
-rw-r--r--include/linux/mfd/wm8994/core.h4
-rw-r--r--include/linux/mfd/wm8994/pdata.h5
33 files changed, 2438 insertions, 117 deletions
diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h
index a0ca0dca1244..478672ed0c3d 100644
--- a/include/linux/mfd/88pm80x.h
+++ b/include/linux/mfd/88pm80x.h
@@ -364,6 +364,6 @@ static inline int pm80x_dev_resume(struct device *dev)
364#endif 364#endif
365 365
366extern int pm80x_init(struct i2c_client *client, 366extern int pm80x_init(struct i2c_client *client,
367 const struct i2c_device_id *id) __devinit; 367 const struct i2c_device_id *id);
368extern int pm80x_deinit(struct i2c_client *client); 368extern int pm80x_deinit(struct i2c_client *client);
369#endif /* __LINUX_MFD_88PM80X_H */ 369#endif /* __LINUX_MFD_88PM80X_H */
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 5d5298d56026..2138bd33021a 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -267,39 +267,21 @@ struct abx500_bm_data {
267 int gnd_lift_resistance; 267 int gnd_lift_resistance;
268 const struct abx500_maxim_parameters *maxi; 268 const struct abx500_maxim_parameters *maxi;
269 const struct abx500_bm_capacity_levels *cap_levels; 269 const struct abx500_bm_capacity_levels *cap_levels;
270 const struct abx500_battery_type *bat_type; 270 struct abx500_battery_type *bat_type;
271 const struct abx500_bm_charger_parameters *chg_params; 271 const struct abx500_bm_charger_parameters *chg_params;
272 const struct abx500_fg_parameters *fg_params; 272 const struct abx500_fg_parameters *fg_params;
273}; 273};
274 274
275struct abx500_chargalg_platform_data { 275extern struct abx500_bm_data ab8500_bm_data;
276 char **supplied_to;
277 size_t num_supplicants;
278};
279
280struct abx500_charger_platform_data {
281 char **supplied_to;
282 size_t num_supplicants;
283 bool autopower_cfg;
284};
285 276
286struct abx500_btemp_platform_data { 277enum {
287 char **supplied_to; 278 NTC_EXTERNAL = 0,
288 size_t num_supplicants; 279 NTC_INTERNAL,
289}; 280};
290 281
291struct abx500_fg_platform_data { 282int bmdevs_of_probe(struct device *dev,
292 char **supplied_to; 283 struct device_node *np,
293 size_t num_supplicants; 284 struct abx500_bm_data **battery);
294};
295
296struct abx500_bm_plat_data {
297 struct abx500_bm_data *battery;
298 struct abx500_charger_platform_data *charger;
299 struct abx500_btemp_platform_data *btemp;
300 struct abx500_fg_platform_data *fg;
301 struct abx500_chargalg_platform_data *chargalg;
302};
303 285
304int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, 286int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
305 u8 value); 287 u8 value);
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 1491044efa10..1cb5698b4d76 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -291,9 +291,9 @@ struct ab8500_platform_data {
291 struct ab8500_codec_platform_data *codec; 291 struct ab8500_codec_platform_data *codec;
292}; 292};
293 293
294extern int __devinit ab8500_init(struct ab8500 *ab8500, 294extern int ab8500_init(struct ab8500 *ab8500,
295 enum ab8500_version version); 295 enum ab8500_version version);
296extern int __devexit ab8500_exit(struct ab8500 *ab8500); 296extern int ab8500_exit(struct ab8500 *ab8500);
297 297
298extern int ab8500_suspend(struct ab8500 *ab8500); 298extern int ab8500_suspend(struct ab8500 *ab8500);
299 299
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
index dd231ac0bb1f..a580363a7d29 100644
--- a/include/linux/mfd/arizona/core.h
+++ b/include/linux/mfd/arizona/core.h
@@ -78,6 +78,8 @@ enum arizona_type {
78 78
79#define ARIZONA_NUM_IRQ 50 79#define ARIZONA_NUM_IRQ 50
80 80
81struct snd_soc_dapm_context;
82
81struct arizona { 83struct arizona {
82 struct regmap *regmap; 84 struct regmap *regmap;
83 struct device *dev; 85 struct device *dev;
@@ -98,6 +100,8 @@ struct arizona {
98 100
99 struct mutex clk_lock; 101 struct mutex clk_lock;
100 int clk32k_ref; 102 int clk32k_ref;
103
104 struct snd_soc_dapm_context *dapm;
101}; 105};
102 106
103int arizona_clk32k_enable(struct arizona *arizona); 107int arizona_clk32k_enable(struct arizona *arizona);
diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h
index 7ab442905a57..8b1d1daaae16 100644
--- a/include/linux/mfd/arizona/pdata.h
+++ b/include/linux/mfd/arizona/pdata.h
@@ -62,6 +62,9 @@
62 62
63#define ARIZONA_MAX_OUTPUT 6 63#define ARIZONA_MAX_OUTPUT 6
64 64
65#define ARIZONA_HAP_ACT_ERM 0
66#define ARIZONA_HAP_ACT_LRA 2
67
65#define ARIZONA_MAX_PDM_SPK 2 68#define ARIZONA_MAX_PDM_SPK 2
66 69
67struct regulator_init_data; 70struct regulator_init_data;
@@ -114,6 +117,9 @@ struct arizona_pdata {
114 117
115 /** PDM speaker format */ 118 /** PDM speaker format */
116 unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK]; 119 unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
120
121 /** Haptic actuator type */
122 unsigned int hap_act;
117}; 123};
118 124
119#endif 125#endif
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 7671a287dfee..1f6fe31a4d5c 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -76,6 +76,7 @@
76#define ARIZONA_RATE_ESTIMATOR_3 0x154 76#define ARIZONA_RATE_ESTIMATOR_3 0x154
77#define ARIZONA_RATE_ESTIMATOR_4 0x155 77#define ARIZONA_RATE_ESTIMATOR_4 0x155
78#define ARIZONA_RATE_ESTIMATOR_5 0x156 78#define ARIZONA_RATE_ESTIMATOR_5 0x156
79#define ARIZONA_DYNAMIC_FREQUENCY_SCALING_1 0x161
79#define ARIZONA_FLL1_CONTROL_1 0x171 80#define ARIZONA_FLL1_CONTROL_1 0x171
80#define ARIZONA_FLL1_CONTROL_2 0x172 81#define ARIZONA_FLL1_CONTROL_2 0x172
81#define ARIZONA_FLL1_CONTROL_3 0x173 82#define ARIZONA_FLL1_CONTROL_3 0x173
@@ -110,6 +111,7 @@
110#define ARIZONA_FLL2_GPIO_CLOCK 0x1AA 111#define ARIZONA_FLL2_GPIO_CLOCK 0x1AA
111#define ARIZONA_MIC_CHARGE_PUMP_1 0x200 112#define ARIZONA_MIC_CHARGE_PUMP_1 0x200
112#define ARIZONA_LDO1_CONTROL_1 0x210 113#define ARIZONA_LDO1_CONTROL_1 0x210
114#define ARIZONA_LDO1_CONTROL_2 0x212
113#define ARIZONA_LDO2_CONTROL_1 0x213 115#define ARIZONA_LDO2_CONTROL_1 0x213
114#define ARIZONA_MIC_BIAS_CTRL_1 0x218 116#define ARIZONA_MIC_BIAS_CTRL_1 0x218
115#define ARIZONA_MIC_BIAS_CTRL_2 0x219 117#define ARIZONA_MIC_BIAS_CTRL_2 0x219
@@ -979,6 +981,7 @@
979#define ARIZONA_DSP1_CLOCKING_1 0x1101 981#define ARIZONA_DSP1_CLOCKING_1 0x1101
980#define ARIZONA_DSP1_STATUS_1 0x1104 982#define ARIZONA_DSP1_STATUS_1 0x1104
981#define ARIZONA_DSP1_STATUS_2 0x1105 983#define ARIZONA_DSP1_STATUS_2 0x1105
984#define ARIZONA_DSP1_STATUS_3 0x1106
982#define ARIZONA_DSP2_CONTROL_1 0x1200 985#define ARIZONA_DSP2_CONTROL_1 0x1200
983#define ARIZONA_DSP2_CLOCKING_1 0x1201 986#define ARIZONA_DSP2_CLOCKING_1 0x1201
984#define ARIZONA_DSP2_STATUS_1 0x1204 987#define ARIZONA_DSP2_STATUS_1 0x1204
@@ -1574,6 +1577,13 @@
1574#define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH 5 /* SAMPLE_RATE_DETECT_D - [4:0] */ 1577#define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH 5 /* SAMPLE_RATE_DETECT_D - [4:0] */
1575 1578
1576/* 1579/*
1580 * R353 (0x161) - Dynamic Frequency Scaling 1
1581 */
1582#define ARIZONA_SUBSYS_MAX_FREQ 0x0001 /* SUBSYS_MAX_FREQ */
1583#define ARIZONA_SUBSYS_MAX_FREQ_SHIFT 0 /* SUBSYS_MAX_FREQ */
1584#define ARIZONA_SUBSYS_MAX_FREQ_WIDTH 1 /* SUBSYS_MAX_FREQ */
1585
1586/*
1577 * R369 (0x171) - FLL1 Control 1 1587 * R369 (0x171) - FLL1 Control 1
1578 */ 1588 */
1579#define ARIZONA_FLL1_FREERUN 0x0002 /* FLL1_FREERUN */ 1589#define ARIZONA_FLL1_FREERUN 0x0002 /* FLL1_FREERUN */
@@ -1889,6 +1899,13 @@
1889#define ARIZONA_LDO1_ENA_WIDTH 1 /* LDO1_ENA */ 1899#define ARIZONA_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
1890 1900
1891/* 1901/*
1902 * R530 (0x212) - LDO1 Control 2
1903 */
1904#define ARIZONA_LDO1_HI_PWR 0x0001 /* LDO1_HI_PWR */
1905#define ARIZONA_LDO1_HI_PWR_SHIFT 0 /* LDO1_HI_PWR */
1906#define ARIZONA_LDO1_HI_PWR_WIDTH 1 /* LDO1_HI_PWR */
1907
1908/*
1892 * R531 (0x213) - LDO2 Control 1 1909 * R531 (0x213) - LDO2 Control 1
1893 */ 1910 */
1894#define ARIZONA_LDO2_VSEL_MASK 0x07E0 /* LDO2_VSEL - [10:5] */ 1911#define ARIZONA_LDO2_VSEL_MASK 0x07E0 /* LDO2_VSEL - [10:5] */
diff --git a/include/linux/mfd/as3711.h b/include/linux/mfd/as3711.h
new file mode 100644
index 000000000000..38452ce1e892
--- /dev/null
+++ b/include/linux/mfd/as3711.h
@@ -0,0 +1,126 @@
1/*
2 * AS3711 PMIC MFC driver header
3 *
4 * Copyright (C) 2012 Renesas Electronics Corporation
5 * Author: Guennadi Liakhovetski, <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the version 2 of the GNU General Public License as
9 * published by the Free Software Foundation
10 */
11
12#ifndef MFD_AS3711_H
13#define MFD_AS3711_H
14
15/*
16 * Client data
17 */
18
19/* Register addresses */
20#define AS3711_SD_1_VOLTAGE 0 /* Digital Step-Down */
21#define AS3711_SD_2_VOLTAGE 1
22#define AS3711_SD_3_VOLTAGE 2
23#define AS3711_SD_4_VOLTAGE 3
24#define AS3711_LDO_1_VOLTAGE 4 /* Analog LDO */
25#define AS3711_LDO_2_VOLTAGE 5
26#define AS3711_LDO_3_VOLTAGE 6 /* Digital LDO */
27#define AS3711_LDO_4_VOLTAGE 7
28#define AS3711_LDO_5_VOLTAGE 8
29#define AS3711_LDO_6_VOLTAGE 9
30#define AS3711_LDO_7_VOLTAGE 0xa
31#define AS3711_LDO_8_VOLTAGE 0xb
32#define AS3711_SD_CONTROL 0x10
33#define AS3711_GPIO_SIGNAL_OUT 0x20
34#define AS3711_GPIO_SIGNAL_IN 0x21
35#define AS3711_SD_CONTROL_1 0x30
36#define AS3711_SD_CONTROL_2 0x31
37#define AS3711_CURR_CONTROL 0x40
38#define AS3711_CURR1_VALUE 0x43
39#define AS3711_CURR2_VALUE 0x44
40#define AS3711_CURR3_VALUE 0x45
41#define AS3711_STEPUP_CONTROL_1 0x50
42#define AS3711_STEPUP_CONTROL_2 0x51
43#define AS3711_STEPUP_CONTROL_4 0x53
44#define AS3711_STEPUP_CONTROL_5 0x54
45#define AS3711_REG_STATUS 0x73
46#define AS3711_INTERRUPT_STATUS_1 0x77
47#define AS3711_INTERRUPT_STATUS_2 0x78
48#define AS3711_INTERRUPT_STATUS_3 0x79
49#define AS3711_CHARGER_STATUS_1 0x86
50#define AS3711_CHARGER_STATUS_2 0x87
51#define AS3711_ASIC_ID_1 0x90
52#define AS3711_ASIC_ID_2 0x91
53
54#define AS3711_MAX_REGS 0x92
55
56/* Regulators */
57enum {
58 AS3711_REGULATOR_SD_1,
59 AS3711_REGULATOR_SD_2,
60 AS3711_REGULATOR_SD_3,
61 AS3711_REGULATOR_SD_4,
62 AS3711_REGULATOR_LDO_1,
63 AS3711_REGULATOR_LDO_2,
64 AS3711_REGULATOR_LDO_3,
65 AS3711_REGULATOR_LDO_4,
66 AS3711_REGULATOR_LDO_5,
67 AS3711_REGULATOR_LDO_6,
68 AS3711_REGULATOR_LDO_7,
69 AS3711_REGULATOR_LDO_8,
70
71 AS3711_REGULATOR_MAX,
72};
73
74struct device;
75struct regmap;
76
77struct as3711 {
78 struct device *dev;
79 struct regmap *regmap;
80};
81
82#define AS3711_MAX_STEPDOWN 4
83#define AS3711_MAX_STEPUP 2
84#define AS3711_MAX_LDO 8
85
86enum as3711_su2_feedback {
87 AS3711_SU2_VOLTAGE,
88 AS3711_SU2_CURR1,
89 AS3711_SU2_CURR2,
90 AS3711_SU2_CURR3,
91 AS3711_SU2_CURR_AUTO,
92};
93
94enum as3711_su2_fbprot {
95 AS3711_SU2_LX_SD4,
96 AS3711_SU2_GPIO2,
97 AS3711_SU2_GPIO3,
98 AS3711_SU2_GPIO4,
99};
100
101/*
102 * Platform data
103 */
104
105struct as3711_regulator_pdata {
106 struct regulator_init_data *init_data[AS3711_REGULATOR_MAX];
107};
108
109struct as3711_bl_pdata {
110 const char *su1_fb;
111 int su1_max_uA;
112 const char *su2_fb;
113 int su2_max_uA;
114 enum as3711_su2_feedback su2_feedback;
115 enum as3711_su2_fbprot su2_fbprot;
116 bool su2_auto_curr1;
117 bool su2_auto_curr2;
118 bool su2_auto_curr3;
119};
120
121struct as3711_platform_data {
122 struct as3711_regulator_pdata regulator;
123 struct as3711_bl_pdata backlight;
124};
125
126#endif
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
index 0507c4c21a7d..86dd93de6ff2 100644
--- a/include/linux/mfd/da9052/da9052.h
+++ b/include/linux/mfd/da9052/da9052.h
@@ -146,4 +146,14 @@ void da9052_device_exit(struct da9052 *da9052);
146 146
147extern struct regmap_config da9052_regmap_config; 147extern struct regmap_config da9052_regmap_config;
148 148
149int da9052_irq_init(struct da9052 *da9052);
150int da9052_irq_exit(struct da9052 *da9052);
151int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
152 irq_handler_t handler, void *data);
153void da9052_free_irq(struct da9052 *da9052, int irq, void *data);
154
155int da9052_enable_irq(struct da9052 *da9052, int irq);
156int da9052_disable_irq(struct da9052 *da9052, int irq);
157int da9052_disable_irq_nosync(struct da9052 *da9052, int irq);
158
149#endif /* __MFD_DA9052_DA9052_H */ 159#endif /* __MFD_DA9052_DA9052_H */
diff --git a/include/linux/mfd/da9055/core.h b/include/linux/mfd/da9055/core.h
index c96ad682c59e..956afa445998 100644
--- a/include/linux/mfd/da9055/core.h
+++ b/include/linux/mfd/da9055/core.h
@@ -1,4 +1,4 @@
1/* 1/*
2 * da9055 declarations for DA9055 PMICs. 2 * da9055 declarations for DA9055 PMICs.
3 * 3 *
4 * Copyright(c) 2012 Dialog Semiconductor Ltd. 4 * Copyright(c) 2012 Dialog Semiconductor Ltd.
diff --git a/include/linux/mfd/da9055/pdata.h b/include/linux/mfd/da9055/pdata.h
index 147293b4471d..04e092be4b07 100644
--- a/include/linux/mfd/da9055/pdata.h
+++ b/include/linux/mfd/da9055/pdata.h
@@ -1,4 +1,4 @@
1/* Copyright (C) 2012 Dialog Semiconductor Ltd. 1/* Copyright (C) 2012 Dialog Semiconductor Ltd.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by 4 * it under the terms of the GNU General Public License as published by
@@ -25,8 +25,29 @@ struct da9055_pdata {
25 int gpio_base; 25 int gpio_base;
26 26
27 struct regulator_init_data *regulators[DA9055_MAX_REGULATORS]; 27 struct regulator_init_data *regulators[DA9055_MAX_REGULATORS];
28 bool reset_enable; /* Enable RTC in RESET Mode */ 28 /* Enable RTC in RESET Mode */
29 enum gpio_select *gpio_rsel; /* Select regulator set thru GPIO 1/2 */ 29 bool reset_enable;
30 enum gpio_select *gpio_ren; /* Enable regulator thru GPIO 1/2 */ 30 /*
31 * GPI muxed pin to control
32 * regulator state A/B, 0 if not available.
33 */
34 int *gpio_ren;
35 /*
36 * GPI muxed pin to control
37 * regulator set, 0 if not available.
38 */
39 int *gpio_rsel;
40 /*
41 * Regulator mode control bits value (GPI offset) that
42 * that controls the regulator state, 0 if not available.
43 */
44 enum gpio_select *reg_ren;
45 /*
46 * Regulator mode control bits value (GPI offset) that
47 * controls the regulator set A/B, 0 if not available.
48 */
49 enum gpio_select *reg_rsel;
50 /* GPIOs to enable regulator, 0 if not available */
51 int *ena_gpio;
31}; 52};
32#endif /* __DA9055_PDATA_H */ 53#endif /* __DA9055_PDATA_H */
diff --git a/include/linux/mfd/da9055/reg.h b/include/linux/mfd/da9055/reg.h
index df237ee54803..2b592e072dbf 100644
--- a/include/linux/mfd/da9055/reg.h
+++ b/include/linux/mfd/da9055/reg.h
@@ -1,4 +1,4 @@
1/* 1/*
2 * DA9055 declarations for DA9055 PMICs. 2 * DA9055 declarations for DA9055 PMICs.
3 * 3 *
4 * Copyright(c) 2012 Dialog Semiconductor Ltd. 4 * Copyright(c) 2012 Dialog Semiconductor Ltd.
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index b82f6ee66a0b..6ee4247df11e 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -515,7 +515,6 @@ enum romcode_read prcmu_get_rc_p2a(void);
515enum ap_pwrst prcmu_get_xp70_current_state(void); 515enum ap_pwrst prcmu_get_xp70_current_state(void);
516bool prcmu_has_arm_maxopp(void); 516bool prcmu_has_arm_maxopp(void);
517struct prcmu_fw_version *prcmu_get_fw_version(void); 517struct prcmu_fw_version *prcmu_get_fw_version(void);
518int prcmu_request_ape_opp_100_voltage(bool enable);
519int prcmu_release_usb_wakeup_state(void); 518int prcmu_release_usb_wakeup_state(void);
520void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 519void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
521 struct prcmu_auto_pm_config *idle); 520 struct prcmu_auto_pm_config *idle);
@@ -564,6 +563,7 @@ int db8500_prcmu_set_arm_opp(u8 opp);
564int db8500_prcmu_get_arm_opp(void); 563int db8500_prcmu_get_arm_opp(void);
565int db8500_prcmu_set_ape_opp(u8 opp); 564int db8500_prcmu_set_ape_opp(u8 opp);
566int db8500_prcmu_get_ape_opp(void); 565int db8500_prcmu_get_ape_opp(void);
566int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
567int db8500_prcmu_set_ddr_opp(u8 opp); 567int db8500_prcmu_set_ddr_opp(u8 opp);
568int db8500_prcmu_get_ddr_opp(void); 568int db8500_prcmu_get_ddr_opp(void);
569 569
@@ -610,7 +610,7 @@ static inline int db8500_prcmu_get_ape_opp(void)
610 return APE_100_OPP; 610 return APE_100_OPP;
611} 611}
612 612
613static inline int prcmu_request_ape_opp_100_voltage(bool enable) 613static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
614{ 614{
615 return 0; 615 return 0;
616} 616}
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index c410d99bd667..c202d6c4d879 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -336,6 +336,11 @@ static inline int prcmu_get_ape_opp(void)
336 return db8500_prcmu_get_ape_opp(); 336 return db8500_prcmu_get_ape_opp();
337} 337}
338 338
339static inline int prcmu_request_ape_opp_100_voltage(bool enable)
340{
341 return db8500_prcmu_request_ape_opp_100_voltage(enable);
342}
343
339static inline void prcmu_system_reset(u16 reset_code) 344static inline void prcmu_system_reset(u16 reset_code)
340{ 345{
341 return db8500_prcmu_system_reset(reset_code); 346 return db8500_prcmu_system_reset(reset_code);
@@ -507,6 +512,11 @@ static inline int prcmu_get_ape_opp(void)
507 return APE_100_OPP; 512 return APE_100_OPP;
508} 513}
509 514
515static inline int prcmu_request_ape_opp_100_voltage(bool enable)
516{
517 return 0;
518}
519
510static inline int prcmu_set_arm_opp(u8 opp) 520static inline int prcmu_set_arm_opp(u8 opp)
511{ 521{
512 return 0; 522 return 0;
diff --git a/include/linux/mfd/lp8788.h b/include/linux/mfd/lp8788.h
index cec364bdccfa..2a32b16f79cb 100644
--- a/include/linux/mfd/lp8788.h
+++ b/include/linux/mfd/lp8788.h
@@ -211,16 +211,16 @@ struct lp8788_chg_param {
211 211
212/* 212/*
213 * struct lp8788_charger_platform_data 213 * struct lp8788_charger_platform_data
214 * @vbatt_adc : adc selection id for battery voltage 214 * @adc_vbatt : adc channel name for battery voltage
215 * @batt_temp_adc : adc selection id for battery temperature 215 * @adc_batt_temp : adc channel name for battery temperature
216 * @max_vbatt_mv : used for calculating battery capacity 216 * @max_vbatt_mv : used for calculating battery capacity
217 * @chg_params : initial charging parameters 217 * @chg_params : initial charging parameters
218 * @num_chg_params : numbers of charging parameters 218 * @num_chg_params : numbers of charging parameters
219 * @charger_event : the charger event can be reported to the platform side 219 * @charger_event : the charger event can be reported to the platform side
220 */ 220 */
221struct lp8788_charger_platform_data { 221struct lp8788_charger_platform_data {
222 enum lp8788_adc_id vbatt_adc; 222 const char *adc_vbatt;
223 enum lp8788_adc_id batt_temp_adc; 223 const char *adc_batt_temp;
224 unsigned int max_vbatt_mv; 224 unsigned int max_vbatt_mv;
225 struct lp8788_chg_param *chg_params; 225 struct lp8788_chg_param *chg_params;
226 int num_chg_params; 226 int num_chg_params;
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 830152cfae33..6ae21bf47d64 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -316,6 +316,7 @@ enum max8997_irq {
316#define MAX8997_NUM_GPIO 12 316#define MAX8997_NUM_GPIO 12
317struct max8997_dev { 317struct max8997_dev {
318 struct device *dev; 318 struct device *dev;
319 struct max8997_platform_data *pdata;
319 struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */ 320 struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
320 struct i2c_client *rtc; /* slave addr 0x0c */ 321 struct i2c_client *rtc; /* slave addr 0x0c */
321 struct i2c_client *haptic; /* slave addr 0x90 */ 322 struct i2c_client *haptic; /* slave addr 0x90 */
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 328d8e24b533..1d4a4fe6ac33 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -75,6 +75,7 @@ enum max8998_regulators {
75struct max8997_regulator_data { 75struct max8997_regulator_data {
76 int id; 76 int id;
77 struct regulator_init_data *initdata; 77 struct regulator_init_data *initdata;
78 struct device_node *reg_node;
78}; 79};
79 80
80enum max8997_muic_usb_type { 81enum max8997_muic_usb_type {
diff --git a/include/linux/mfd/menelaus.h b/include/linux/mfd/menelaus.h
new file mode 100644
index 000000000000..f097e89134cb
--- /dev/null
+++ b/include/linux/mfd/menelaus.h
@@ -0,0 +1,47 @@
1/*
2 * Functions to access Menelaus power management chip
3 */
4
5#ifndef __ASM_ARCH_MENELAUS_H
6#define __ASM_ARCH_MENELAUS_H
7
8struct device;
9
10struct menelaus_platform_data {
11 int (* late_init)(struct device *dev);
12};
13
14extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
15 void *data);
16extern void menelaus_unregister_mmc_callback(void);
17extern int menelaus_set_mmc_opendrain(int slot, int enable);
18extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
19
20extern int menelaus_set_vmem(unsigned int mV);
21extern int menelaus_set_vio(unsigned int mV);
22extern int menelaus_set_vmmc(unsigned int mV);
23extern int menelaus_set_vaux(unsigned int mV);
24extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
25extern int menelaus_set_slot_sel(int enable);
26extern int menelaus_get_slot_pin_states(void);
27extern int menelaus_set_vcore_sw(unsigned int mV);
28extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
29
30#define EN_VPLL_SLEEP (1 << 7)
31#define EN_VMMC_SLEEP (1 << 6)
32#define EN_VAUX_SLEEP (1 << 5)
33#define EN_VIO_SLEEP (1 << 4)
34#define EN_VMEM_SLEEP (1 << 3)
35#define EN_DC3_SLEEP (1 << 2)
36#define EN_DC2_SLEEP (1 << 1)
37#define EN_VC_SLEEP (1 << 0)
38
39extern int menelaus_set_regulator_sleep(int enable, u32 val);
40
41#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
42#define omap_has_menelaus() 1
43#else
44#define omap_has_menelaus() 0
45#endif
46
47#endif
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
index 4b21769f4483..f83d6b43ecbb 100644
--- a/include/linux/mfd/pm8xxx/irq.h
+++ b/include/linux/mfd/pm8xxx/irq.h
@@ -37,21 +37,21 @@ struct pm_irq_chip;
37 37
38#ifdef CONFIG_MFD_PM8XXX_IRQ 38#ifdef CONFIG_MFD_PM8XXX_IRQ
39int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq); 39int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
40struct pm_irq_chip * __devinit pm8xxx_irq_init(struct device *dev, 40struct pm_irq_chip *pm8xxx_irq_init(struct device *dev,
41 const struct pm8xxx_irq_platform_data *pdata); 41 const struct pm8xxx_irq_platform_data *pdata);
42int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip); 42int pm8xxx_irq_exit(struct pm_irq_chip *chip);
43#else 43#else
44static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq) 44static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
45{ 45{
46 return -ENXIO; 46 return -ENXIO;
47} 47}
48static inline struct pm_irq_chip * __devinit pm8xxx_irq_init( 48static inline struct pm_irq_chip *pm8xxx_irq_init(
49 const struct device *dev, 49 const struct device *dev,
50 const struct pm8xxx_irq_platform_data *pdata) 50 const struct pm8xxx_irq_platform_data *pdata)
51{ 51{
52 return ERR_PTR(-ENXIO); 52 return ERR_PTR(-ENXIO);
53} 53}
54static inline int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip) 54static inline int pm8xxx_irq_exit(struct pm_irq_chip *chip)
55{ 55{
56 return -ENXIO; 56 return -ENXIO;
57} 57}
diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h
index 36c242e52ef1..fd413ccab915 100644
--- a/include/linux/mfd/rc5t583.h
+++ b/include/linux/mfd/rc5t583.h
@@ -33,6 +33,7 @@
33/* Maximum number of main interrupts */ 33/* Maximum number of main interrupts */
34#define MAX_MAIN_INTERRUPT 5 34#define MAX_MAIN_INTERRUPT 5
35#define RC5T583_MAX_GPEDGE_REG 2 35#define RC5T583_MAX_GPEDGE_REG 2
36#define RC5T583_MAX_INTERRUPT_EN_REGS 8
36#define RC5T583_MAX_INTERRUPT_MASK_REGS 9 37#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
37 38
38/* Interrupt enable register */ 39/* Interrupt enable register */
@@ -304,7 +305,7 @@ struct rc5t583 {
304 uint8_t intc_inten_reg; 305 uint8_t intc_inten_reg;
305 306
306 /* For group interrupt bits and address */ 307 /* For group interrupt bits and address */
307 uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS]; 308 uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_EN_REGS];
308 309
309 /* For gpio edge */ 310 /* For gpio edge */
310 uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG]; 311 uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
diff --git a/include/linux/mfd/retu.h b/include/linux/mfd/retu.h
new file mode 100644
index 000000000000..1e2715d5b836
--- /dev/null
+++ b/include/linux/mfd/retu.h
@@ -0,0 +1,22 @@
1/*
2 * Retu MFD driver interface
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of this
6 * archive for more details.
7 */
8
9#ifndef __LINUX_MFD_RETU_H
10#define __LINUX_MFD_RETU_H
11
12struct retu_dev;
13
14int retu_read(struct retu_dev *, u8);
15int retu_write(struct retu_dev *, u8, u16);
16
17/* Registers */
18#define RETU_REG_WATCHDOG 0x17 /* Watchdog */
19#define RETU_REG_CC1 0x0d /* Common control register 1 */
20#define RETU_REG_STATUS 0x16 /* Status register */
21
22#endif /* __LINUX_MFD_RETU_H */
diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h
new file mode 100644
index 000000000000..a8d393e3066b
--- /dev/null
+++ b/include/linux/mfd/rtsx_common.h
@@ -0,0 +1,48 @@
1/* Driver for Realtek driver-based card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#ifndef __RTSX_COMMON_H
24#define __RTSX_COMMON_H
25
26#define DRV_NAME_RTSX_PCI "rtsx_pci"
27#define DRV_NAME_RTSX_PCI_SDMMC "rtsx_pci_sdmmc"
28#define DRV_NAME_RTSX_PCI_MS "rtsx_pci_ms"
29
30#define RTSX_REG_PAIR(addr, val) (((u32)(addr) << 16) | (u8)(val))
31
32#define RTSX_SSC_DEPTH_4M 0x01
33#define RTSX_SSC_DEPTH_2M 0x02
34#define RTSX_SSC_DEPTH_1M 0x03
35#define RTSX_SSC_DEPTH_500K 0x04
36#define RTSX_SSC_DEPTH_250K 0x05
37
38#define RTSX_SD_CARD 0
39#define RTSX_MS_CARD 1
40
41struct platform_device;
42
43struct rtsx_slot {
44 struct platform_device *p_dev;
45 void (*card_event)(struct platform_device *p_dev);
46};
47
48#endif
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
new file mode 100644
index 000000000000..060b721fcbfb
--- /dev/null
+++ b/include/linux/mfd/rtsx_pci.h
@@ -0,0 +1,794 @@
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#ifndef __RTSX_PCI_H
24#define __RTSX_PCI_H
25
26#include <linux/sched.h>
27#include <linux/pci.h>
28
29#include "rtsx_common.h"
30
31#define MAX_RW_REG_CNT 1024
32
33/* PCI Operation Register Address */
34#define RTSX_HCBAR 0x00
35#define RTSX_HCBCTLR 0x04
36#define RTSX_HDBAR 0x08
37#define RTSX_HDBCTLR 0x0C
38#define RTSX_HAIMR 0x10
39#define RTSX_BIPR 0x14
40#define RTSX_BIER 0x18
41
42/* Host command buffer control register */
43#define STOP_CMD (0x01 << 28)
44
45/* Host data buffer control register */
46#define SDMA_MODE 0x00
47#define ADMA_MODE (0x02 << 26)
48#define STOP_DMA (0x01 << 28)
49#define TRIG_DMA (0x01 << 31)
50
51/* Host access internal memory register */
52#define HAIMR_TRANS_START (0x01 << 31)
53#define HAIMR_READ 0x00
54#define HAIMR_WRITE (0x01 << 30)
55#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
56#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
57#define HAIMR_TRANS_END (HAIMR_TRANS_START)
58
59/* Bus interrupt pending register */
60#define CMD_DONE_INT (1 << 31)
61#define DATA_DONE_INT (1 << 30)
62#define TRANS_OK_INT (1 << 29)
63#define TRANS_FAIL_INT (1 << 28)
64#define XD_INT (1 << 27)
65#define MS_INT (1 << 26)
66#define SD_INT (1 << 25)
67#define GPIO0_INT (1 << 24)
68#define OC_INT (1 << 23)
69#define SD_WRITE_PROTECT (1 << 19)
70#define XD_EXIST (1 << 18)
71#define MS_EXIST (1 << 17)
72#define SD_EXIST (1 << 16)
73#define DELINK_INT GPIO0_INT
74#define MS_OC_INT (1 << 23)
75#define SD_OC_INT (1 << 22)
76
77#define CARD_INT (XD_INT | MS_INT | SD_INT)
78#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
79#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
80 CARD_INT | GPIO0_INT | OC_INT)
81
82#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
83
84/* Bus interrupt enable register */
85#define CMD_DONE_INT_EN (1 << 31)
86#define DATA_DONE_INT_EN (1 << 30)
87#define TRANS_OK_INT_EN (1 << 29)
88#define TRANS_FAIL_INT_EN (1 << 28)
89#define XD_INT_EN (1 << 27)
90#define MS_INT_EN (1 << 26)
91#define SD_INT_EN (1 << 25)
92#define GPIO0_INT_EN (1 << 24)
93#define OC_INT_EN (1 << 23)
94#define DELINK_INT_EN GPIO0_INT_EN
95#define MS_OC_INT_EN (1 << 23)
96#define SD_OC_INT_EN (1 << 22)
97
98#define READ_REG_CMD 0
99#define WRITE_REG_CMD 1
100#define CHECK_REG_CMD 2
101
102/*
103 * macros for easy use
104 */
105#define rtsx_pci_writel(pcr, reg, value) \
106 iowrite32(value, (pcr)->remap_addr + reg)
107#define rtsx_pci_readl(pcr, reg) \
108 ioread32((pcr)->remap_addr + reg)
109#define rtsx_pci_writew(pcr, reg, value) \
110 iowrite16(value, (pcr)->remap_addr + reg)
111#define rtsx_pci_readw(pcr, reg) \
112 ioread16((pcr)->remap_addr + reg)
113#define rtsx_pci_writeb(pcr, reg, value) \
114 iowrite8(value, (pcr)->remap_addr + reg)
115#define rtsx_pci_readb(pcr, reg) \
116 ioread8((pcr)->remap_addr + reg)
117
118#define rtsx_pci_read_config_byte(pcr, where, val) \
119 pci_read_config_byte((pcr)->pci, where, val)
120
121#define rtsx_pci_write_config_byte(pcr, where, val) \
122 pci_write_config_byte((pcr)->pci, where, val)
123
124#define rtsx_pci_read_config_dword(pcr, where, val) \
125 pci_read_config_dword((pcr)->pci, where, val)
126
127#define rtsx_pci_write_config_dword(pcr, where, val) \
128 pci_write_config_dword((pcr)->pci, where, val)
129
130#define STATE_TRANS_NONE 0
131#define STATE_TRANS_CMD 1
132#define STATE_TRANS_BUF 2
133#define STATE_TRANS_SG 3
134
135#define TRANS_NOT_READY 0
136#define TRANS_RESULT_OK 1
137#define TRANS_RESULT_FAIL 2
138#define TRANS_NO_DEVICE 3
139
140#define RTSX_RESV_BUF_LEN 4096
141#define HOST_CMDS_BUF_LEN 1024
142#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
143#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
144#define MAX_SG_ITEM_LEN 0x80000
145
146#define HOST_TO_DEVICE 0
147#define DEVICE_TO_HOST 1
148
149#define MAX_PHASE 31
150#define RX_TUNING_CNT 3
151
152/* SG descriptor */
153#define SG_INT 0x04
154#define SG_END 0x02
155#define SG_VALID 0x01
156
157#define SG_NO_OP 0x00
158#define SG_TRANS_DATA (0x02 << 4)
159#define SG_LINK_DESC (0x03 << 4)
160
161/* SD bank voltage */
162#define SD_IO_3V3 0
163#define SD_IO_1V8 1
164
165
166/* Card Clock Enable Register */
167#define SD_CLK_EN 0x04
168#define MS_CLK_EN 0x08
169
170/* Card Select Register */
171#define SD_MOD_SEL 2
172#define MS_MOD_SEL 3
173
174/* Card Output Enable Register */
175#define SD_OUTPUT_EN 0x04
176#define MS_OUTPUT_EN 0x08
177
178/* CARD_SHARE_MODE */
179#define CARD_SHARE_MASK 0x0F
180#define CARD_SHARE_MULTI_LUN 0x00
181#define CARD_SHARE_NORMAL 0x00
182#define CARD_SHARE_48_SD 0x04
183#define CARD_SHARE_48_MS 0x08
184/* CARD_SHARE_MODE for barossa */
185#define CARD_SHARE_BAROSSA_SD 0x01
186#define CARD_SHARE_BAROSSA_MS 0x02
187
188/* SD30_DRIVE_SEL */
189#define DRIVER_TYPE_A 0x05
190#define DRIVER_TYPE_B 0x03
191#define DRIVER_TYPE_C 0x02
192#define DRIVER_TYPE_D 0x01
193
194/* FPDCTL */
195#define SSC_POWER_DOWN 0x01
196#define SD_OC_POWER_DOWN 0x02
197#define ALL_POWER_DOWN 0x07
198#define OC_POWER_DOWN 0x06
199
200/* CLK_CTL */
201#define CHANGE_CLK 0x01
202
203/* LDO_CTL */
204#define BPP_LDO_POWB 0x03
205#define BPP_LDO_ON 0x00
206#define BPP_LDO_SUSPEND 0x02
207#define BPP_LDO_OFF 0x03
208
209/* CD_PAD_CTL */
210#define CD_DISABLE_MASK 0x07
211#define MS_CD_DISABLE 0x04
212#define SD_CD_DISABLE 0x02
213#define XD_CD_DISABLE 0x01
214#define CD_DISABLE 0x07
215#define CD_ENABLE 0x00
216#define MS_CD_EN_ONLY 0x03
217#define SD_CD_EN_ONLY 0x05
218#define XD_CD_EN_ONLY 0x06
219#define FORCE_CD_LOW_MASK 0x38
220#define FORCE_CD_XD_LOW 0x08
221#define FORCE_CD_SD_LOW 0x10
222#define FORCE_CD_MS_LOW 0x20
223#define CD_AUTO_DISABLE 0x40
224
225/* SD_STAT1 */
226#define SD_CRC7_ERR 0x80
227#define SD_CRC16_ERR 0x40
228#define SD_CRC_WRITE_ERR 0x20
229#define SD_CRC_WRITE_ERR_MASK 0x1C
230#define GET_CRC_TIME_OUT 0x02
231#define SD_TUNING_COMPARE_ERR 0x01
232
233/* SD_STAT2 */
234#define SD_RSP_80CLK_TIMEOUT 0x01
235
236/* SD_BUS_STAT */
237#define SD_CLK_TOGGLE_EN 0x80
238#define SD_CLK_FORCE_STOP 0x40
239#define SD_DAT3_STATUS 0x10
240#define SD_DAT2_STATUS 0x08
241#define SD_DAT1_STATUS 0x04
242#define SD_DAT0_STATUS 0x02
243#define SD_CMD_STATUS 0x01
244
245/* SD_PAD_CTL */
246#define SD_IO_USING_1V8 0x80
247#define SD_IO_USING_3V3 0x7F
248#define TYPE_A_DRIVING 0x00
249#define TYPE_B_DRIVING 0x01
250#define TYPE_C_DRIVING 0x02
251#define TYPE_D_DRIVING 0x03
252
253/* SD_SAMPLE_POINT_CTL */
254#define DDR_FIX_RX_DAT 0x00
255#define DDR_VAR_RX_DAT 0x80
256#define DDR_FIX_RX_DAT_EDGE 0x00
257#define DDR_FIX_RX_DAT_14_DELAY 0x40
258#define DDR_FIX_RX_CMD 0x00
259#define DDR_VAR_RX_CMD 0x20
260#define DDR_FIX_RX_CMD_POS_EDGE 0x00
261#define DDR_FIX_RX_CMD_14_DELAY 0x10
262#define SD20_RX_POS_EDGE 0x00
263#define SD20_RX_14_DELAY 0x08
264#define SD20_RX_SEL_MASK 0x08
265
266/* SD_PUSH_POINT_CTL */
267#define DDR_FIX_TX_CMD_DAT 0x00
268#define DDR_VAR_TX_CMD_DAT 0x80
269#define DDR_FIX_TX_DAT_14_TSU 0x00
270#define DDR_FIX_TX_DAT_12_TSU 0x40
271#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
272#define DDR_FIX_TX_CMD_14_AHEAD 0x20
273#define SD20_TX_NEG_EDGE 0x00
274#define SD20_TX_14_AHEAD 0x10
275#define SD20_TX_SEL_MASK 0x10
276#define DDR_VAR_SDCLK_POL_SWAP 0x01
277
278/* SD_TRANSFER */
279#define SD_TRANSFER_START 0x80
280#define SD_TRANSFER_END 0x40
281#define SD_STAT_IDLE 0x20
282#define SD_TRANSFER_ERR 0x10
283/* SD Transfer Mode definition */
284#define SD_TM_NORMAL_WRITE 0x00
285#define SD_TM_AUTO_WRITE_3 0x01
286#define SD_TM_AUTO_WRITE_4 0x02
287#define SD_TM_AUTO_READ_3 0x05
288#define SD_TM_AUTO_READ_4 0x06
289#define SD_TM_CMD_RSP 0x08
290#define SD_TM_AUTO_WRITE_1 0x09
291#define SD_TM_AUTO_WRITE_2 0x0A
292#define SD_TM_NORMAL_READ 0x0C
293#define SD_TM_AUTO_READ_1 0x0D
294#define SD_TM_AUTO_READ_2 0x0E
295#define SD_TM_AUTO_TUNING 0x0F
296
297/* SD_VPTX_CTL / SD_VPRX_CTL */
298#define PHASE_CHANGE 0x80
299#define PHASE_NOT_RESET 0x40
300
301/* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
302#define DCMPS_CHANGE 0x80
303#define DCMPS_CHANGE_DONE 0x40
304#define DCMPS_ERROR 0x20
305#define DCMPS_CURRENT_PHASE 0x1F
306
307/* SD Configure 1 Register */
308#define SD_CLK_DIVIDE_0 0x00
309#define SD_CLK_DIVIDE_256 0xC0
310#define SD_CLK_DIVIDE_128 0x80
311#define SD_BUS_WIDTH_1BIT 0x00
312#define SD_BUS_WIDTH_4BIT 0x01
313#define SD_BUS_WIDTH_8BIT 0x02
314#define SD_ASYNC_FIFO_NOT_RST 0x10
315#define SD_20_MODE 0x00
316#define SD_DDR_MODE 0x04
317#define SD_30_MODE 0x08
318
319#define SD_CLK_DIVIDE_MASK 0xC0
320
321/* SD_CMD_STATE */
322#define SD_CMD_IDLE 0x80
323
324/* SD_DATA_STATE */
325#define SD_DATA_IDLE 0x80
326
327/* DCM_DRP_CTL */
328#define DCM_RESET 0x08
329#define DCM_LOCKED 0x04
330#define DCM_208M 0x00
331#define DCM_TX 0x01
332#define DCM_RX 0x02
333
334/* DCM_DRP_TRIG */
335#define DRP_START 0x80
336#define DRP_DONE 0x40
337
338/* DCM_DRP_CFG */
339#define DRP_WRITE 0x80
340#define DRP_READ 0x00
341#define DCM_WRITE_ADDRESS_50 0x50
342#define DCM_WRITE_ADDRESS_51 0x51
343#define DCM_READ_ADDRESS_00 0x00
344#define DCM_READ_ADDRESS_51 0x51
345
346/* IRQSTAT0 */
347#define DMA_DONE_INT 0x80
348#define SUSPEND_INT 0x40
349#define LINK_RDY_INT 0x20
350#define LINK_DOWN_INT 0x10
351
352/* DMACTL */
353#define DMA_RST 0x80
354#define DMA_BUSY 0x04
355#define DMA_DIR_TO_CARD 0x00
356#define DMA_DIR_FROM_CARD 0x02
357#define DMA_EN 0x01
358#define DMA_128 (0 << 4)
359#define DMA_256 (1 << 4)
360#define DMA_512 (2 << 4)
361#define DMA_1024 (3 << 4)
362#define DMA_PACK_SIZE_MASK 0x30
363
364/* SSC_CTL1 */
365#define SSC_RSTB 0x80
366#define SSC_8X_EN 0x40
367#define SSC_FIX_FRAC 0x20
368#define SSC_SEL_1M 0x00
369#define SSC_SEL_2M 0x08
370#define SSC_SEL_4M 0x10
371#define SSC_SEL_8M 0x18
372
373/* SSC_CTL2 */
374#define SSC_DEPTH_MASK 0x07
375#define SSC_DEPTH_DISALBE 0x00
376#define SSC_DEPTH_4M 0x01
377#define SSC_DEPTH_2M 0x02
378#define SSC_DEPTH_1M 0x03
379#define SSC_DEPTH_500K 0x04
380#define SSC_DEPTH_250K 0x05
381
382/* System Clock Control Register */
383#define CLK_LOW_FREQ 0x01
384
385/* System Clock Divider Register */
386#define CLK_DIV_1 0x01
387#define CLK_DIV_2 0x02
388#define CLK_DIV_4 0x03
389#define CLK_DIV_8 0x04
390
391/* MS_CFG */
392#define SAMPLE_TIME_RISING 0x00
393#define SAMPLE_TIME_FALLING 0x80
394#define PUSH_TIME_DEFAULT 0x00
395#define PUSH_TIME_ODD 0x40
396#define NO_EXTEND_TOGGLE 0x00
397#define EXTEND_TOGGLE_CHK 0x20
398#define MS_BUS_WIDTH_1 0x00
399#define MS_BUS_WIDTH_4 0x10
400#define MS_BUS_WIDTH_8 0x18
401#define MS_2K_SECTOR_MODE 0x04
402#define MS_512_SECTOR_MODE 0x00
403#define MS_TOGGLE_TIMEOUT_EN 0x00
404#define MS_TOGGLE_TIMEOUT_DISEN 0x01
405#define MS_NO_CHECK_INT 0x02
406
407/* MS_TRANS_CFG */
408#define WAIT_INT 0x80
409#define NO_WAIT_INT 0x00
410#define NO_AUTO_READ_INT_REG 0x00
411#define AUTO_READ_INT_REG 0x40
412#define MS_CRC16_ERR 0x20
413#define MS_RDY_TIMEOUT 0x10
414#define MS_INT_CMDNK 0x08
415#define MS_INT_BREQ 0x04
416#define MS_INT_ERR 0x02
417#define MS_INT_CED 0x01
418
419/* MS_TRANSFER */
420#define MS_TRANSFER_START 0x80
421#define MS_TRANSFER_END 0x40
422#define MS_TRANSFER_ERR 0x20
423#define MS_BS_STATE 0x10
424#define MS_TM_READ_BYTES 0x00
425#define MS_TM_NORMAL_READ 0x01
426#define MS_TM_WRITE_BYTES 0x04
427#define MS_TM_NORMAL_WRITE 0x05
428#define MS_TM_AUTO_READ 0x08
429#define MS_TM_AUTO_WRITE 0x0C
430
431/* SD Configure 2 Register */
432#define SD_CALCULATE_CRC7 0x00
433#define SD_NO_CALCULATE_CRC7 0x80
434#define SD_CHECK_CRC16 0x00
435#define SD_NO_CHECK_CRC16 0x40
436#define SD_NO_CHECK_WAIT_CRC_TO 0x20
437#define SD_WAIT_BUSY_END 0x08
438#define SD_NO_WAIT_BUSY_END 0x00
439#define SD_CHECK_CRC7 0x00
440#define SD_NO_CHECK_CRC7 0x04
441#define SD_RSP_LEN_0 0x00
442#define SD_RSP_LEN_6 0x01
443#define SD_RSP_LEN_17 0x02
444/* SD/MMC Response Type Definition */
445#define SD_RSP_TYPE_R0 0x04
446#define SD_RSP_TYPE_R1 0x01
447#define SD_RSP_TYPE_R1b 0x09
448#define SD_RSP_TYPE_R2 0x02
449#define SD_RSP_TYPE_R3 0x05
450#define SD_RSP_TYPE_R4 0x05
451#define SD_RSP_TYPE_R5 0x01
452#define SD_RSP_TYPE_R6 0x01
453#define SD_RSP_TYPE_R7 0x01
454
455/* SD_CONFIURE3 */
456#define SD_RSP_80CLK_TIMEOUT_EN 0x01
457
458/* Card Transfer Reset Register */
459#define SPI_STOP 0x01
460#define XD_STOP 0x02
461#define SD_STOP 0x04
462#define MS_STOP 0x08
463#define SPI_CLR_ERR 0x10
464#define XD_CLR_ERR 0x20
465#define SD_CLR_ERR 0x40
466#define MS_CLR_ERR 0x80
467
468/* Card Data Source Register */
469#define PINGPONG_BUFFER 0x01
470#define RING_BUFFER 0x00
471
472/* Card Power Control Register */
473#define PMOS_STRG_MASK 0x10
474#define PMOS_STRG_800mA 0x10
475#define PMOS_STRG_400mA 0x00
476#define SD_POWER_OFF 0x03
477#define SD_PARTIAL_POWER_ON 0x01
478#define SD_POWER_ON 0x00
479#define SD_POWER_MASK 0x03
480#define MS_POWER_OFF 0x0C
481#define MS_PARTIAL_POWER_ON 0x04
482#define MS_POWER_ON 0x00
483#define MS_POWER_MASK 0x0C
484#define BPP_POWER_OFF 0x0F
485#define BPP_POWER_5_PERCENT_ON 0x0E
486#define BPP_POWER_10_PERCENT_ON 0x0C
487#define BPP_POWER_15_PERCENT_ON 0x08
488#define BPP_POWER_ON 0x00
489#define BPP_POWER_MASK 0x0F
490
491/* PWR_GATE_CTRL */
492#define PWR_GATE_EN 0x01
493#define LDO3318_PWR_MASK 0x06
494#define LDO_ON 0x00
495#define LDO_SUSPEND 0x04
496#define LDO_OFF 0x06
497
498/* CARD_CLK_SOURCE */
499#define CRC_FIX_CLK (0x00 << 0)
500#define CRC_VAR_CLK0 (0x01 << 0)
501#define CRC_VAR_CLK1 (0x02 << 0)
502#define SD30_FIX_CLK (0x00 << 2)
503#define SD30_VAR_CLK0 (0x01 << 2)
504#define SD30_VAR_CLK1 (0x02 << 2)
505#define SAMPLE_FIX_CLK (0x00 << 4)
506#define SAMPLE_VAR_CLK0 (0x01 << 4)
507#define SAMPLE_VAR_CLK1 (0x02 << 4)
508
509#define MS_CFG 0xFD40
510#define MS_TPC 0xFD41
511#define MS_TRANS_CFG 0xFD42
512#define MS_TRANSFER 0xFD43
513#define MS_INT_REG 0xFD44
514#define MS_BYTE_CNT 0xFD45
515#define MS_SECTOR_CNT_L 0xFD46
516#define MS_SECTOR_CNT_H 0xFD47
517#define MS_DBUS_H 0xFD48
518
519#define SD_CFG1 0xFDA0
520#define SD_CFG2 0xFDA1
521#define SD_CFG3 0xFDA2
522#define SD_STAT1 0xFDA3
523#define SD_STAT2 0xFDA4
524#define SD_BUS_STAT 0xFDA5
525#define SD_PAD_CTL 0xFDA6
526#define SD_SAMPLE_POINT_CTL 0xFDA7
527#define SD_PUSH_POINT_CTL 0xFDA8
528#define SD_CMD0 0xFDA9
529#define SD_CMD1 0xFDAA
530#define SD_CMD2 0xFDAB
531#define SD_CMD3 0xFDAC
532#define SD_CMD4 0xFDAD
533#define SD_CMD5 0xFDAE
534#define SD_BYTE_CNT_L 0xFDAF
535#define SD_BYTE_CNT_H 0xFDB0
536#define SD_BLOCK_CNT_L 0xFDB1
537#define SD_BLOCK_CNT_H 0xFDB2
538#define SD_TRANSFER 0xFDB3
539#define SD_CMD_STATE 0xFDB5
540#define SD_DATA_STATE 0xFDB6
541
542#define SRCTL 0xFC13
543
544#define DCM_DRP_CTL 0xFC23
545#define DCM_DRP_TRIG 0xFC24
546#define DCM_DRP_CFG 0xFC25
547#define DCM_DRP_WR_DATA_L 0xFC26
548#define DCM_DRP_WR_DATA_H 0xFC27
549#define DCM_DRP_RD_DATA_L 0xFC28
550#define DCM_DRP_RD_DATA_H 0xFC29
551#define SD_VPCLK0_CTL 0xFC2A
552#define SD_VPCLK1_CTL 0xFC2B
553#define SD_DCMPS0_CTL 0xFC2C
554#define SD_DCMPS1_CTL 0xFC2D
555#define SD_VPTX_CTL SD_VPCLK0_CTL
556#define SD_VPRX_CTL SD_VPCLK1_CTL
557#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
558#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
559#define CARD_CLK_SOURCE 0xFC2E
560
561#define CARD_PWR_CTL 0xFD50
562#define CARD_CLK_SWITCH 0xFD51
563#define CARD_SHARE_MODE 0xFD52
564#define CARD_DRIVE_SEL 0xFD53
565#define CARD_STOP 0xFD54
566#define CARD_OE 0xFD55
567#define CARD_AUTO_BLINK 0xFD56
568#define CARD_GPIO_DIR 0xFD57
569#define CARD_GPIO 0xFD58
570#define CARD_DATA_SOURCE 0xFD5B
571#define CARD_SELECT 0xFD5C
572#define SD30_DRIVE_SEL 0xFD5E
573#define CARD_CLK_EN 0xFD69
574#define SDIO_CTRL 0xFD6B
575#define CD_PAD_CTL 0xFD73
576
577#define FPDCTL 0xFC00
578#define PDINFO 0xFC01
579
580#define CLK_CTL 0xFC02
581#define CLK_DIV 0xFC03
582#define CLK_SEL 0xFC04
583
584#define SSC_DIV_N_0 0xFC0F
585#define SSC_DIV_N_1 0xFC10
586#define SSC_CTL1 0xFC11
587#define SSC_CTL2 0xFC12
588
589#define RCCTL 0xFC14
590
591#define FPGA_PULL_CTL 0xFC1D
592#define OLT_LED_CTL 0xFC1E
593#define GPIO_CTL 0xFC1F
594
595#define LDO_CTL 0xFC1E
596#define SYS_VER 0xFC32
597
598#define CARD_PULL_CTL1 0xFD60
599#define CARD_PULL_CTL2 0xFD61
600#define CARD_PULL_CTL3 0xFD62
601#define CARD_PULL_CTL4 0xFD63
602#define CARD_PULL_CTL5 0xFD64
603#define CARD_PULL_CTL6 0xFD65
604
605/* PCI Express Related Registers */
606#define IRQEN0 0xFE20
607#define IRQSTAT0 0xFE21
608#define IRQEN1 0xFE22
609#define IRQSTAT1 0xFE23
610#define TLPRIEN 0xFE24
611#define TLPRISTAT 0xFE25
612#define TLPTIEN 0xFE26
613#define TLPTISTAT 0xFE27
614#define DMATC0 0xFE28
615#define DMATC1 0xFE29
616#define DMATC2 0xFE2A
617#define DMATC3 0xFE2B
618#define DMACTL 0xFE2C
619#define BCTL 0xFE2D
620#define RBBC0 0xFE2E
621#define RBBC1 0xFE2F
622#define RBDAT 0xFE30
623#define RBCTL 0xFE34
624#define CFGADDR0 0xFE35
625#define CFGADDR1 0xFE36
626#define CFGDATA0 0xFE37
627#define CFGDATA1 0xFE38
628#define CFGDATA2 0xFE39
629#define CFGDATA3 0xFE3A
630#define CFGRWCTL 0xFE3B
631#define PHYRWCTL 0xFE3C
632#define PHYDATA0 0xFE3D
633#define PHYDATA1 0xFE3E
634#define PHYADDR 0xFE3F
635#define MSGRXDATA0 0xFE40
636#define MSGRXDATA1 0xFE41
637#define MSGRXDATA2 0xFE42
638#define MSGRXDATA3 0xFE43
639#define MSGTXDATA0 0xFE44
640#define MSGTXDATA1 0xFE45
641#define MSGTXDATA2 0xFE46
642#define MSGTXDATA3 0xFE47
643#define MSGTXCTL 0xFE48
644#define PETXCFG 0xFE49
645
646#define CDRESUMECTL 0xFE52
647#define WAKE_SEL_CTL 0xFE54
648#define PME_FORCE_CTL 0xFE56
649#define ASPM_FORCE_CTL 0xFE57
650#define PM_CLK_FORCE_CTL 0xFE58
651#define PERST_GLITCH_WIDTH 0xFE5C
652#define CHANGE_LINK_STATE 0xFE5B
653#define RESET_LOAD_REG 0xFE5E
654#define EFUSE_CONTENT 0xFE5F
655#define HOST_SLEEP_STATE 0xFE60
656#define SDIO_CFG 0xFE70
657
658#define NFTS_TX_CTRL 0xFE72
659
660#define PWR_GATE_CTRL 0xFE75
661#define PWD_SUSPEND_EN 0xFE76
662#define LDO_PWR_SEL 0xFE78
663
664#define DUMMY_REG_RESET_0 0xFE90
665
666/* Memory mapping */
667#define SRAM_BASE 0xE600
668#define RBUF_BASE 0xF400
669#define PPBUF_BASE1 0xF800
670#define PPBUF_BASE2 0xFA00
671#define IMAGE_FLAG_ADDR0 0xCE80
672#define IMAGE_FLAG_ADDR1 0xCE81
673
674#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
675
676struct rtsx_pcr;
677
678struct pcr_handle {
679 struct rtsx_pcr *pcr;
680};
681
682struct pcr_ops {
683 int (*extra_init_hw)(struct rtsx_pcr *pcr);
684 int (*optimize_phy)(struct rtsx_pcr *pcr);
685 int (*turn_on_led)(struct rtsx_pcr *pcr);
686 int (*turn_off_led)(struct rtsx_pcr *pcr);
687 int (*enable_auto_blink)(struct rtsx_pcr *pcr);
688 int (*disable_auto_blink)(struct rtsx_pcr *pcr);
689 int (*card_power_on)(struct rtsx_pcr *pcr, int card);
690 int (*card_power_off)(struct rtsx_pcr *pcr, int card);
691 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
692};
693
694enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
695
696struct rtsx_pcr {
697 struct pci_dev *pci;
698 unsigned int id;
699
700 /* pci resources */
701 unsigned long addr;
702 void __iomem *remap_addr;
703 int irq;
704
705 /* host reserved buffer */
706 void *rtsx_resv_buf;
707 dma_addr_t rtsx_resv_buf_addr;
708
709 void *host_cmds_ptr;
710 dma_addr_t host_cmds_addr;
711 int ci;
712
713 void *host_sg_tbl_ptr;
714 dma_addr_t host_sg_tbl_addr;
715 int sgi;
716
717 u32 bier;
718 char trans_result;
719
720 unsigned int card_inserted;
721 unsigned int card_removed;
722
723 struct delayed_work carddet_work;
724 struct delayed_work idle_work;
725
726 spinlock_t lock;
727 struct mutex pcr_mutex;
728 struct completion *done;
729 struct completion *finish_me;
730
731 unsigned int cur_clock;
732 bool ms_pmos;
733 bool remove_pci;
734 bool msi_en;
735
736#define EXTRA_CAPS_SD_SDR50 (1 << 0)
737#define EXTRA_CAPS_SD_SDR104 (1 << 1)
738#define EXTRA_CAPS_SD_DDR50 (1 << 2)
739#define EXTRA_CAPS_MMC_HSDDR (1 << 3)
740#define EXTRA_CAPS_MMC_HS200 (1 << 4)
741#define EXTRA_CAPS_MMC_8BIT (1 << 5)
742 u32 extra_caps;
743
744#define IC_VER_A 0
745#define IC_VER_B 1
746#define IC_VER_C 2
747#define IC_VER_D 3
748 u8 ic_version;
749
750 const u32 *sd_pull_ctl_enable_tbl;
751 const u32 *sd_pull_ctl_disable_tbl;
752 const u32 *ms_pull_ctl_enable_tbl;
753 const u32 *ms_pull_ctl_disable_tbl;
754
755 const struct pcr_ops *ops;
756 enum PDEV_STAT state;
757
758 int num_slots;
759 struct rtsx_slot *slots;
760};
761
762#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
763#define PCI_VID(pcr) ((pcr)->pci->vendor)
764#define PCI_PID(pcr) ((pcr)->pci->device)
765
766void rtsx_pci_start_run(struct rtsx_pcr *pcr);
767int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
768int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
769int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
770int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
771void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
772void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
773 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
774void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
775int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
776int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
777 int num_sg, bool read, int timeout);
778int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
779int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
780int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
781int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
782int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
783 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
784int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
785int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
786unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
787void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
788
789static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
790{
791 return (u8 *)(pcr->host_cmds_ptr);
792}
793
794#endif
diff --git a/include/linux/mfd/sta2x11-mfd.h b/include/linux/mfd/sta2x11-mfd.h
index d179227e866f..9a855ac11cbf 100644
--- a/include/linux/mfd/sta2x11-mfd.h
+++ b/include/linux/mfd/sta2x11-mfd.h
@@ -26,6 +26,28 @@
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/pci.h> 27#include <linux/pci.h>
28 28
29enum sta2x11_mfd_plat_dev {
30 sta2x11_sctl = 0,
31 sta2x11_gpio,
32 sta2x11_scr,
33 sta2x11_time,
34 sta2x11_apbreg,
35 sta2x11_apb_soc_regs,
36 sta2x11_vic,
37 sta2x11_n_mfd_plat_devs,
38};
39
40#define STA2X11_MFD_SCTL_NAME "sta2x11-sctl"
41#define STA2X11_MFD_GPIO_NAME "sta2x11-gpio"
42#define STA2X11_MFD_SCR_NAME "sta2x11-scr"
43#define STA2X11_MFD_TIME_NAME "sta2x11-time"
44#define STA2X11_MFD_APBREG_NAME "sta2x11-apbreg"
45#define STA2X11_MFD_APB_SOC_REGS_NAME "sta2x11-apb-soc-regs"
46#define STA2X11_MFD_VIC_NAME "sta2x11-vic"
47
48extern u32
49__sta2x11_mfd_mask(struct pci_dev *, u32, u32, u32, enum sta2x11_mfd_plat_dev);
50
29/* 51/*
30 * The MFD PCI block includes the GPIO peripherals and other register blocks. 52 * The MFD PCI block includes the GPIO peripherals and other register blocks.
31 * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".) 53 * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
@@ -182,7 +204,11 @@ struct sta2x11_gpio_pdata {
182 * The APB bridge has its own registers, needed by our users as well. 204 * The APB bridge has its own registers, needed by our users as well.
183 * They are accessed with the following read/mask/write function. 205 * They are accessed with the following read/mask/write function.
184 */ 206 */
185u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val); 207static inline u32
208sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
209{
210 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg);
211}
186 212
187/* CAN and MLB */ 213/* CAN and MLB */
188#define APBREG_BSR 0x00 /* Bridge Status Reg */ 214#define APBREG_BSR 0x00 /* Bridge Status Reg */
@@ -211,19 +237,45 @@ u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
211 * The system controller has its own registers. Some of these are accessed 237 * The system controller has its own registers. Some of these are accessed
212 * by out users as well, using the following read/mask/write/function 238 * by out users as well, using the following read/mask/write/function
213 */ 239 */
214u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val); 240static inline
241u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
242{
243 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl);
244}
215 245
216#define SCTL_SCCTL 0x00 /* System controller control register */ 246#define SCTL_SCCTL 0x00 /* System controller control register */
217#define SCTL_ARMCFG 0x04 /* ARM configuration register */ 247#define SCTL_ARMCFG 0x04 /* ARM configuration register */
218#define SCTL_SCPLLCTL 0x08 /* PLL control status register */ 248#define SCTL_SCPLLCTL 0x08 /* PLL control status register */
249
250#define SCTL_SCPLLCTL_AUDIO_PLL_PD BIT(1)
251#define SCTL_SCPLLCTL_FRAC_CONTROL BIT(3)
252#define SCTL_SCPLLCTL_STRB_BYPASS BIT(6)
253#define SCTL_SCPLLCTL_STRB_INPUT BIT(8)
254
219#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */ 255#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */
256
257#define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_MASK 0xff
258#define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_SHIFT 10
259#define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_MASK 7
260#define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_SHIFT 21
261#define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_MASK 7
262#define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_SHIFT 18
263#define SCTL_SCPLLFCTRL_DITHER_DISABLE_MASK 0x03
264#define SCTL_SCPLLFCTRL_DITHER_DISABLE_SHIFT 4
265
266
220#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */ 267#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */
268
269#define SCTL_SCRESFRACT_MASK 0x0000ffff
270
271
221#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */ 272#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */
222#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */ 273#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */
223#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */ 274#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */
224#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */ 275#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
225#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */ 276#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
226#define SCTL_SCGRST 0x28 /* Peripheral global reset */ 277#define SCTL_SCGRST 0x28 /* Peripheral global reset */
278#define SCTL_SCPCIECSBRST 0x2c /* PCIe PAB CSB reset status register */
227#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */ 279#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */
228#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */ 280#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */
229#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */ 281#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */
@@ -321,4 +373,146 @@ u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
321#define SCTL_SCPEREN1_I2C3 (1 << 16) 373#define SCTL_SCPEREN1_I2C3 (1 << 16)
322#define SCTL_SCPEREN1_USB_PHY (1 << 17) 374#define SCTL_SCPEREN1_USB_PHY (1 << 17)
323 375
376/*
377 * APB-SOC registers
378 */
379static inline
380u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
381{
382 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs);
383}
384
385#define PCIE_EP1_FUNC3_0_INTR_REG 0x000
386#define PCIE_EP1_FUNC7_4_INTR_REG 0x004
387#define PCIE_EP2_FUNC3_0_INTR_REG 0x008
388#define PCIE_EP2_FUNC7_4_INTR_REG 0x00c
389#define PCIE_EP3_FUNC3_0_INTR_REG 0x010
390#define PCIE_EP3_FUNC7_4_INTR_REG 0x014
391#define PCIE_EP4_FUNC3_0_INTR_REG 0x018
392#define PCIE_EP4_FUNC7_4_INTR_REG 0x01c
393#define PCIE_INTR_ENABLE0_REG 0x020
394#define PCIE_INTR_ENABLE1_REG 0x024
395#define PCIE_EP1_FUNC_TC_REG 0x028
396#define PCIE_EP2_FUNC_TC_REG 0x02c
397#define PCIE_EP3_FUNC_TC_REG 0x030
398#define PCIE_EP4_FUNC_TC_REG 0x034
399#define PCIE_EP1_FUNC_F_REG 0x038
400#define PCIE_EP2_FUNC_F_REG 0x03c
401#define PCIE_EP3_FUNC_F_REG 0x040
402#define PCIE_EP4_FUNC_F_REG 0x044
403#define PCIE_PAB_AMBA_SW_RST_REG 0x048
404#define PCIE_PM_STATUS_0_PORT_0_4 0x04c
405#define PCIE_PM_STATUS_7_0_EP1 0x050
406#define PCIE_PM_STATUS_7_0_EP2 0x054
407#define PCIE_PM_STATUS_7_0_EP3 0x058
408#define PCIE_PM_STATUS_7_0_EP4 0x05c
409#define PCIE_DEV_ID_0_EP1_REG 0x060
410#define PCIE_CC_REV_ID_0_EP1_REG 0x064
411#define PCIE_DEV_ID_1_EP1_REG 0x068
412#define PCIE_CC_REV_ID_1_EP1_REG 0x06c
413#define PCIE_DEV_ID_2_EP1_REG 0x070
414#define PCIE_CC_REV_ID_2_EP1_REG 0x074
415#define PCIE_DEV_ID_3_EP1_REG 0x078
416#define PCIE_CC_REV_ID_3_EP1_REG 0x07c
417#define PCIE_DEV_ID_4_EP1_REG 0x080
418#define PCIE_CC_REV_ID_4_EP1_REG 0x084
419#define PCIE_DEV_ID_5_EP1_REG 0x088
420#define PCIE_CC_REV_ID_5_EP1_REG 0x08c
421#define PCIE_DEV_ID_6_EP1_REG 0x090
422#define PCIE_CC_REV_ID_6_EP1_REG 0x094
423#define PCIE_DEV_ID_7_EP1_REG 0x098
424#define PCIE_CC_REV_ID_7_EP1_REG 0x09c
425#define PCIE_DEV_ID_0_EP2_REG 0x0a0
426#define PCIE_CC_REV_ID_0_EP2_REG 0x0a4
427#define PCIE_DEV_ID_1_EP2_REG 0x0a8
428#define PCIE_CC_REV_ID_1_EP2_REG 0x0ac
429#define PCIE_DEV_ID_2_EP2_REG 0x0b0
430#define PCIE_CC_REV_ID_2_EP2_REG 0x0b4
431#define PCIE_DEV_ID_3_EP2_REG 0x0b8
432#define PCIE_CC_REV_ID_3_EP2_REG 0x0bc
433#define PCIE_DEV_ID_4_EP2_REG 0x0c0
434#define PCIE_CC_REV_ID_4_EP2_REG 0x0c4
435#define PCIE_DEV_ID_5_EP2_REG 0x0c8
436#define PCIE_CC_REV_ID_5_EP2_REG 0x0cc
437#define PCIE_DEV_ID_6_EP2_REG 0x0d0
438#define PCIE_CC_REV_ID_6_EP2_REG 0x0d4
439#define PCIE_DEV_ID_7_EP2_REG 0x0d8
440#define PCIE_CC_REV_ID_7_EP2_REG 0x0dC
441#define PCIE_DEV_ID_0_EP3_REG 0x0e0
442#define PCIE_CC_REV_ID_0_EP3_REG 0x0e4
443#define PCIE_DEV_ID_1_EP3_REG 0x0e8
444#define PCIE_CC_REV_ID_1_EP3_REG 0x0ec
445#define PCIE_DEV_ID_2_EP3_REG 0x0f0
446#define PCIE_CC_REV_ID_2_EP3_REG 0x0f4
447#define PCIE_DEV_ID_3_EP3_REG 0x0f8
448#define PCIE_CC_REV_ID_3_EP3_REG 0x0fc
449#define PCIE_DEV_ID_4_EP3_REG 0x100
450#define PCIE_CC_REV_ID_4_EP3_REG 0x104
451#define PCIE_DEV_ID_5_EP3_REG 0x108
452#define PCIE_CC_REV_ID_5_EP3_REG 0x10c
453#define PCIE_DEV_ID_6_EP3_REG 0x110
454#define PCIE_CC_REV_ID_6_EP3_REG 0x114
455#define PCIE_DEV_ID_7_EP3_REG 0x118
456#define PCIE_CC_REV_ID_7_EP3_REG 0x11c
457#define PCIE_DEV_ID_0_EP4_REG 0x120
458#define PCIE_CC_REV_ID_0_EP4_REG 0x124
459#define PCIE_DEV_ID_1_EP4_REG 0x128
460#define PCIE_CC_REV_ID_1_EP4_REG 0x12c
461#define PCIE_DEV_ID_2_EP4_REG 0x130
462#define PCIE_CC_REV_ID_2_EP4_REG 0x134
463#define PCIE_DEV_ID_3_EP4_REG 0x138
464#define PCIE_CC_REV_ID_3_EP4_REG 0x13c
465#define PCIE_DEV_ID_4_EP4_REG 0x140
466#define PCIE_CC_REV_ID_4_EP4_REG 0x144
467#define PCIE_DEV_ID_5_EP4_REG 0x148
468#define PCIE_CC_REV_ID_5_EP4_REG 0x14c
469#define PCIE_DEV_ID_6_EP4_REG 0x150
470#define PCIE_CC_REV_ID_6_EP4_REG 0x154
471#define PCIE_DEV_ID_7_EP4_REG 0x158
472#define PCIE_CC_REV_ID_7_EP4_REG 0x15c
473#define PCIE_SUBSYS_VEN_ID_REG 0x160
474#define PCIE_COMMON_CLOCK_CONFIG_0_4_0 0x164
475#define PCIE_MIPHYP_SSC_EN_REG 0x168
476#define PCIE_MIPHYP_ADDR_REG 0x16c
477#define PCIE_L1_ASPM_READY_REG 0x170
478#define PCIE_EXT_CFG_RDY_REG 0x174
479#define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178
480#define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c
481#define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180
482#define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184
483#define DMA_IP_CTRL_REG 0x324
484#define DISP_BRIDGE_PU_PD_CTRL_REG 0x328
485#define VIP_PU_PD_CTRL_REG 0x32c
486#define USB_MLB_PU_PD_CTRL_REG 0x330
487#define SDIO_PU_PD_MISCFUNC_CTRL_REG1 0x334
488#define SDIO_PU_PD_MISCFUNC_CTRL_REG2 0x338
489#define UART_PU_PD_CTRL_REG 0x33c
490#define ARM_Lock 0x340
491#define SYS_IO_CHAR_REG1 0x344
492#define SYS_IO_CHAR_REG2 0x348
493#define SATA_CORE_ID_REG 0x34c
494#define SATA_CTRL_REG 0x350
495#define I2C_HSFIX_MISC_REG 0x354
496#define SPARE2_RESERVED 0x358
497#define SPARE3_RESERVED 0x35c
498#define MASTER_LOCK_REG 0x368
499#define SYSTEM_CONFIG_STATUS_REG 0x36c
500#define MSP_CLK_CTRL_REG 0x39c
501#define COMPENSATION_REG1 0x3c4
502#define COMPENSATION_REG2 0x3c8
503#define COMPENSATION_REG3 0x3cc
504#define TEST_CTL_REG 0x3d0
505
506/*
507 * SECR (OTP) registers
508 */
509#define STA2X11_SECR_CR 0x00
510#define STA2X11_SECR_FVR0 0x10
511#define STA2X11_SECR_FVR1 0x14
512
513extern int sta2x11_mfd_get_regs_data(struct platform_device *pdev,
514 enum sta2x11_mfd_plat_dev index,
515 void __iomem **regs,
516 spinlock_t **lock);
517
324#endif /* __STA2X11_MFD_H */ 518#endif /* __STA2X11_MFD_H */
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index f8d5b4d5843f..383ac1512a39 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -62,6 +62,7 @@ struct stmpe_client_info;
62 * @lock: lock protecting I/O operations 62 * @lock: lock protecting I/O operations
63 * @irq_lock: IRQ bus lock 63 * @irq_lock: IRQ bus lock
64 * @dev: device, mostly for dev_dbg() 64 * @dev: device, mostly for dev_dbg()
65 * @irq_domain: IRQ domain
65 * @client: client - i2c or spi 66 * @client: client - i2c or spi
66 * @ci: client specific information 67 * @ci: client specific information
67 * @partnum: part number 68 * @partnum: part number
@@ -79,6 +80,7 @@ struct stmpe {
79 struct mutex lock; 80 struct mutex lock;
80 struct mutex irq_lock; 81 struct mutex irq_lock;
81 struct device *dev; 82 struct device *dev;
83 struct irq_domain *domain;
82 void *client; 84 void *client;
83 struct stmpe_client_info *ci; 85 struct stmpe_client_info *ci;
84 enum stmpe_partnum partnum; 86 enum stmpe_partnum partnum;
@@ -188,7 +190,6 @@ struct stmpe_ts_platform_data {
188 * @id: device id to distinguish between multiple STMPEs on the same board 190 * @id: device id to distinguish between multiple STMPEs on the same board
189 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) 191 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
190 * @irq_trigger: IRQ trigger to use for the interrupt to the host 192 * @irq_trigger: IRQ trigger to use for the interrupt to the host
191 * @irq_invert_polarity: IRQ line is connected with reversed polarity
192 * @autosleep: bool to enable/disable stmpe autosleep 193 * @autosleep: bool to enable/disable stmpe autosleep
193 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 194 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
194 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or 195 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
@@ -205,7 +206,6 @@ struct stmpe_platform_data {
205 unsigned int blocks; 206 unsigned int blocks;
206 int irq_base; 207 int irq_base;
207 unsigned int irq_trigger; 208 unsigned int irq_trigger;
208 bool irq_invert_polarity;
209 bool autosleep; 209 bool autosleep;
210 bool irq_over_gpio; 210 bool irq_over_gpio;
211 int irq_gpio; 211 int irq_gpio;
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
new file mode 100644
index 000000000000..c79ad5d2f271
--- /dev/null
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -0,0 +1,152 @@
1#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
2#define __LINUX_TI_AM335X_TSCADC_MFD_H
3
4/*
5 * TI Touch Screen / ADC MFD driver
6 *
7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mfd/core.h>
20
21#define REG_RAWIRQSTATUS 0x024
22#define REG_IRQSTATUS 0x028
23#define REG_IRQENABLE 0x02C
24#define REG_IRQCLR 0x030
25#define REG_IRQWAKEUP 0x034
26#define REG_CTRL 0x040
27#define REG_ADCFSM 0x044
28#define REG_CLKDIV 0x04C
29#define REG_SE 0x054
30#define REG_IDLECONFIG 0x058
31#define REG_CHARGECONFIG 0x05C
32#define REG_CHARGEDELAY 0x060
33#define REG_STEPCONFIG(n) (0x64 + ((n - 1) * 8))
34#define REG_STEPDELAY(n) (0x68 + ((n - 1) * 8))
35#define REG_FIFO0CNT 0xE4
36#define REG_FIFO0THR 0xE8
37#define REG_FIFO1CNT 0xF0
38#define REG_FIFO1THR 0xF4
39#define REG_FIFO0 0x100
40#define REG_FIFO1 0x200
41
42/* Register Bitfields */
43/* IRQ wakeup enable */
44#define IRQWKUP_ENB BIT(0)
45
46/* Step Enable */
47#define STEPENB_MASK (0x1FFFF << 0)
48#define STEPENB(val) ((val) << 0)
49#define STPENB_STEPENB STEPENB(0x1FFFF)
50#define STPENB_STEPENB_TC STEPENB(0x1FFF)
51
52/* IRQ enable */
53#define IRQENB_HW_PEN BIT(0)
54#define IRQENB_FIFO0THRES BIT(2)
55#define IRQENB_FIFO1THRES BIT(5)
56#define IRQENB_PENUP BIT(9)
57
58/* Step Configuration */
59#define STEPCONFIG_MODE_MASK (3 << 0)
60#define STEPCONFIG_MODE(val) ((val) << 0)
61#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
62#define STEPCONFIG_AVG_MASK (7 << 2)
63#define STEPCONFIG_AVG(val) ((val) << 2)
64#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
65#define STEPCONFIG_XPP BIT(5)
66#define STEPCONFIG_XNN BIT(6)
67#define STEPCONFIG_YPP BIT(7)
68#define STEPCONFIG_YNN BIT(8)
69#define STEPCONFIG_XNP BIT(9)
70#define STEPCONFIG_YPN BIT(10)
71#define STEPCONFIG_INM_MASK (0xF << 15)
72#define STEPCONFIG_INM(val) ((val) << 15)
73#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
74#define STEPCONFIG_INP_MASK (0xF << 19)
75#define STEPCONFIG_INP(val) ((val) << 19)
76#define STEPCONFIG_INP_AN2 STEPCONFIG_INP(2)
77#define STEPCONFIG_INP_AN3 STEPCONFIG_INP(3)
78#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
79#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
80#define STEPCONFIG_FIFO1 BIT(26)
81
82/* Delay register */
83#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
84#define STEPDELAY_OPEN(val) ((val) << 0)
85#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
86#define STEPDELAY_SAMPLE_MASK (0xFF << 24)
87#define STEPDELAY_SAMPLE(val) ((val) << 24)
88#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
89
90/* Charge Config */
91#define STEPCHARGE_RFP_MASK (7 << 12)
92#define STEPCHARGE_RFP(val) ((val) << 12)
93#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
94#define STEPCHARGE_INM_MASK (0xF << 15)
95#define STEPCHARGE_INM(val) ((val) << 15)
96#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
97#define STEPCHARGE_INP_MASK (0xF << 19)
98#define STEPCHARGE_INP(val) ((val) << 19)
99#define STEPCHARGE_INP_AN1 STEPCHARGE_INP(1)
100#define STEPCHARGE_RFM_MASK (3 << 23)
101#define STEPCHARGE_RFM(val) ((val) << 23)
102#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
103
104/* Charge delay */
105#define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
106#define CHARGEDLY_OPEN(val) ((val) << 0)
107#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(1)
108
109/* Control register */
110#define CNTRLREG_TSCSSENB BIT(0)
111#define CNTRLREG_STEPID BIT(1)
112#define CNTRLREG_STEPCONFIGWRT BIT(2)
113#define CNTRLREG_POWERDOWN BIT(4)
114#define CNTRLREG_AFE_CTRL_MASK (3 << 5)
115#define CNTRLREG_AFE_CTRL(val) ((val) << 5)
116#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
117#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
118#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
119#define CNTRLREG_TSCENB BIT(7)
120
121#define ADC_CLK 3000000
122#define MAX_CLK_DIV 7
123#define TOTAL_STEPS 16
124#define TOTAL_CHANNELS 8
125
126#define TSCADC_CELLS 2
127
128enum tscadc_cells {
129 TSC_CELL,
130 ADC_CELL,
131};
132
133struct mfd_tscadc_board {
134 struct tsc_data *tsc_init;
135 struct adc_data *adc_init;
136};
137
138struct ti_tscadc_dev {
139 struct device *dev;
140 struct regmap *regmap_tscadc;
141 void __iomem *tscadc_base;
142 int irq;
143 struct mfd_cell cells[TSCADC_CELLS];
144
145 /* tsc device */
146 struct titsc *tsc;
147
148 /* adc device */
149 struct adc_device *adc;
150};
151
152#endif
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
index 6bc31d854626..6694cf43e8b8 100644
--- a/include/linux/mfd/tps65090.h
+++ b/include/linux/mfd/tps65090.h
@@ -23,37 +23,109 @@
23#define __LINUX_MFD_TPS65090_H 23#define __LINUX_MFD_TPS65090_H
24 24
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/regmap.h>
27
28/* TPS65090 IRQs */
29enum {
30 TPS65090_IRQ_VAC_STATUS_CHANGE,
31 TPS65090_IRQ_VSYS_STATUS_CHANGE,
32 TPS65090_IRQ_BAT_STATUS_CHANGE,
33 TPS65090_IRQ_CHARGING_STATUS_CHANGE,
34 TPS65090_IRQ_CHARGING_COMPLETE,
35 TPS65090_IRQ_OVERLOAD_DCDC1,
36 TPS65090_IRQ_OVERLOAD_DCDC2,
37 TPS65090_IRQ_OVERLOAD_DCDC3,
38 TPS65090_IRQ_OVERLOAD_FET1,
39 TPS65090_IRQ_OVERLOAD_FET2,
40 TPS65090_IRQ_OVERLOAD_FET3,
41 TPS65090_IRQ_OVERLOAD_FET4,
42 TPS65090_IRQ_OVERLOAD_FET5,
43 TPS65090_IRQ_OVERLOAD_FET6,
44 TPS65090_IRQ_OVERLOAD_FET7,
45};
46
47/* TPS65090 Regulator ID */
48enum {
49 TPS65090_REGULATOR_DCDC1,
50 TPS65090_REGULATOR_DCDC2,
51 TPS65090_REGULATOR_DCDC3,
52 TPS65090_REGULATOR_FET1,
53 TPS65090_REGULATOR_FET2,
54 TPS65090_REGULATOR_FET3,
55 TPS65090_REGULATOR_FET4,
56 TPS65090_REGULATOR_FET5,
57 TPS65090_REGULATOR_FET6,
58 TPS65090_REGULATOR_FET7,
59 TPS65090_REGULATOR_LDO1,
60 TPS65090_REGULATOR_LDO2,
61
62 /* Last entry for maximum ID */
63 TPS65090_REGULATOR_MAX,
64};
26 65
27struct tps65090 { 66struct tps65090 {
28 struct mutex lock;
29 struct device *dev; 67 struct device *dev;
30 struct i2c_client *client;
31 struct regmap *rmap; 68 struct regmap *rmap;
32 struct irq_chip irq_chip; 69 struct regmap_irq_chip_data *irq_data;
33 struct mutex irq_lock;
34 int irq_base;
35 unsigned int id;
36}; 70};
37 71
38struct tps65090_subdev_info { 72/*
39 int id; 73 * struct tps65090_regulator_plat_data
40 const char *name; 74 *
41 void *platform_data; 75 * @reg_init_data: The regulator init data.
76 * @enable_ext_control: Enable extrenal control or not. Only available for
77 * DCDC1, DCDC2 and DCDC3.
78 * @gpio: Gpio number if external control is enabled and controlled through
79 * gpio.
80 */
81struct tps65090_regulator_plat_data {
82 struct regulator_init_data *reg_init_data;
83 bool enable_ext_control;
84 int gpio;
42}; 85};
43 86
44struct tps65090_platform_data { 87struct tps65090_platform_data {
45 int irq_base; 88 int irq_base;
46 int num_subdevs; 89 struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX];
47 struct tps65090_subdev_info *subdevs;
48}; 90};
49 91
50/* 92/*
51 * NOTE: the functions below are not intended for use outside 93 * NOTE: the functions below are not intended for use outside
52 * of the TPS65090 sub-device drivers 94 * of the TPS65090 sub-device drivers
53 */ 95 */
54extern int tps65090_write(struct device *dev, int reg, uint8_t val); 96static inline int tps65090_write(struct device *dev, int reg, uint8_t val)
55extern int tps65090_read(struct device *dev, int reg, uint8_t *val); 97{
56extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num); 98 struct tps65090 *tps = dev_get_drvdata(dev);
57extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num); 99
100 return regmap_write(tps->rmap, reg, val);
101}
102
103static inline int tps65090_read(struct device *dev, int reg, uint8_t *val)
104{
105 struct tps65090 *tps = dev_get_drvdata(dev);
106 unsigned int temp_val;
107 int ret;
108
109 ret = regmap_read(tps->rmap, reg, &temp_val);
110 if (!ret)
111 *val = temp_val;
112 return ret;
113}
114
115static inline int tps65090_set_bits(struct device *dev, int reg,
116 uint8_t bit_num)
117{
118 struct tps65090 *tps = dev_get_drvdata(dev);
119
120 return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u);
121}
122
123static inline int tps65090_clr_bits(struct device *dev, int reg,
124 uint8_t bit_num)
125{
126 struct tps65090 *tps = dev_get_drvdata(dev);
127
128 return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u);
129}
58 130
59#endif /*__LINUX_MFD_TPS65090_H */ 131#endif /*__LINUX_MFD_TPS65090_H */
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index 2dd123194958..87994542573b 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -29,6 +29,7 @@ enum {
29 TPS6586X_ID_LDO_8, 29 TPS6586X_ID_LDO_8,
30 TPS6586X_ID_LDO_9, 30 TPS6586X_ID_LDO_9,
31 TPS6586X_ID_LDO_RTC, 31 TPS6586X_ID_LDO_RTC,
32 TPS6586X_ID_MAX_REGULATOR,
32}; 33};
33 34
34enum { 35enum {
@@ -79,6 +80,8 @@ struct tps6586x_platform_data {
79 int gpio_base; 80 int gpio_base;
80 int irq_base; 81 int irq_base;
81 bool pm_off; 82 bool pm_off;
83
84 struct regulator_init_data *reg_init_data[TPS6586X_ID_MAX_REGULATOR];
82}; 85};
83 86
84/* 87/*
@@ -93,5 +96,6 @@ extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
93extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); 96extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
94extern int tps6586x_update(struct device *dev, int reg, uint8_t val, 97extern int tps6586x_update(struct device *dev, int reg, uint8_t val,
95 uint8_t mask); 98 uint8_t mask);
99extern int tps6586x_irq_get_virq(struct device *dev, int irq);
96 100
97#endif /*__LINUX_MFD_TPS6586X_H */ 101#endif /*__LINUX_MFD_TPS6586X_H */
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 02e894f3ff45..20e433e551e3 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -572,6 +572,49 @@
572#define SPARE_SPARE_MASK 0xFF 572#define SPARE_SPARE_MASK 0xFF
573#define SPARE_SPARE_SHIFT 0 573#define SPARE_SPARE_SHIFT 0
574 574
575#define TPS65910_INT_STS_RTC_PERIOD_IT_MASK 0x80
576#define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT 7
577#define TPS65910_INT_STS_RTC_ALARM_IT_MASK 0x40
578#define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT 6
579#define TPS65910_INT_STS_HOTDIE_IT_MASK 0x20
580#define TPS65910_INT_STS_HOTDIE_IT_SHIFT 5
581#define TPS65910_INT_STS_PWRHOLD_F_IT_MASK 0x10
582#define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT 4
583#define TPS65910_INT_STS_PWRON_LP_IT_MASK 0x08
584#define TPS65910_INT_STS_PWRON_LP_IT_SHIFT 3
585#define TPS65910_INT_STS_PWRON_IT_MASK 0x04
586#define TPS65910_INT_STS_PWRON_IT_SHIFT 2
587#define TPS65910_INT_STS_VMBHI_IT_MASK 0x02
588#define TPS65910_INT_STS_VMBHI_IT_SHIFT 1
589#define TPS65910_INT_STS_VMBDCH_IT_MASK 0x01
590#define TPS65910_INT_STS_VMBDCH_IT_SHIFT 0
591
592#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
593#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
594#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
595#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
596#define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK 0x20
597#define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT 5
598#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
599#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
600#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
601#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
602#define TPS65910_INT_MSK_PWRON_IT_MSK_MASK 0x04
603#define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT 2
604#define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK 0x02
605#define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT 1
606#define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK 0x01
607#define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT 0
608
609#define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT 2
610#define TPS65910_INT_STS2_GPIO0_F_IT_MASK 0x02
611#define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT 1
612#define TPS65910_INT_STS2_GPIO0_R_IT_MASK 0x01
613
614#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT 2
615#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
616#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT 1
617#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
575 618
576/*Register INT_STS (0x80) register.RegisterDescription */ 619/*Register INT_STS (0x80) register.RegisterDescription */
577#define INT_STS_RTC_PERIOD_IT_MASK 0x80 620#define INT_STS_RTC_PERIOD_IT_MASK 0x80
@@ -580,16 +623,16 @@
580#define INT_STS_RTC_ALARM_IT_SHIFT 6 623#define INT_STS_RTC_ALARM_IT_SHIFT 6
581#define INT_STS_HOTDIE_IT_MASK 0x20 624#define INT_STS_HOTDIE_IT_MASK 0x20
582#define INT_STS_HOTDIE_IT_SHIFT 5 625#define INT_STS_HOTDIE_IT_SHIFT 5
583#define INT_STS_PWRHOLD_IT_MASK 0x10 626#define INT_STS_PWRHOLD_R_IT_MASK 0x10
584#define INT_STS_PWRHOLD_IT_SHIFT 4 627#define INT_STS_PWRHOLD_R_IT_SHIFT 4
585#define INT_STS_PWRON_LP_IT_MASK 0x08 628#define INT_STS_PWRON_LP_IT_MASK 0x08
586#define INT_STS_PWRON_LP_IT_SHIFT 3 629#define INT_STS_PWRON_LP_IT_SHIFT 3
587#define INT_STS_PWRON_IT_MASK 0x04 630#define INT_STS_PWRON_IT_MASK 0x04
588#define INT_STS_PWRON_IT_SHIFT 2 631#define INT_STS_PWRON_IT_SHIFT 2
589#define INT_STS_VMBHI_IT_MASK 0x02 632#define INT_STS_VMBHI_IT_MASK 0x02
590#define INT_STS_VMBHI_IT_SHIFT 1 633#define INT_STS_VMBHI_IT_SHIFT 1
591#define INT_STS_VMBDCH_IT_MASK 0x01 634#define INT_STS_PWRHOLD_F_IT_MASK 0x01
592#define INT_STS_VMBDCH_IT_SHIFT 0 635#define INT_STS_PWRHOLD_F_IT_SHIFT 0
593 636
594 637
595/*Register INT_MSK (0x80) register.RegisterDescription */ 638/*Register INT_MSK (0x80) register.RegisterDescription */
@@ -599,16 +642,16 @@
599#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 642#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
600#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 643#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
601#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 644#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
602#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 645#define INT_MSK_PWRHOLD_R_IT_MSK_MASK 0x10
603#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 646#define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT 4
604#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 647#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
605#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 648#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
606#define INT_MSK_PWRON_IT_MSK_MASK 0x04 649#define INT_MSK_PWRON_IT_MSK_MASK 0x04
607#define INT_MSK_PWRON_IT_MSK_SHIFT 2 650#define INT_MSK_PWRON_IT_MSK_SHIFT 2
608#define INT_MSK_VMBHI_IT_MSK_MASK 0x02 651#define INT_MSK_VMBHI_IT_MSK_MASK 0x02
609#define INT_MSK_VMBHI_IT_MSK_SHIFT 1 652#define INT_MSK_VMBHI_IT_MSK_SHIFT 1
610#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 653#define INT_MSK_PWRHOLD_F_IT_MSK_MASK 0x01
611#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 654#define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT 0
612 655
613 656
614/*Register INT_STS2 (0x80) register.RegisterDescription */ 657/*Register INT_STS2 (0x80) register.RegisterDescription */
@@ -650,6 +693,14 @@
650 693
651 694
652/*Register INT_STS3 (0x80) register.RegisterDescription */ 695/*Register INT_STS3 (0x80) register.RegisterDescription */
696#define INT_STS3_PWRDN_IT_MASK 0x80
697#define INT_STS3_PWRDN_IT_SHIFT 7
698#define INT_STS3_VMBCH2_L_IT_MASK 0x40
699#define INT_STS3_VMBCH2_L_IT_SHIFT 6
700#define INT_STS3_VMBCH2_H_IT_MASK 0x20
701#define INT_STS3_VMBCH2_H_IT_SHIFT 5
702#define INT_STS3_WTCHDG_IT_MASK 0x10
703#define INT_STS3_WTCHDG_IT_SHIFT 4
653#define INT_STS3_GPIO5_F_IT_MASK 0x08 704#define INT_STS3_GPIO5_F_IT_MASK 0x08
654#define INT_STS3_GPIO5_F_IT_SHIFT 3 705#define INT_STS3_GPIO5_F_IT_SHIFT 3
655#define INT_STS3_GPIO5_R_IT_MASK 0x04 706#define INT_STS3_GPIO5_R_IT_MASK 0x04
@@ -661,6 +712,14 @@
661 712
662 713
663/*Register INT_MSK3 (0x80) register.RegisterDescription */ 714/*Register INT_MSK3 (0x80) register.RegisterDescription */
715#define INT_MSK3_PWRDN_IT_MSK_MASK 0x80
716#define INT_MSK3_PWRDN_IT_MSK_SHIFT 7
717#define INT_MSK3_VMBCH2_L_IT_MSK_MASK 0x40
718#define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT 6
719#define INT_MSK3_VMBCH2_H_IT_MSK_MASK 0x20
720#define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT 5
721#define INT_MSK3_WTCHDG_IT_MSK_MASK 0x10
722#define INT_MSK3_WTCHDG_IT_MSK_SHIFT 4
664#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 723#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
665#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 724#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
666#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 725#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
@@ -721,34 +780,32 @@
721#define TPS65910_IRQ_GPIO_F 9 780#define TPS65910_IRQ_GPIO_F 9
722#define TPS65910_NUM_IRQ 10 781#define TPS65910_NUM_IRQ 10
723 782
724#define TPS65911_IRQ_VBAT_VMBDCH 0 783#define TPS65911_IRQ_PWRHOLD_F 0
725#define TPS65911_IRQ_VBAT_VMBDCH2L 1 784#define TPS65911_IRQ_VBAT_VMHI 1
726#define TPS65911_IRQ_VBAT_VMBDCH2H 2 785#define TPS65911_IRQ_PWRON 2
727#define TPS65911_IRQ_VBAT_VMHI 3 786#define TPS65911_IRQ_PWRON_LP 3
728#define TPS65911_IRQ_PWRON 4 787#define TPS65911_IRQ_PWRHOLD_R 4
729#define TPS65911_IRQ_PWRON_LP 5 788#define TPS65911_IRQ_HOTDIE 5
730#define TPS65911_IRQ_PWRHOLD_F 6 789#define TPS65911_IRQ_RTC_ALARM 6
731#define TPS65911_IRQ_PWRHOLD_R 7 790#define TPS65911_IRQ_RTC_PERIOD 7
732#define TPS65911_IRQ_HOTDIE 8 791#define TPS65911_IRQ_GPIO0_R 8
733#define TPS65911_IRQ_RTC_ALARM 9 792#define TPS65911_IRQ_GPIO0_F 9
734#define TPS65911_IRQ_RTC_PERIOD 10 793#define TPS65911_IRQ_GPIO1_R 10
735#define TPS65911_IRQ_GPIO0_R 11 794#define TPS65911_IRQ_GPIO1_F 11
736#define TPS65911_IRQ_GPIO0_F 12 795#define TPS65911_IRQ_GPIO2_R 12
737#define TPS65911_IRQ_GPIO1_R 13 796#define TPS65911_IRQ_GPIO2_F 13
738#define TPS65911_IRQ_GPIO1_F 14 797#define TPS65911_IRQ_GPIO3_R 14
739#define TPS65911_IRQ_GPIO2_R 15 798#define TPS65911_IRQ_GPIO3_F 15
740#define TPS65911_IRQ_GPIO2_F 16 799#define TPS65911_IRQ_GPIO4_R 16
741#define TPS65911_IRQ_GPIO3_R 17 800#define TPS65911_IRQ_GPIO4_F 17
742#define TPS65911_IRQ_GPIO3_F 18 801#define TPS65911_IRQ_GPIO5_R 18
743#define TPS65911_IRQ_GPIO4_R 19 802#define TPS65911_IRQ_GPIO5_F 19
744#define TPS65911_IRQ_GPIO4_F 20 803#define TPS65911_IRQ_WTCHDG 20
745#define TPS65911_IRQ_GPIO5_R 21 804#define TPS65911_IRQ_VMBCH2_H 21
746#define TPS65911_IRQ_GPIO5_F 22 805#define TPS65911_IRQ_VMBCH2_L 22
747#define TPS65911_IRQ_WTCHDG 23 806#define TPS65911_IRQ_PWRDN 23
748#define TPS65911_IRQ_PWRDN 24 807
749 808#define TPS65911_NUM_IRQ 24
750#define TPS65911_NUM_IRQ 25
751
752 809
753/* GPIO Register Definitions */ 810/* GPIO Register Definitions */
754#define TPS65910_GPIO_DEB BIT(2) 811#define TPS65910_GPIO_DEB BIT(2)
@@ -836,7 +893,6 @@ struct tps65910 {
836 struct device *dev; 893 struct device *dev;
837 struct i2c_client *i2c_client; 894 struct i2c_client *i2c_client;
838 struct regmap *regmap; 895 struct regmap *regmap;
839 struct mutex io_mutex;
840 unsigned int id; 896 unsigned int id;
841 897
842 /* Client devices */ 898 /* Client devices */
@@ -848,12 +904,8 @@ struct tps65910 {
848 struct tps65910_board *of_plat_data; 904 struct tps65910_board *of_plat_data;
849 905
850 /* IRQ Handling */ 906 /* IRQ Handling */
851 struct mutex irq_lock;
852 int chip_irq; 907 int chip_irq;
853 int irq_base; 908 struct regmap_irq_chip_data *irq_data;
854 int irq_num;
855 u32 irq_mask;
856 struct irq_domain *domain;
857}; 909};
858 910
859struct tps65910_platform_data { 911struct tps65910_platform_data {
@@ -861,10 +913,6 @@ struct tps65910_platform_data {
861 int irq_base; 913 int irq_base;
862}; 914};
863 915
864int tps65910_irq_init(struct tps65910 *tps65910, int irq,
865 struct tps65910_platform_data *pdata);
866int tps65910_irq_exit(struct tps65910 *tps65910);
867
868static inline int tps65910_chip_id(struct tps65910 *tps65910) 916static inline int tps65910_chip_id(struct tps65910 *tps65910)
869{ 917{
870 return tps65910->id; 918 return tps65910->id;
@@ -900,4 +948,9 @@ static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg,
900 return regmap_update_bits(tps65910->regmap, reg, mask, val); 948 return regmap_update_bits(tps65910->regmap, reg, mask, val);
901} 949}
902 950
951static inline int tps65910_irq_get_virq(struct tps65910 *tps65910, int irq)
952{
953 return regmap_irq_get_virq(tps65910->irq_data, irq);
954}
955
903#endif /* __LINUX_MFD_TPS65910_H */ 956#endif /* __LINUX_MFD_TPS65910_H */
diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h
new file mode 100644
index 000000000000..2c75c9c9318f
--- /dev/null
+++ b/include/linux/mfd/tps80031.h
@@ -0,0 +1,637 @@
1/*
2 * tps80031.h -- TI TPS80031 and TI TPS80032 PMIC driver.
3 *
4 * Copyright (c) 2012, NVIDIA Corporation.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
13 * whether express or implied; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307, USA
21 */
22
23#ifndef __LINUX_MFD_TPS80031_H
24#define __LINUX_MFD_TPS80031_H
25
26#include <linux/device.h>
27#include <linux/regmap.h>
28
29/* Pull-ups/Pull-downs */
30#define TPS80031_CFG_INPUT_PUPD1 0xF0
31#define TPS80031_CFG_INPUT_PUPD2 0xF1
32#define TPS80031_CFG_INPUT_PUPD3 0xF2
33#define TPS80031_CFG_INPUT_PUPD4 0xF3
34#define TPS80031_CFG_LDO_PD1 0xF4
35#define TPS80031_CFG_LDO_PD2 0xF5
36#define TPS80031_CFG_SMPS_PD 0xF6
37
38/* Real Time Clock */
39#define TPS80031_SECONDS_REG 0x00
40#define TPS80031_MINUTES_REG 0x01
41#define TPS80031_HOURS_REG 0x02
42#define TPS80031_DAYS_REG 0x03
43#define TPS80031_MONTHS_REG 0x04
44#define TPS80031_YEARS_REG 0x05
45#define TPS80031_WEEKS_REG 0x06
46#define TPS80031_ALARM_SECONDS_REG 0x08
47#define TPS80031_ALARM_MINUTES_REG 0x09
48#define TPS80031_ALARM_HOURS_REG 0x0A
49#define TPS80031_ALARM_DAYS_REG 0x0B
50#define TPS80031_ALARM_MONTHS_REG 0x0C
51#define TPS80031_ALARM_YEARS_REG 0x0D
52#define TPS80031_RTC_CTRL_REG 0x10
53#define TPS80031_RTC_STATUS_REG 0x11
54#define TPS80031_RTC_INTERRUPTS_REG 0x12
55#define TPS80031_RTC_COMP_LSB_REG 0x13
56#define TPS80031_RTC_COMP_MSB_REG 0x14
57#define TPS80031_RTC_RESET_STATUS_REG 0x16
58
59/*PMC Master Module */
60#define TPS80031_PHOENIX_START_CONDITION 0x1F
61#define TPS80031_PHOENIX_MSK_TRANSITION 0x20
62#define TPS80031_STS_HW_CONDITIONS 0x21
63#define TPS80031_PHOENIX_LAST_TURNOFF_STS 0x22
64#define TPS80031_VSYSMIN_LO_THRESHOLD 0x23
65#define TPS80031_VSYSMIN_HI_THRESHOLD 0x24
66#define TPS80031_PHOENIX_DEV_ON 0x25
67#define TPS80031_STS_PWR_GRP_STATE 0x27
68#define TPS80031_PH_CFG_VSYSLOW 0x28
69#define TPS80031_PH_STS_BOOT 0x29
70#define TPS80031_PHOENIX_SENS_TRANSITION 0x2A
71#define TPS80031_PHOENIX_SEQ_CFG 0x2B
72#define TPS80031_PRIMARY_WATCHDOG_CFG 0X2C
73#define TPS80031_KEY_PRESS_DUR_CFG 0X2D
74#define TPS80031_SMPS_LDO_SHORT_STS 0x2E
75
76/* PMC Slave Module - Broadcast */
77#define TPS80031_BROADCAST_ADDR_ALL 0x31
78#define TPS80031_BROADCAST_ADDR_REF 0x32
79#define TPS80031_BROADCAST_ADDR_PROV 0x33
80#define TPS80031_BROADCAST_ADDR_CLK_RST 0x34
81
82/* PMC Slave Module SMPS Regulators */
83#define TPS80031_SMPS4_CFG_TRANS 0x41
84#define TPS80031_SMPS4_CFG_STATE 0x42
85#define TPS80031_SMPS4_CFG_VOLTAGE 0x44
86#define TPS80031_VIO_CFG_TRANS 0x47
87#define TPS80031_VIO_CFG_STATE 0x48
88#define TPS80031_VIO_CFG_FORCE 0x49
89#define TPS80031_VIO_CFG_VOLTAGE 0x4A
90#define TPS80031_VIO_CFG_STEP 0x48
91#define TPS80031_SMPS1_CFG_TRANS 0x53
92#define TPS80031_SMPS1_CFG_STATE 0x54
93#define TPS80031_SMPS1_CFG_FORCE 0x55
94#define TPS80031_SMPS1_CFG_VOLTAGE 0x56
95#define TPS80031_SMPS1_CFG_STEP 0x57
96#define TPS80031_SMPS2_CFG_TRANS 0x59
97#define TPS80031_SMPS2_CFG_STATE 0x5A
98#define TPS80031_SMPS2_CFG_FORCE 0x5B
99#define TPS80031_SMPS2_CFG_VOLTAGE 0x5C
100#define TPS80031_SMPS2_CFG_STEP 0x5D
101#define TPS80031_SMPS3_CFG_TRANS 0x65
102#define TPS80031_SMPS3_CFG_STATE 0x66
103#define TPS80031_SMPS3_CFG_VOLTAGE 0x68
104
105/* PMC Slave Module LDO Regulators */
106#define TPS80031_VANA_CFG_TRANS 0x81
107#define TPS80031_VANA_CFG_STATE 0x82
108#define TPS80031_VANA_CFG_VOLTAGE 0x83
109#define TPS80031_LDO2_CFG_TRANS 0x85
110#define TPS80031_LDO2_CFG_STATE 0x86
111#define TPS80031_LDO2_CFG_VOLTAGE 0x87
112#define TPS80031_LDO4_CFG_TRANS 0x89
113#define TPS80031_LDO4_CFG_STATE 0x8A
114#define TPS80031_LDO4_CFG_VOLTAGE 0x8B
115#define TPS80031_LDO3_CFG_TRANS 0x8D
116#define TPS80031_LDO3_CFG_STATE 0x8E
117#define TPS80031_LDO3_CFG_VOLTAGE 0x8F
118#define TPS80031_LDO6_CFG_TRANS 0x91
119#define TPS80031_LDO6_CFG_STATE 0x92
120#define TPS80031_LDO6_CFG_VOLTAGE 0x93
121#define TPS80031_LDOLN_CFG_TRANS 0x95
122#define TPS80031_LDOLN_CFG_STATE 0x96
123#define TPS80031_LDOLN_CFG_VOLTAGE 0x97
124#define TPS80031_LDO5_CFG_TRANS 0x99
125#define TPS80031_LDO5_CFG_STATE 0x9A
126#define TPS80031_LDO5_CFG_VOLTAGE 0x9B
127#define TPS80031_LDO1_CFG_TRANS 0x9D
128#define TPS80031_LDO1_CFG_STATE 0x9E
129#define TPS80031_LDO1_CFG_VOLTAGE 0x9F
130#define TPS80031_LDOUSB_CFG_TRANS 0xA1
131#define TPS80031_LDOUSB_CFG_STATE 0xA2
132#define TPS80031_LDOUSB_CFG_VOLTAGE 0xA3
133#define TPS80031_LDO7_CFG_TRANS 0xA5
134#define TPS80031_LDO7_CFG_STATE 0xA6
135#define TPS80031_LDO7_CFG_VOLTAGE 0xA7
136
137/* PMC Slave Module External Control */
138#define TPS80031_REGEN1_CFG_TRANS 0xAE
139#define TPS80031_REGEN1_CFG_STATE 0xAF
140#define TPS80031_REGEN2_CFG_TRANS 0xB1
141#define TPS80031_REGEN2_CFG_STATE 0xB2
142#define TPS80031_SYSEN_CFG_TRANS 0xB4
143#define TPS80031_SYSEN_CFG_STATE 0xB5
144
145/* PMC Slave Module Internal Control */
146#define TPS80031_NRESPWRON_CFG_TRANS 0xB7
147#define TPS80031_NRESPWRON_CFG_STATE 0xB8
148#define TPS80031_CLK32KAO_CFG_TRANS 0xBA
149#define TPS80031_CLK32KAO_CFG_STATE 0xBB
150#define TPS80031_CLK32KG_CFG_TRANS 0xBD
151#define TPS80031_CLK32KG_CFG_STATE 0xBE
152#define TPS80031_CLK32KAUDIO_CFG_TRANS 0xC0
153#define TPS80031_CLK32KAUDIO_CFG_STATE 0xC1
154#define TPS80031_VRTC_CFG_TRANS 0xC3
155#define TPS80031_VRTC_CFG_STATE 0xC4
156#define TPS80031_BIAS_CFG_TRANS 0xC6
157#define TPS80031_BIAS_CFG_STATE 0xC7
158#define TPS80031_VSYSMIN_HI_CFG_TRANS 0xC9
159#define TPS80031_VSYSMIN_HI_CFG_STATE 0xCA
160#define TPS80031_RC6MHZ_CFG_TRANS 0xCC
161#define TPS80031_RC6MHZ_CFG_STATE 0xCD
162#define TPS80031_TMP_CFG_TRANS 0xCF
163#define TPS80031_TMP_CFG_STATE 0xD0
164
165/* PMC Slave Module resources assignment */
166#define TPS80031_PREQ1_RES_ASS_A 0xD7
167#define TPS80031_PREQ1_RES_ASS_B 0xD8
168#define TPS80031_PREQ1_RES_ASS_C 0xD9
169#define TPS80031_PREQ2_RES_ASS_A 0xDA
170#define TPS80031_PREQ2_RES_ASS_B 0xDB
171#define TPS80031_PREQ2_RES_ASS_C 0xDC
172#define TPS80031_PREQ3_RES_ASS_A 0xDD
173#define TPS80031_PREQ3_RES_ASS_B 0xDE
174#define TPS80031_PREQ3_RES_ASS_C 0xDF
175
176/* PMC Slave Module Miscellaneous */
177#define TPS80031_SMPS_OFFSET 0xE0
178#define TPS80031_SMPS_MULT 0xE3
179#define TPS80031_MISC1 0xE4
180#define TPS80031_MISC2 0xE5
181#define TPS80031_BBSPOR_CFG 0xE6
182#define TPS80031_TMP_CFG 0xE7
183
184/* Battery Charging Controller and Indicator LED */
185#define TPS80031_CONTROLLER_CTRL2 0xDA
186#define TPS80031_CONTROLLER_VSEL_COMP 0xDB
187#define TPS80031_CHARGERUSB_VSYSREG 0xDC
188#define TPS80031_CHARGERUSB_VICHRG_PC 0xDD
189#define TPS80031_LINEAR_CHRG_STS 0xDE
190#define TPS80031_CONTROLLER_INT_MASK 0xE0
191#define TPS80031_CONTROLLER_CTRL1 0xE1
192#define TPS80031_CONTROLLER_WDG 0xE2
193#define TPS80031_CONTROLLER_STAT1 0xE3
194#define TPS80031_CHARGERUSB_INT_STATUS 0xE4
195#define TPS80031_CHARGERUSB_INT_MASK 0xE5
196#define TPS80031_CHARGERUSB_STATUS_INT1 0xE6
197#define TPS80031_CHARGERUSB_STATUS_INT2 0xE7
198#define TPS80031_CHARGERUSB_CTRL1 0xE8
199#define TPS80031_CHARGERUSB_CTRL2 0xE9
200#define TPS80031_CHARGERUSB_CTRL3 0xEA
201#define TPS80031_CHARGERUSB_STAT1 0xEB
202#define TPS80031_CHARGERUSB_VOREG 0xEC
203#define TPS80031_CHARGERUSB_VICHRG 0xED
204#define TPS80031_CHARGERUSB_CINLIMIT 0xEE
205#define TPS80031_CHARGERUSB_CTRLLIMIT1 0xEF
206#define TPS80031_CHARGERUSB_CTRLLIMIT2 0xF0
207#define TPS80031_LED_PWM_CTRL1 0xF4
208#define TPS80031_LED_PWM_CTRL2 0xF5
209
210/* USB On-The-Go */
211#define TPS80031_BACKUP_REG 0xFA
212#define TPS80031_USB_VENDOR_ID_LSB 0x00
213#define TPS80031_USB_VENDOR_ID_MSB 0x01
214#define TPS80031_USB_PRODUCT_ID_LSB 0x02
215#define TPS80031_USB_PRODUCT_ID_MSB 0x03
216#define TPS80031_USB_VBUS_CTRL_SET 0x04
217#define TPS80031_USB_VBUS_CTRL_CLR 0x05
218#define TPS80031_USB_ID_CTRL_SET 0x06
219#define TPS80031_USB_ID_CTRL_CLR 0x07
220#define TPS80031_USB_VBUS_INT_SRC 0x08
221#define TPS80031_USB_VBUS_INT_LATCH_SET 0x09
222#define TPS80031_USB_VBUS_INT_LATCH_CLR 0x0A
223#define TPS80031_USB_VBUS_INT_EN_LO_SET 0x0B
224#define TPS80031_USB_VBUS_INT_EN_LO_CLR 0x0C
225#define TPS80031_USB_VBUS_INT_EN_HI_SET 0x0D
226#define TPS80031_USB_VBUS_INT_EN_HI_CLR 0x0E
227#define TPS80031_USB_ID_INT_SRC 0x0F
228#define TPS80031_USB_ID_INT_LATCH_SET 0x10
229#define TPS80031_USB_ID_INT_LATCH_CLR 0x11
230#define TPS80031_USB_ID_INT_EN_LO_SET 0x12
231#define TPS80031_USB_ID_INT_EN_LO_CLR 0x13
232#define TPS80031_USB_ID_INT_EN_HI_SET 0x14
233#define TPS80031_USB_ID_INT_EN_HI_CLR 0x15
234#define TPS80031_USB_OTG_ADP_CTRL 0x16
235#define TPS80031_USB_OTG_ADP_HIGH 0x17
236#define TPS80031_USB_OTG_ADP_LOW 0x18
237#define TPS80031_USB_OTG_ADP_RISE 0x19
238#define TPS80031_USB_OTG_REVISION 0x1A
239
240/* Gas Gauge */
241#define TPS80031_FG_REG_00 0xC0
242#define TPS80031_FG_REG_01 0xC1
243#define TPS80031_FG_REG_02 0xC2
244#define TPS80031_FG_REG_03 0xC3
245#define TPS80031_FG_REG_04 0xC4
246#define TPS80031_FG_REG_05 0xC5
247#define TPS80031_FG_REG_06 0xC6
248#define TPS80031_FG_REG_07 0xC7
249#define TPS80031_FG_REG_08 0xC8
250#define TPS80031_FG_REG_09 0xC9
251#define TPS80031_FG_REG_10 0xCA
252#define TPS80031_FG_REG_11 0xCB
253
254/* General Purpose ADC */
255#define TPS80031_GPADC_CTRL 0x2E
256#define TPS80031_GPADC_CTRL2 0x2F
257#define TPS80031_RTSELECT_LSB 0x32
258#define TPS80031_RTSELECT_ISB 0x33
259#define TPS80031_RTSELECT_MSB 0x34
260#define TPS80031_GPSELECT_ISB 0x35
261#define TPS80031_CTRL_P1 0x36
262#define TPS80031_RTCH0_LSB 0x37
263#define TPS80031_RTCH0_MSB 0x38
264#define TPS80031_RTCH1_LSB 0x39
265#define TPS80031_RTCH1_MSB 0x3A
266#define TPS80031_GPCH0_LSB 0x3B
267#define TPS80031_GPCH0_MSB 0x3C
268
269/* SIM, MMC and Battery Detection */
270#define TPS80031_SIMDEBOUNCING 0xEB
271#define TPS80031_SIMCTRL 0xEC
272#define TPS80031_MMCDEBOUNCING 0xED
273#define TPS80031_MMCCTRL 0xEE
274#define TPS80031_BATDEBOUNCING 0xEF
275
276/* Vibrator Driver and PWMs */
277#define TPS80031_VIBCTRL 0x9B
278#define TPS80031_VIBMODE 0x9C
279#define TPS80031_PWM1ON 0xBA
280#define TPS80031_PWM1OFF 0xBB
281#define TPS80031_PWM2ON 0xBD
282#define TPS80031_PWM2OFF 0xBE
283
284/* Control Interface */
285#define TPS80031_INT_STS_A 0xD0
286#define TPS80031_INT_STS_B 0xD1
287#define TPS80031_INT_STS_C 0xD2
288#define TPS80031_INT_MSK_LINE_A 0xD3
289#define TPS80031_INT_MSK_LINE_B 0xD4
290#define TPS80031_INT_MSK_LINE_C 0xD5
291#define TPS80031_INT_MSK_STS_A 0xD6
292#define TPS80031_INT_MSK_STS_B 0xD7
293#define TPS80031_INT_MSK_STS_C 0xD8
294#define TPS80031_TOGGLE1 0x90
295#define TPS80031_TOGGLE2 0x91
296#define TPS80031_TOGGLE3 0x92
297#define TPS80031_PWDNSTATUS1 0x93
298#define TPS80031_PWDNSTATUS2 0x94
299#define TPS80031_VALIDITY0 0x17
300#define TPS80031_VALIDITY1 0x18
301#define TPS80031_VALIDITY2 0x19
302#define TPS80031_VALIDITY3 0x1A
303#define TPS80031_VALIDITY4 0x1B
304#define TPS80031_VALIDITY5 0x1C
305#define TPS80031_VALIDITY6 0x1D
306#define TPS80031_VALIDITY7 0x1E
307
308/* Version number related register */
309#define TPS80031_JTAGVERNUM 0x87
310#define TPS80031_EPROM_REV 0xDF
311
312/* GPADC Trimming Bits. */
313#define TPS80031_GPADC_TRIM0 0xCC
314#define TPS80031_GPADC_TRIM1 0xCD
315#define TPS80031_GPADC_TRIM2 0xCE
316#define TPS80031_GPADC_TRIM3 0xCF
317#define TPS80031_GPADC_TRIM4 0xD0
318#define TPS80031_GPADC_TRIM5 0xD1
319#define TPS80031_GPADC_TRIM6 0xD2
320#define TPS80031_GPADC_TRIM7 0xD3
321#define TPS80031_GPADC_TRIM8 0xD4
322#define TPS80031_GPADC_TRIM9 0xD5
323#define TPS80031_GPADC_TRIM10 0xD6
324#define TPS80031_GPADC_TRIM11 0xD7
325#define TPS80031_GPADC_TRIM12 0xD8
326#define TPS80031_GPADC_TRIM13 0xD9
327#define TPS80031_GPADC_TRIM14 0xDA
328#define TPS80031_GPADC_TRIM15 0xDB
329#define TPS80031_GPADC_TRIM16 0xDC
330#define TPS80031_GPADC_TRIM17 0xDD
331#define TPS80031_GPADC_TRIM18 0xDE
332
333/* TPS80031_CONTROLLER_STAT1 bit fields */
334#define TPS80031_CONTROLLER_STAT1_BAT_TEMP 0
335#define TPS80031_CONTROLLER_STAT1_BAT_REMOVED 1
336#define TPS80031_CONTROLLER_STAT1_VBUS_DET 2
337#define TPS80031_CONTROLLER_STAT1_VAC_DET 3
338#define TPS80031_CONTROLLER_STAT1_FAULT_WDG 4
339#define TPS80031_CONTROLLER_STAT1_LINCH_GATED 6
340/* TPS80031_CONTROLLER_INT_MASK bit filed */
341#define TPS80031_CONTROLLER_INT_MASK_MVAC_DET 0
342#define TPS80031_CONTROLLER_INT_MASK_MVBUS_DET 1
343#define TPS80031_CONTROLLER_INT_MASK_MBAT_TEMP 2
344#define TPS80031_CONTROLLER_INT_MASK_MFAULT_WDG 3
345#define TPS80031_CONTROLLER_INT_MASK_MBAT_REMOVED 4
346#define TPS80031_CONTROLLER_INT_MASK_MLINCH_GATED 5
347
348#define TPS80031_CHARGE_CONTROL_SUB_INT_MASK 0x3F
349
350/* TPS80031_PHOENIX_DEV_ON bit field */
351#define TPS80031_DEVOFF 0x1
352
353#define TPS80031_EXT_CONTROL_CFG_TRANS 0
354#define TPS80031_EXT_CONTROL_CFG_STATE 1
355
356/* State register field */
357#define TPS80031_STATE_OFF 0x00
358#define TPS80031_STATE_ON 0x01
359#define TPS80031_STATE_MASK 0x03
360
361/* Trans register field */
362#define TPS80031_TRANS_ACTIVE_OFF 0x00
363#define TPS80031_TRANS_ACTIVE_ON 0x01
364#define TPS80031_TRANS_ACTIVE_MASK 0x03
365#define TPS80031_TRANS_SLEEP_OFF 0x00
366#define TPS80031_TRANS_SLEEP_ON 0x04
367#define TPS80031_TRANS_SLEEP_MASK 0x0C
368#define TPS80031_TRANS_OFF_OFF 0x00
369#define TPS80031_TRANS_OFF_ACTIVE 0x10
370#define TPS80031_TRANS_OFF_MASK 0x30
371
372#define TPS80031_EXT_PWR_REQ (TPS80031_PWR_REQ_INPUT_PREQ1 | \
373 TPS80031_PWR_REQ_INPUT_PREQ2 | \
374 TPS80031_PWR_REQ_INPUT_PREQ3)
375
376/* TPS80031_BBSPOR_CFG bit field */
377#define TPS80031_BBSPOR_CHG_EN 0x8
378#define TPS80031_MAX_REGISTER 0xFF
379
380struct i2c_client;
381
382/* Supported chips */
383enum chips {
384 TPS80031 = 0x00000001,
385 TPS80032 = 0x00000002,
386};
387
388enum {
389 TPS80031_INT_PWRON,
390 TPS80031_INT_RPWRON,
391 TPS80031_INT_SYS_VLOW,
392 TPS80031_INT_RTC_ALARM,
393 TPS80031_INT_RTC_PERIOD,
394 TPS80031_INT_HOT_DIE,
395 TPS80031_INT_VXX_SHORT,
396 TPS80031_INT_SPDURATION,
397 TPS80031_INT_WATCHDOG,
398 TPS80031_INT_BAT,
399 TPS80031_INT_SIM,
400 TPS80031_INT_MMC,
401 TPS80031_INT_RES,
402 TPS80031_INT_GPADC_RT,
403 TPS80031_INT_GPADC_SW2_EOC,
404 TPS80031_INT_CC_AUTOCAL,
405 TPS80031_INT_ID_WKUP,
406 TPS80031_INT_VBUSS_WKUP,
407 TPS80031_INT_ID,
408 TPS80031_INT_VBUS,
409 TPS80031_INT_CHRG_CTRL,
410 TPS80031_INT_EXT_CHRG,
411 TPS80031_INT_INT_CHRG,
412 TPS80031_INT_RES2,
413 TPS80031_INT_BAT_TEMP_OVRANGE,
414 TPS80031_INT_BAT_REMOVED,
415 TPS80031_INT_VBUS_DET,
416 TPS80031_INT_VAC_DET,
417 TPS80031_INT_FAULT_WDG,
418 TPS80031_INT_LINCH_GATED,
419
420 /* Last interrupt id to get the end number */
421 TPS80031_INT_NR,
422};
423
424/* TPS80031 Slave IDs */
425#define TPS80031_NUM_SLAVES 4
426#define TPS80031_SLAVE_ID0 0
427#define TPS80031_SLAVE_ID1 1
428#define TPS80031_SLAVE_ID2 2
429#define TPS80031_SLAVE_ID3 3
430
431/* TPS80031 I2C addresses */
432#define TPS80031_I2C_ID0_ADDR 0x12
433#define TPS80031_I2C_ID1_ADDR 0x48
434#define TPS80031_I2C_ID2_ADDR 0x49
435#define TPS80031_I2C_ID3_ADDR 0x4A
436
437enum {
438 TPS80031_REGULATOR_VIO,
439 TPS80031_REGULATOR_SMPS1,
440 TPS80031_REGULATOR_SMPS2,
441 TPS80031_REGULATOR_SMPS3,
442 TPS80031_REGULATOR_SMPS4,
443 TPS80031_REGULATOR_VANA,
444 TPS80031_REGULATOR_LDO1,
445 TPS80031_REGULATOR_LDO2,
446 TPS80031_REGULATOR_LDO3,
447 TPS80031_REGULATOR_LDO4,
448 TPS80031_REGULATOR_LDO5,
449 TPS80031_REGULATOR_LDO6,
450 TPS80031_REGULATOR_LDO7,
451 TPS80031_REGULATOR_LDOLN,
452 TPS80031_REGULATOR_LDOUSB,
453 TPS80031_REGULATOR_VBUS,
454 TPS80031_REGULATOR_REGEN1,
455 TPS80031_REGULATOR_REGEN2,
456 TPS80031_REGULATOR_SYSEN,
457 TPS80031_REGULATOR_MAX,
458};
459
460/* Different configurations for the rails */
461enum {
462 /* USBLDO input selection */
463 TPS80031_USBLDO_INPUT_VSYS = 0x00000001,
464 TPS80031_USBLDO_INPUT_PMID = 0x00000002,
465
466 /* LDO3 output mode */
467 TPS80031_LDO3_OUTPUT_VIB = 0x00000004,
468
469 /* VBUS configuration */
470 TPS80031_VBUS_DISCHRG_EN_PDN = 0x00000004,
471 TPS80031_VBUS_SW_ONLY = 0x00000008,
472 TPS80031_VBUS_SW_N_ID = 0x00000010,
473};
474
475/* External controls requests */
476enum tps80031_ext_control {
477 TPS80031_PWR_REQ_INPUT_NONE = 0x00000000,
478 TPS80031_PWR_REQ_INPUT_PREQ1 = 0x00000001,
479 TPS80031_PWR_REQ_INPUT_PREQ2 = 0x00000002,
480 TPS80031_PWR_REQ_INPUT_PREQ3 = 0x00000004,
481 TPS80031_PWR_OFF_ON_SLEEP = 0x00000008,
482 TPS80031_PWR_ON_ON_SLEEP = 0x00000010,
483};
484
485enum tps80031_pupd_pins {
486 TPS80031_PREQ1 = 0,
487 TPS80031_PREQ2A,
488 TPS80031_PREQ2B,
489 TPS80031_PREQ2C,
490 TPS80031_PREQ3,
491 TPS80031_NRES_WARM,
492 TPS80031_PWM_FORCE,
493 TPS80031_CHRG_EXT_CHRG_STATZ,
494 TPS80031_SIM,
495 TPS80031_MMC,
496 TPS80031_GPADC_START,
497 TPS80031_DVSI2C_SCL,
498 TPS80031_DVSI2C_SDA,
499 TPS80031_CTLI2C_SCL,
500 TPS80031_CTLI2C_SDA,
501};
502
503enum tps80031_pupd_settings {
504 TPS80031_PUPD_NORMAL,
505 TPS80031_PUPD_PULLDOWN,
506 TPS80031_PUPD_PULLUP,
507};
508
509struct tps80031 {
510 struct device *dev;
511 unsigned long chip_info;
512 int es_version;
513 struct i2c_client *clients[TPS80031_NUM_SLAVES];
514 struct regmap *regmap[TPS80031_NUM_SLAVES];
515 struct regmap_irq_chip_data *irq_data;
516};
517
518struct tps80031_pupd_init_data {
519 int input_pin;
520 int setting;
521};
522
523/*
524 * struct tps80031_regulator_platform_data - tps80031 regulator platform data.
525 *
526 * @reg_init_data: The regulator init data.
527 * @ext_ctrl_flag: External control flag for sleep/power request control.
528 * @config_flags: Configuration flag to configure the rails.
529 * It should be ORed of config enums.
530 */
531
532struct tps80031_regulator_platform_data {
533 struct regulator_init_data *reg_init_data;
534 unsigned int ext_ctrl_flag;
535 unsigned int config_flags;
536};
537
538struct tps80031_platform_data {
539 int irq_base;
540 bool use_power_off;
541 struct tps80031_pupd_init_data *pupd_init_data;
542 int pupd_init_data_size;
543 struct tps80031_regulator_platform_data
544 *regulator_pdata[TPS80031_REGULATOR_MAX];
545};
546
547static inline int tps80031_write(struct device *dev, int sid,
548 int reg, uint8_t val)
549{
550 struct tps80031 *tps80031 = dev_get_drvdata(dev);
551
552 return regmap_write(tps80031->regmap[sid], reg, val);
553}
554
555static inline int tps80031_writes(struct device *dev, int sid, int reg,
556 int len, uint8_t *val)
557{
558 struct tps80031 *tps80031 = dev_get_drvdata(dev);
559
560 return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
561}
562
563static inline int tps80031_read(struct device *dev, int sid,
564 int reg, uint8_t *val)
565{
566 struct tps80031 *tps80031 = dev_get_drvdata(dev);
567 unsigned int ival;
568 int ret;
569
570 ret = regmap_read(tps80031->regmap[sid], reg, &ival);
571 if (ret < 0) {
572 dev_err(dev, "failed reading from reg 0x%02x\n", reg);
573 return ret;
574 }
575
576 *val = ival;
577 return ret;
578}
579
580static inline int tps80031_reads(struct device *dev, int sid,
581 int reg, int len, uint8_t *val)
582{
583 struct tps80031 *tps80031 = dev_get_drvdata(dev);
584
585 return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
586}
587
588static inline int tps80031_set_bits(struct device *dev, int sid,
589 int reg, uint8_t bit_mask)
590{
591 struct tps80031 *tps80031 = dev_get_drvdata(dev);
592
593 return regmap_update_bits(tps80031->regmap[sid], reg,
594 bit_mask, bit_mask);
595}
596
597static inline int tps80031_clr_bits(struct device *dev, int sid,
598 int reg, uint8_t bit_mask)
599{
600 struct tps80031 *tps80031 = dev_get_drvdata(dev);
601
602 return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
603}
604
605static inline int tps80031_update(struct device *dev, int sid,
606 int reg, uint8_t val, uint8_t mask)
607{
608 struct tps80031 *tps80031 = dev_get_drvdata(dev);
609
610 return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
611}
612
613static inline unsigned long tps80031_get_chip_info(struct device *dev)
614{
615 struct tps80031 *tps80031 = dev_get_drvdata(dev);
616
617 return tps80031->chip_info;
618}
619
620static inline int tps80031_get_pmu_version(struct device *dev)
621{
622 struct tps80031 *tps80031 = dev_get_drvdata(dev);
623
624 return tps80031->es_version;
625}
626
627static inline int tps80031_irq_get_virq(struct device *dev, int irq)
628{
629 struct tps80031 *tps80031 = dev_get_drvdata(dev);
630
631 return regmap_irq_get_virq(tps80031->irq_data, irq);
632}
633
634extern int tps80031_ext_power_req_config(struct device *dev,
635 unsigned long ext_ctrl_flag, int preq_bit,
636 int state_reg_add, int trans_reg_add);
637#endif /*__LINUX_MFD_TPS80031_H */
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index a8eff4ad9be5..94ac944d12f0 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -207,10 +207,12 @@ struct twl6040_platform_data {
207}; 207};
208 208
209struct regmap; 209struct regmap;
210struct regmap_irq_chips_data;
210 211
211struct twl6040 { 212struct twl6040 {
212 struct device *dev; 213 struct device *dev;
213 struct regmap *regmap; 214 struct regmap *regmap;
215 struct regmap_irq_chip_data *irq_data;
214 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */ 216 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
215 struct mutex mutex; 217 struct mutex mutex;
216 struct mutex irq_mutex; 218 struct mutex irq_mutex;
@@ -228,9 +230,8 @@ struct twl6040 {
228 unsigned int mclk; 230 unsigned int mclk;
229 231
230 unsigned int irq; 232 unsigned int irq;
231 unsigned int irq_base; 233 unsigned int irq_ready;
232 u8 irq_masks_cur; 234 unsigned int irq_th;
233 u8 irq_masks_cache;
234}; 235};
235 236
236int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg); 237int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
@@ -245,8 +246,7 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
245 unsigned int freq_in, unsigned int freq_out); 246 unsigned int freq_in, unsigned int freq_out);
246int twl6040_get_pll(struct twl6040 *twl6040); 247int twl6040_get_pll(struct twl6040 *twl6040);
247unsigned int twl6040_get_sysclk(struct twl6040 *twl6040); 248unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
248int twl6040_irq_init(struct twl6040 *twl6040); 249
249void twl6040_irq_exit(struct twl6040 *twl6040);
250/* Get the combined status of the vibra control register */ 250/* Get the combined status of the vibra control register */
251int twl6040_get_vibralr_status(struct twl6040 *twl6040); 251int twl6040_get_vibralr_status(struct twl6040 *twl6040);
252 252
diff --git a/include/linux/mfd/viperboard.h b/include/linux/mfd/viperboard.h
new file mode 100644
index 000000000000..193452848c04
--- /dev/null
+++ b/include/linux/mfd/viperboard.h
@@ -0,0 +1,110 @@
1/*
2 * include/linux/mfd/viperboard.h
3 *
4 * Nano River Technologies viperboard definitions
5 *
6 * (C) 2012 by Lemonage GmbH
7 * Author: Lars Poeschel <poeschel@lemonage.de>
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MFD_VIPERBOARD_H__
18#define __MFD_VIPERBOARD_H__
19
20#include <linux/types.h>
21#include <linux/usb.h>
22
23#define VPRBRD_EP_OUT 0x02
24#define VPRBRD_EP_IN 0x86
25
26#define VPRBRD_I2C_MSG_LEN 512 /* max length of a msg on USB level */
27
28#define VPRBRD_I2C_FREQ_6MHZ 1 /* 6 MBit/s */
29#define VPRBRD_I2C_FREQ_3MHZ 2 /* 3 MBit/s */
30#define VPRBRD_I2C_FREQ_1MHZ 3 /* 1 MBit/s */
31#define VPRBRD_I2C_FREQ_FAST 4 /* 400 kbit/s */
32#define VPRBRD_I2C_FREQ_400KHZ VPRBRD_I2C_FREQ_FAST
33#define VPRBRD_I2C_FREQ_200KHZ 5 /* 200 kbit/s */
34#define VPRBRD_I2C_FREQ_STD 6 /* 100 kbit/s */
35#define VPRBRD_I2C_FREQ_100KHZ VPRBRD_I2C_FREQ_STD
36#define VPRBRD_I2C_FREQ_10KHZ 7 /* 10 kbit/s */
37
38#define VPRBRD_I2C_CMD_WRITE 0x00
39#define VPRBRD_I2C_CMD_READ 0x01
40#define VPRBRD_I2C_CMD_ADDR 0x02
41
42#define VPRBRD_USB_TYPE_OUT 0x40
43#define VPRBRD_USB_TYPE_IN 0xc0
44#define VPRBRD_USB_TIMEOUT_MS 100
45#define VPRBRD_USB_REQUEST_I2C_FREQ 0xe6
46#define VPRBRD_USB_REQUEST_I2C 0xe9
47#define VPRBRD_USB_REQUEST_MAJOR 0xea
48#define VPRBRD_USB_REQUEST_MINOR 0xeb
49#define VPRBRD_USB_REQUEST_ADC 0xec
50#define VPRBRD_USB_REQUEST_GPIOA 0xed
51#define VPRBRD_USB_REQUEST_GPIOB 0xdd
52
53struct vprbrd_i2c_write_hdr {
54 u8 cmd;
55 u16 addr;
56 u8 len1;
57 u8 len2;
58 u8 last;
59 u8 chan;
60 u16 spi;
61} __packed;
62
63struct vprbrd_i2c_read_hdr {
64 u8 cmd;
65 u16 addr;
66 u8 len0;
67 u8 len1;
68 u8 len2;
69 u8 len3;
70 u8 len4;
71 u8 len5;
72 u16 tf1; /* transfer 1 length */
73 u16 tf2; /* transfer 2 length */
74} __packed;
75
76struct vprbrd_i2c_status {
77 u8 unknown[11];
78 u8 status;
79} __packed;
80
81struct vprbrd_i2c_write_msg {
82 struct vprbrd_i2c_write_hdr header;
83 u8 data[VPRBRD_I2C_MSG_LEN
84 - sizeof(struct vprbrd_i2c_write_hdr)];
85} __packed;
86
87struct vprbrd_i2c_read_msg {
88 struct vprbrd_i2c_read_hdr header;
89 u8 data[VPRBRD_I2C_MSG_LEN
90 - sizeof(struct vprbrd_i2c_read_hdr)];
91} __packed;
92
93struct vprbrd_i2c_addr_msg {
94 u8 cmd;
95 u8 addr;
96 u8 unknown1;
97 u16 len;
98 u8 unknown2;
99 u8 unknown3;
100} __packed;
101
102/* Structure to hold all device specific stuff */
103struct vprbrd {
104 struct usb_device *usb_dev; /* the usb device for this device */
105 struct mutex lock;
106 u8 buf[sizeof(struct vprbrd_i2c_write_msg)];
107 struct platform_device pdev;
108};
109
110#endif /* __MFD_VIPERBOARD_H__ */
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index 1f173306bf05..ae5c249530b4 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -19,6 +19,8 @@
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/regmap.h> 20#include <linux/regmap.h>
21 21
22#include <linux/mfd/wm8994/pdata.h>
23
22enum wm8994_type { 24enum wm8994_type {
23 WM8994 = 0, 25 WM8994 = 0,
24 WM8958 = 1, 26 WM8958 = 1,
@@ -55,6 +57,8 @@ struct regulator_bulk_data;
55struct wm8994 { 57struct wm8994 {
56 struct mutex irq_lock; 58 struct mutex irq_lock;
57 59
60 struct wm8994_pdata pdata;
61
58 enum wm8994_type type; 62 enum wm8994_type type;
59 int revision; 63 int revision;
60 int cust_id; 64 int cust_id;
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index fc87be4fdc25..8e21a094836d 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -176,6 +176,11 @@ struct wm8994_pdata {
176 unsigned int lineout1fb:1; 176 unsigned int lineout1fb:1;
177 unsigned int lineout2fb:1; 177 unsigned int lineout2fb:1;
178 178
179 /* Delay between detecting a jack and starting microphone
180 * detect (specified in ms)
181 */
182 int micdet_delay;
183
179 /* IRQ for microphone detection if brought out directly as a 184 /* IRQ for microphone detection if brought out directly as a
180 * signal. 185 * signal.
181 */ 186 */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 08:24:27 -0500