1 files changed, 61 insertions, 0 deletions

diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 2ff15195f73d..2e1fbde020ca 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -31,6 +31,7 @@
 #include <linux/list.h>
 #include <linux/iommu.h>
 #include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/dmar.h>
 
 #include <asm/cacheflush.h>
 #include <asm/iommu.h>
@@ -387,6 +388,42 @@ struct pasid_entry;
 struct pasid_state_entry;
 struct page_req_dsc;
 
+struct dmar_domain {
+        int     nid;                    /* node id */
+
+        unsigned        iommu_refcnt[DMAR_UNITS_SUPPORTED];
+                                        /* Refcount of devices per iommu */
+
+
+        u16             iommu_did[DMAR_UNITS_SUPPORTED];
+                                        /* Domain ids per IOMMU. Use u16 since
+                                         * domain ids are 16 bit wide according
+                                         * to VT-d spec, section 9.3 */
+
+        bool has_iotlb_device;
+        struct list_head devices;       /* all devices' list */
+        struct iova_domain iovad;       /* iova's that belong to this domain */
+
+        struct dma_pte  *pgd;           /* virtual address */
+        int             gaw;            /* max guest address width */
+
+        /* adjusted guest address width, 0 is level 2 30-bit */
+        int             agaw;
+
+        int             flags;          /* flags to find out type of domain */
+
+        int             iommu_coherency;/* indicate coherency of iommu access */
+        int             iommu_snooping; /* indicate snooping control feature*/
+        int             iommu_count;    /* reference count of iommu */
+        int             iommu_superpage;/* Level of superpages supported:
+                                           0 == 4KiB (no superpages), 1 == 2MiB,
+                                           2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
+        u64             max_addr;       /* maximum mapped address */
+
+        struct iommu_domain domain;     /* generic domain data structure for
+                                           iommu core */
+};
+
 struct intel_iommu {
         void __iomem    *reg; /* Pointer to hardware regs, virtual addr */
         u64             reg_phys; /* physical address of hw register set */
@@ -435,6 +472,25 @@ struct intel_iommu {
         u32             flags;      /* Software defined flags */
 };
 
+/* PCI domain-device relationship */
+struct device_domain_info {
+        struct list_head link;  /* link to domain siblings */
+        struct list_head global; /* link to global list */
+        u8 bus;                 /* PCI bus number */
+        u8 devfn;               /* PCI devfn number */
+        u16 pfsid;              /* SRIOV physical function source ID */
+        u8 pasid_supported:3;
+        u8 pasid_enabled:1;
+        u8 pri_supported:1;
+        u8 pri_enabled:1;
+        u8 ats_supported:1;
+        u8 ats_enabled:1;
+        u8 ats_qdep;
+        struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
+        struct intel_iommu *iommu; /* IOMMU used by this device */
+        struct dmar_domain *domain; /* pointer to domain */
+};
+
 static inline void __iommu_flush_cache(
         struct intel_iommu *iommu, void *addr, int size)
 {
@@ -460,6 +516,11 @@ extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
 
 extern int dmar_ir_support(void);
 
+struct dmar_domain *get_valid_domain_for_dev(struct device *dev);
+void *alloc_pgtable_page(int node);
+void free_pgtable_page(void *vaddr);
+struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
+
 #ifdef CONFIG_INTEL_IOMMU_SVM
 extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
 extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);