diff options
Diffstat (limited to 'include/linux/firmware/imx')
| -rw-r--r-- | include/linux/firmware/imx/ipc.h | 59 | ||||
| -rw-r--r-- | include/linux/firmware/imx/sci.h | 16 | ||||
| -rw-r--r-- | include/linux/firmware/imx/types.h | 617 |
3 files changed, 692 insertions, 0 deletions
diff --git a/include/linux/firmware/imx/ipc.h b/include/linux/firmware/imx/ipc.h new file mode 100644 index 000000000000..6312c8cb084a --- /dev/null +++ b/include/linux/firmware/imx/ipc.h | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ | ||
| 2 | /* | ||
| 3 | * Copyright 2018 NXP | ||
| 4 | * | ||
| 5 | * Header file for the IPC implementation. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _SC_IPC_H | ||
| 9 | #define _SC_IPC_H | ||
| 10 | |||
| 11 | #include <linux/device.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | |||
| 14 | #define IMX_SC_RPC_VERSION 1 | ||
| 15 | #define IMX_SC_RPC_MAX_MSG 8 | ||
| 16 | |||
| 17 | struct imx_sc_ipc; | ||
| 18 | |||
| 19 | enum imx_sc_rpc_svc { | ||
| 20 | IMX_SC_RPC_SVC_UNKNOWN = 0, | ||
| 21 | IMX_SC_RPC_SVC_RETURN = 1, | ||
| 22 | IMX_SC_RPC_SVC_PM = 2, | ||
| 23 | IMX_SC_RPC_SVC_RM = 3, | ||
| 24 | IMX_SC_RPC_SVC_TIMER = 5, | ||
| 25 | IMX_SC_RPC_SVC_PAD = 6, | ||
| 26 | IMX_SC_RPC_SVC_MISC = 7, | ||
| 27 | IMX_SC_RPC_SVC_IRQ = 8, | ||
| 28 | IMX_SC_RPC_SVC_ABORT = 9 | ||
| 29 | }; | ||
| 30 | |||
| 31 | struct imx_sc_rpc_msg { | ||
| 32 | uint8_t ver; | ||
| 33 | uint8_t size; | ||
| 34 | uint8_t svc; | ||
| 35 | uint8_t func; | ||
| 36 | }; | ||
| 37 | |||
| 38 | /* | ||
| 39 | * This is an function to send an RPC message over an IPC channel. | ||
| 40 | * It is called by client-side SCFW API function shims. | ||
| 41 | * | ||
| 42 | * @param[in] ipc IPC handle | ||
| 43 | * @param[in,out] msg handle to a message | ||
| 44 | * @param[in] have_resp response flag | ||
| 45 | * | ||
| 46 | * If have_resp is true then this function waits for a response | ||
| 47 | * and returns the result in msg. | ||
| 48 | */ | ||
| 49 | int imx_scu_call_rpc(struct imx_sc_ipc *ipc, void *msg, bool have_resp); | ||
| 50 | |||
| 51 | /* | ||
| 52 | * This function gets the default ipc handle used by SCU | ||
| 53 | * | ||
| 54 | * @param[out] ipc sc ipc handle | ||
| 55 | * | ||
| 56 | * @return Returns an error code (0 = success, failed if < 0) | ||
| 57 | */ | ||
| 58 | int imx_scu_get_handle(struct imx_sc_ipc **ipc); | ||
| 59 | #endif /* _SC_IPC_H */ | ||
diff --git a/include/linux/firmware/imx/sci.h b/include/linux/firmware/imx/sci.h new file mode 100644 index 000000000000..ff3227ad8d7c --- /dev/null +++ b/include/linux/firmware/imx/sci.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ | ||
| 2 | /* | ||
| 3 | * Copyright (C) 2016 Freescale Semiconductor, Inc. | ||
| 4 | * Copyright 2017~2018 NXP | ||
| 5 | * | ||
| 6 | * Header file containing the public System Controller Interface (SCI) | ||
| 7 | * definitions. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _SC_SCI_H | ||
| 11 | #define _SC_SCI_H | ||
| 12 | |||
| 13 | #include <linux/firmware/imx/ipc.h> | ||
| 14 | #include <linux/firmware/imx/types.h> | ||
| 15 | |||
| 16 | #endif /* _SC_SCI_H */ | ||
diff --git a/include/linux/firmware/imx/types.h b/include/linux/firmware/imx/types.h new file mode 100644 index 000000000000..9cbf0c4a6069 --- /dev/null +++ b/include/linux/firmware/imx/types.h | |||
| @@ -0,0 +1,617 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ | ||
| 2 | /* | ||
| 3 | * Copyright (C) 2016 Freescale Semiconductor, Inc. | ||
| 4 | * Copyright 2017~2018 NXP | ||
| 5 | * | ||
| 6 | * Header file containing types used across multiple service APIs. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _SC_TYPES_H | ||
| 10 | #define _SC_TYPES_H | ||
| 11 | |||
| 12 | /* | ||
| 13 | * This type is used to indicate a resource. Resources include peripherals | ||
| 14 | * and bus masters (but not memory regions). Note items from list should | ||
| 15 | * never be changed or removed (only added to at the end of the list). | ||
| 16 | */ | ||
| 17 | enum imx_sc_rsrc { | ||
| 18 | IMX_SC_R_A53 = 0, | ||
| 19 | IMX_SC_R_A53_0 = 1, | ||
| 20 | IMX_SC_R_A53_1 = 2, | ||
| 21 | IMX_SC_R_A53_2 = 3, | ||
| 22 | IMX_SC_R_A53_3 = 4, | ||
| 23 | IMX_SC_R_A72 = 5, | ||
| 24 | IMX_SC_R_A72_0 = 6, | ||
| 25 | IMX_SC_R_A72_1 = 7, | ||
| 26 | IMX_SC_R_A72_2 = 8, | ||
| 27 | IMX_SC_R_A72_3 = 9, | ||
| 28 | IMX_SC_R_CCI = 10, | ||
| 29 | IMX_SC_R_DB = 11, | ||
| 30 | IMX_SC_R_DRC_0 = 12, | ||
| 31 | IMX_SC_R_DRC_1 = 13, | ||
| 32 | IMX_SC_R_GIC_SMMU = 14, | ||
| 33 | IMX_SC_R_IRQSTR_M4_0 = 15, | ||
| 34 | IMX_SC_R_IRQSTR_M4_1 = 16, | ||
| 35 | IMX_SC_R_SMMU = 17, | ||
| 36 | IMX_SC_R_GIC = 18, | ||
| 37 | IMX_SC_R_DC_0_BLIT0 = 19, | ||
| 38 | IMX_SC_R_DC_0_BLIT1 = 20, | ||
| 39 | IMX_SC_R_DC_0_BLIT2 = 21, | ||
| 40 | IMX_SC_R_DC_0_BLIT_OUT = 22, | ||
| 41 | IMX_SC_R_DC_0_CAPTURE0 = 23, | ||
| 42 | IMX_SC_R_DC_0_CAPTURE1 = 24, | ||
| 43 | IMX_SC_R_DC_0_WARP = 25, | ||
| 44 | IMX_SC_R_DC_0_INTEGRAL0 = 26, | ||
| 45 | IMX_SC_R_DC_0_INTEGRAL1 = 27, | ||
| 46 | IMX_SC_R_DC_0_VIDEO0 = 28, | ||
| 47 | IMX_SC_R_DC_0_VIDEO1 = 29, | ||
| 48 | IMX_SC_R_DC_0_FRAC0 = 30, | ||
| 49 | IMX_SC_R_DC_0_FRAC1 = 31, | ||
| 50 | IMX_SC_R_DC_0 = 32, | ||
| 51 | IMX_SC_R_GPU_2_PID0 = 33, | ||
| 52 | IMX_SC_R_DC_0_PLL_0 = 34, | ||
| 53 | IMX_SC_R_DC_0_PLL_1 = 35, | ||
| 54 | IMX_SC_R_DC_1_BLIT0 = 36, | ||
| 55 | IMX_SC_R_DC_1_BLIT1 = 37, | ||
| 56 | IMX_SC_R_DC_1_BLIT2 = 38, | ||
| 57 | IMX_SC_R_DC_1_BLIT_OUT = 39, | ||
| 58 | IMX_SC_R_DC_1_CAPTURE0 = 40, | ||
| 59 | IMX_SC_R_DC_1_CAPTURE1 = 41, | ||
| 60 | IMX_SC_R_DC_1_WARP = 42, | ||
| 61 | IMX_SC_R_DC_1_INTEGRAL0 = 43, | ||
| 62 | IMX_SC_R_DC_1_INTEGRAL1 = 44, | ||
| 63 | IMX_SC_R_DC_1_VIDEO0 = 45, | ||
| 64 | IMX_SC_R_DC_1_VIDEO1 = 46, | ||
| 65 | IMX_SC_R_DC_1_FRAC0 = 47, | ||
| 66 | IMX_SC_R_DC_1_FRAC1 = 48, | ||
| 67 | IMX_SC_R_DC_1 = 49, | ||
| 68 | IMX_SC_R_GPU_3_PID0 = 50, | ||
| 69 | IMX_SC_R_DC_1_PLL_0 = 51, | ||
| 70 | IMX_SC_R_DC_1_PLL_1 = 52, | ||
| 71 | IMX_SC_R_SPI_0 = 53, | ||
| 72 | IMX_SC_R_SPI_1 = 54, | ||
| 73 | IMX_SC_R_SPI_2 = 55, | ||
| 74 | IMX_SC_R_SPI_3 = 56, | ||
| 75 | IMX_SC_R_UART_0 = 57, | ||
| 76 | IMX_SC_R_UART_1 = 58, | ||
| 77 | IMX_SC_R_UART_2 = 59, | ||
| 78 | IMX_SC_R_UART_3 = 60, | ||
| 79 | IMX_SC_R_UART_4 = 61, | ||
| 80 | IMX_SC_R_EMVSIM_0 = 62, | ||
| 81 | IMX_SC_R_EMVSIM_1 = 63, | ||
| 82 | IMX_SC_R_DMA_0_CH0 = 64, | ||
| 83 | IMX_SC_R_DMA_0_CH1 = 65, | ||
| 84 | IMX_SC_R_DMA_0_CH2 = 66, | ||
| 85 | IMX_SC_R_DMA_0_CH3 = 67, | ||
| 86 | IMX_SC_R_DMA_0_CH4 = 68, | ||
| 87 | IMX_SC_R_DMA_0_CH5 = 69, | ||
| 88 | IMX_SC_R_DMA_0_CH6 = 70, | ||
| 89 | IMX_SC_R_DMA_0_CH7 = 71, | ||
| 90 | IMX_SC_R_DMA_0_CH8 = 72, | ||
| 91 | IMX_SC_R_DMA_0_CH9 = 73, | ||
| 92 | IMX_SC_R_DMA_0_CH10 = 74, | ||
| 93 | IMX_SC_R_DMA_0_CH11 = 75, | ||
| 94 | IMX_SC_R_DMA_0_CH12 = 76, | ||
| 95 | IMX_SC_R_DMA_0_CH13 = 77, | ||
| 96 | IMX_SC_R_DMA_0_CH14 = 78, | ||
| 97 | IMX_SC_R_DMA_0_CH15 = 79, | ||
| 98 | IMX_SC_R_DMA_0_CH16 = 80, | ||
| 99 | IMX_SC_R_DMA_0_CH17 = 81, | ||
| 100 | IMX_SC_R_DMA_0_CH18 = 82, | ||
| 101 | IMX_SC_R_DMA_0_CH19 = 83, | ||
| 102 | IMX_SC_R_DMA_0_CH20 = 84, | ||
| 103 | IMX_SC_R_DMA_0_CH21 = 85, | ||
| 104 | IMX_SC_R_DMA_0_CH22 = 86, | ||
| 105 | IMX_SC_R_DMA_0_CH23 = 87, | ||
| 106 | IMX_SC_R_DMA_0_CH24 = 88, | ||
| 107 | IMX_SC_R_DMA_0_CH25 = 89, | ||
| 108 | IMX_SC_R_DMA_0_CH26 = 90, | ||
| 109 | IMX_SC_R_DMA_0_CH27 = 91, | ||
| 110 | IMX_SC_R_DMA_0_CH28 = 92, | ||
| 111 | IMX_SC_R_DMA_0_CH29 = 93, | ||
| 112 | IMX_SC_R_DMA_0_CH30 = 94, | ||
| 113 | IMX_SC_R_DMA_0_CH31 = 95, | ||
| 114 | IMX_SC_R_I2C_0 = 96, | ||
| 115 | IMX_SC_R_I2C_1 = 97, | ||
| 116 | IMX_SC_R_I2C_2 = 98, | ||
| 117 | IMX_SC_R_I2C_3 = 99, | ||
| 118 | IMX_SC_R_I2C_4 = 100, | ||
| 119 | IMX_SC_R_ADC_0 = 101, | ||
| 120 | IMX_SC_R_ADC_1 = 102, | ||
| 121 | IMX_SC_R_FTM_0 = 103, | ||
| 122 | IMX_SC_R_FTM_1 = 104, | ||
| 123 | IMX_SC_R_CAN_0 = 105, | ||
| 124 | IMX_SC_R_CAN_1 = 106, | ||
| 125 | IMX_SC_R_CAN_2 = 107, | ||
| 126 | IMX_SC_R_DMA_1_CH0 = 108, | ||
| 127 | IMX_SC_R_DMA_1_CH1 = 109, | ||
| 128 | IMX_SC_R_DMA_1_CH2 = 110, | ||
| 129 | IMX_SC_R_DMA_1_CH3 = 111, | ||
| 130 | IMX_SC_R_DMA_1_CH4 = 112, | ||
| 131 | IMX_SC_R_DMA_1_CH5 = 113, | ||
| 132 | IMX_SC_R_DMA_1_CH6 = 114, | ||
| 133 | IMX_SC_R_DMA_1_CH7 = 115, | ||
| 134 | IMX_SC_R_DMA_1_CH8 = 116, | ||
| 135 | IMX_SC_R_DMA_1_CH9 = 117, | ||
| 136 | IMX_SC_R_DMA_1_CH10 = 118, | ||
| 137 | IMX_SC_R_DMA_1_CH11 = 119, | ||
| 138 | IMX_SC_R_DMA_1_CH12 = 120, | ||
| 139 | IMX_SC_R_DMA_1_CH13 = 121, | ||
| 140 | IMX_SC_R_DMA_1_CH14 = 122, | ||
| 141 | IMX_SC_R_DMA_1_CH15 = 123, | ||
| 142 | IMX_SC_R_DMA_1_CH16 = 124, | ||
| 143 | IMX_SC_R_DMA_1_CH17 = 125, | ||
| 144 | IMX_SC_R_DMA_1_CH18 = 126, | ||
| 145 | IMX_SC_R_DMA_1_CH19 = 127, | ||
| 146 | IMX_SC_R_DMA_1_CH20 = 128, | ||
| 147 | IMX_SC_R_DMA_1_CH21 = 129, | ||
| 148 | IMX_SC_R_DMA_1_CH22 = 130, | ||
| 149 | IMX_SC_R_DMA_1_CH23 = 131, | ||
| 150 | IMX_SC_R_DMA_1_CH24 = 132, | ||
| 151 | IMX_SC_R_DMA_1_CH25 = 133, | ||
| 152 | IMX_SC_R_DMA_1_CH26 = 134, | ||
| 153 | IMX_SC_R_DMA_1_CH27 = 135, | ||
| 154 | IMX_SC_R_DMA_1_CH28 = 136, | ||
| 155 | IMX_SC_R_DMA_1_CH29 = 137, | ||
| 156 | IMX_SC_R_DMA_1_CH30 = 138, | ||
| 157 | IMX_SC_R_DMA_1_CH31 = 139, | ||
| 158 | IMX_SC_R_UNUSED1 = 140, | ||
| 159 | IMX_SC_R_UNUSED2 = 141, | ||
| 160 | IMX_SC_R_UNUSED3 = 142, | ||
| 161 | IMX_SC_R_UNUSED4 = 143, | ||
| 162 | IMX_SC_R_GPU_0_PID0 = 144, | ||
| 163 | IMX_SC_R_GPU_0_PID1 = 145, | ||
| 164 | IMX_SC_R_GPU_0_PID2 = 146, | ||
| 165 | IMX_SC_R_GPU_0_PID3 = 147, | ||
| 166 | IMX_SC_R_GPU_1_PID0 = 148, | ||
| 167 | IMX_SC_R_GPU_1_PID1 = 149, | ||
| 168 | IMX_SC_R_GPU_1_PID2 = 150, | ||
| 169 | IMX_SC_R_GPU_1_PID3 = 151, | ||
| 170 | IMX_SC_R_PCIE_A = 152, | ||
| 171 | IMX_SC_R_SERDES_0 = 153, | ||
| 172 | IMX_SC_R_MATCH_0 = 154, | ||
| 173 | IMX_SC_R_MATCH_1 = 155, | ||
| 174 | IMX_SC_R_MATCH_2 = 156, | ||
| 175 | IMX_SC_R_MATCH_3 = 157, | ||
| 176 | IMX_SC_R_MATCH_4 = 158, | ||
| 177 | IMX_SC_R_MATCH_5 = 159, | ||
| 178 | IMX_SC_R_MATCH_6 = 160, | ||
| 179 | IMX_SC_R_MATCH_7 = 161, | ||
| 180 | IMX_SC_R_MATCH_8 = 162, | ||
| 181 | IMX_SC_R_MATCH_9 = 163, | ||
| 182 | IMX_SC_R_MATCH_10 = 164, | ||
| 183 | IMX_SC_R_MATCH_11 = 165, | ||
| 184 | IMX_SC_R_MATCH_12 = 166, | ||
| 185 | IMX_SC_R_MATCH_13 = 167, | ||
| 186 | IMX_SC_R_MATCH_14 = 168, | ||
| 187 | IMX_SC_R_PCIE_B = 169, | ||
| 188 | IMX_SC_R_SATA_0 = 170, | ||
| 189 | IMX_SC_R_SERDES_1 = 171, | ||
| 190 | IMX_SC_R_HSIO_GPIO = 172, | ||
| 191 | IMX_SC_R_MATCH_15 = 173, | ||
| 192 | IMX_SC_R_MATCH_16 = 174, | ||
| 193 | IMX_SC_R_MATCH_17 = 175, | ||
| 194 | IMX_SC_R_MATCH_18 = 176, | ||
| 195 | IMX_SC_R_MATCH_19 = 177, | ||
| 196 | IMX_SC_R_MATCH_20 = 178, | ||
| 197 | IMX_SC_R_MATCH_21 = 179, | ||
| 198 | IMX_SC_R_MATCH_22 = 180, | ||
| 199 | IMX_SC_R_MATCH_23 = 181, | ||
| 200 | IMX_SC_R_MATCH_24 = 182, | ||
| 201 | IMX_SC_R_MATCH_25 = 183, | ||
| 202 | IMX_SC_R_MATCH_26 = 184, | ||
| 203 | IMX_SC_R_MATCH_27 = 185, | ||
| 204 | IMX_SC_R_MATCH_28 = 186, | ||
| 205 | IMX_SC_R_LCD_0 = 187, | ||
| 206 | IMX_SC_R_LCD_0_PWM_0 = 188, | ||
| 207 | IMX_SC_R_LCD_0_I2C_0 = 189, | ||
| 208 | IMX_SC_R_LCD_0_I2C_1 = 190, | ||
| 209 | IMX_SC_R_PWM_0 = 191, | ||
| 210 | IMX_SC_R_PWM_1 = 192, | ||
| 211 | IMX_SC_R_PWM_2 = 193, | ||
| 212 | IMX_SC_R_PWM_3 = 194, | ||
| 213 | IMX_SC_R_PWM_4 = 195, | ||
| 214 | IMX_SC_R_PWM_5 = 196, | ||
| 215 | IMX_SC_R_PWM_6 = 197, | ||
| 216 | IMX_SC_R_PWM_7 = 198, | ||
| 217 | IMX_SC_R_GPIO_0 = 199, | ||
| 218 | IMX_SC_R_GPIO_1 = 200, | ||
| 219 | IMX_SC_R_GPIO_2 = 201, | ||
| 220 | IMX_SC_R_GPIO_3 = 202, | ||
| 221 | IMX_SC_R_GPIO_4 = 203, | ||
| 222 | IMX_SC_R_GPIO_5 = 204, | ||
| 223 | IMX_SC_R_GPIO_6 = 205, | ||
| 224 | IMX_SC_R_GPIO_7 = 206, | ||
| 225 | IMX_SC_R_GPT_0 = 207, | ||
| 226 | IMX_SC_R_GPT_1 = 208, | ||
| 227 | IMX_SC_R_GPT_2 = 209, | ||
| 228 | IMX_SC_R_GPT_3 = 210, | ||
| 229 | IMX_SC_R_GPT_4 = 211, | ||
| 230 | IMX_SC_R_KPP = 212, | ||
| 231 | IMX_SC_R_MU_0A = 213, | ||
| 232 | IMX_SC_R_MU_1A = 214, | ||
| 233 | IMX_SC_R_MU_2A = 215, | ||
| 234 | IMX_SC_R_MU_3A = 216, | ||
| 235 | IMX_SC_R_MU_4A = 217, | ||
| 236 | IMX_SC_R_MU_5A = 218, | ||
| 237 | IMX_SC_R_MU_6A = 219, | ||
| 238 | IMX_SC_R_MU_7A = 220, | ||
| 239 | IMX_SC_R_MU_8A = 221, | ||
| 240 | IMX_SC_R_MU_9A = 222, | ||
| 241 | IMX_SC_R_MU_10A = 223, | ||
| 242 | IMX_SC_R_MU_11A = 224, | ||
| 243 | IMX_SC_R_MU_12A = 225, | ||
| 244 | IMX_SC_R_MU_13A = 226, | ||
| 245 | IMX_SC_R_MU_5B = 227, | ||
| 246 | IMX_SC_R_MU_6B = 228, | ||
| 247 | IMX_SC_R_MU_7B = 229, | ||
| 248 | IMX_SC_R_MU_8B = 230, | ||
| 249 | IMX_SC_R_MU_9B = 231, | ||
| 250 | IMX_SC_R_MU_10B = 232, | ||
| 251 | IMX_SC_R_MU_11B = 233, | ||
| 252 | IMX_SC_R_MU_12B = 234, | ||
| 253 | IMX_SC_R_MU_13B = 235, | ||
| 254 | IMX_SC_R_ROM_0 = 236, | ||
| 255 | IMX_SC_R_FSPI_0 = 237, | ||
| 256 | IMX_SC_R_FSPI_1 = 238, | ||
| 257 | IMX_SC_R_IEE = 239, | ||
| 258 | IMX_SC_R_IEE_R0 = 240, | ||
| 259 | IMX_SC_R_IEE_R1 = 241, | ||
| 260 | IMX_SC_R_IEE_R2 = 242, | ||
| 261 | IMX_SC_R_IEE_R3 = 243, | ||
| 262 | IMX_SC_R_IEE_R4 = 244, | ||
| 263 | IMX_SC_R_IEE_R5 = 245, | ||
| 264 | IMX_SC_R_IEE_R6 = 246, | ||
| 265 | IMX_SC_R_IEE_R7 = 247, | ||
| 266 | IMX_SC_R_SDHC_0 = 248, | ||
| 267 | IMX_SC_R_SDHC_1 = 249, | ||
| 268 | IMX_SC_R_SDHC_2 = 250, | ||
| 269 | IMX_SC_R_ENET_0 = 251, | ||
| 270 | IMX_SC_R_ENET_1 = 252, | ||
| 271 | IMX_SC_R_MLB_0 = 253, | ||
| 272 | IMX_SC_R_DMA_2_CH0 = 254, | ||
| 273 | IMX_SC_R_DMA_2_CH1 = 255, | ||
| 274 | IMX_SC_R_DMA_2_CH2 = 256, | ||
| 275 | IMX_SC_R_DMA_2_CH3 = 257, | ||
| 276 | IMX_SC_R_DMA_2_CH4 = 258, | ||
| 277 | IMX_SC_R_USB_0 = 259, | ||
| 278 | IMX_SC_R_USB_1 = 260, | ||
| 279 | IMX_SC_R_USB_0_PHY = 261, | ||
| 280 | IMX_SC_R_USB_2 = 262, | ||
| 281 | IMX_SC_R_USB_2_PHY = 263, | ||
| 282 | IMX_SC_R_DTCP = 264, | ||
| 283 | IMX_SC_R_NAND = 265, | ||
| 284 | IMX_SC_R_LVDS_0 = 266, | ||
| 285 | IMX_SC_R_LVDS_0_PWM_0 = 267, | ||
| 286 | IMX_SC_R_LVDS_0_I2C_0 = 268, | ||
| 287 | IMX_SC_R_LVDS_0_I2C_1 = 269, | ||
| 288 | IMX_SC_R_LVDS_1 = 270, | ||
| 289 | IMX_SC_R_LVDS_1_PWM_0 = 271, | ||
| 290 | IMX_SC_R_LVDS_1_I2C_0 = 272, | ||
| 291 | IMX_SC_R_LVDS_1_I2C_1 = 273, | ||
| 292 | IMX_SC_R_LVDS_2 = 274, | ||
| 293 | IMX_SC_R_LVDS_2_PWM_0 = 275, | ||
| 294 | IMX_SC_R_LVDS_2_I2C_0 = 276, | ||
| 295 | IMX_SC_R_LVDS_2_I2C_1 = 277, | ||
| 296 | IMX_SC_R_M4_0_PID0 = 278, | ||
| 297 | IMX_SC_R_M4_0_PID1 = 279, | ||
| 298 | IMX_SC_R_M4_0_PID2 = 280, | ||
| 299 | IMX_SC_R_M4_0_PID3 = 281, | ||
| 300 | IMX_SC_R_M4_0_PID4 = 282, | ||
| 301 | IMX_SC_R_M4_0_RGPIO = 283, | ||
| 302 | IMX_SC_R_M4_0_SEMA42 = 284, | ||
| 303 | IMX_SC_R_M4_0_TPM = 285, | ||
| 304 | IMX_SC_R_M4_0_PIT = 286, | ||
| 305 | IMX_SC_R_M4_0_UART = 287, | ||
| 306 | IMX_SC_R_M4_0_I2C = 288, | ||
| 307 | IMX_SC_R_M4_0_INTMUX = 289, | ||
| 308 | IMX_SC_R_M4_0_SIM = 290, | ||
| 309 | IMX_SC_R_M4_0_WDOG = 291, | ||
| 310 | IMX_SC_R_M4_0_MU_0B = 292, | ||
| 311 | IMX_SC_R_M4_0_MU_0A0 = 293, | ||
| 312 | IMX_SC_R_M4_0_MU_0A1 = 294, | ||
| 313 | IMX_SC_R_M4_0_MU_0A2 = 295, | ||
| 314 | IMX_SC_R_M4_0_MU_0A3 = 296, | ||
| 315 | IMX_SC_R_M4_0_MU_1A = 297, | ||
| 316 | IMX_SC_R_M4_1_PID0 = 298, | ||
| 317 | IMX_SC_R_M4_1_PID1 = 299, | ||
| 318 | IMX_SC_R_M4_1_PID2 = 300, | ||
| 319 | IMX_SC_R_M4_1_PID3 = 301, | ||
| 320 | IMX_SC_R_M4_1_PID4 = 302, | ||
| 321 | IMX_SC_R_M4_1_RGPIO = 303, | ||
| 322 | IMX_SC_R_M4_1_SEMA42 = 304, | ||
| 323 | IMX_SC_R_M4_1_TPM = 305, | ||
| 324 | IMX_SC_R_M4_1_PIT = 306, | ||
| 325 | IMX_SC_R_M4_1_UART = 307, | ||
| 326 | IMX_SC_R_M4_1_I2C = 308, | ||
| 327 | IMX_SC_R_M4_1_INTMUX = 309, | ||
| 328 | IMX_SC_R_M4_1_SIM = 310, | ||
| 329 | IMX_SC_R_M4_1_WDOG = 311, | ||
| 330 | IMX_SC_R_M4_1_MU_0B = 312, | ||
| 331 | IMX_SC_R_M4_1_MU_0A0 = 313, | ||
| 332 | IMX_SC_R_M4_1_MU_0A1 = 314, | ||
| 333 | IMX_SC_R_M4_1_MU_0A2 = 315, | ||
| 334 | IMX_SC_R_M4_1_MU_0A3 = 316, | ||
| 335 | IMX_SC_R_M4_1_MU_1A = 317, | ||
| 336 | IMX_SC_R_SAI_0 = 318, | ||
| 337 | IMX_SC_R_SAI_1 = 319, | ||
| 338 | IMX_SC_R_SAI_2 = 320, | ||
| 339 | IMX_SC_R_IRQSTR_SCU2 = 321, | ||
| 340 | IMX_SC_R_IRQSTR_DSP = 322, | ||
| 341 | IMX_SC_R_UNUSED5 = 323, | ||
| 342 | IMX_SC_R_UNUSED6 = 324, | ||
| 343 | IMX_SC_R_AUDIO_PLL_0 = 325, | ||
| 344 | IMX_SC_R_PI_0 = 326, | ||
| 345 | IMX_SC_R_PI_0_PWM_0 = 327, | ||
| 346 | IMX_SC_R_PI_0_PWM_1 = 328, | ||
| 347 | IMX_SC_R_PI_0_I2C_0 = 329, | ||
| 348 | IMX_SC_R_PI_0_PLL = 330, | ||
| 349 | IMX_SC_R_PI_1 = 331, | ||
| 350 | IMX_SC_R_PI_1_PWM_0 = 332, | ||
| 351 | IMX_SC_R_PI_1_PWM_1 = 333, | ||
| 352 | IMX_SC_R_PI_1_I2C_0 = 334, | ||
| 353 | IMX_SC_R_PI_1_PLL = 335, | ||
| 354 | IMX_SC_R_SC_PID0 = 336, | ||
| 355 | IMX_SC_R_SC_PID1 = 337, | ||
| 356 | IMX_SC_R_SC_PID2 = 338, | ||
| 357 | IMX_SC_R_SC_PID3 = 339, | ||
| 358 | IMX_SC_R_SC_PID4 = 340, | ||
| 359 | IMX_SC_R_SC_SEMA42 = 341, | ||
| 360 | IMX_SC_R_SC_TPM = 342, | ||
| 361 | IMX_SC_R_SC_PIT = 343, | ||
| 362 | IMX_SC_R_SC_UART = 344, | ||
| 363 | IMX_SC_R_SC_I2C = 345, | ||
| 364 | IMX_SC_R_SC_MU_0B = 346, | ||
| 365 | IMX_SC_R_SC_MU_0A0 = 347, | ||
| 366 | IMX_SC_R_SC_MU_0A1 = 348, | ||
| 367 | IMX_SC_R_SC_MU_0A2 = 349, | ||
| 368 | IMX_SC_R_SC_MU_0A3 = 350, | ||
| 369 | IMX_SC_R_SC_MU_1A = 351, | ||
| 370 | IMX_SC_R_SYSCNT_RD = 352, | ||
| 371 | IMX_SC_R_SYSCNT_CMP = 353, | ||
| 372 | IMX_SC_R_DEBUG = 354, | ||
| 373 | IMX_SC_R_SYSTEM = 355, | ||
| 374 | IMX_SC_R_SNVS = 356, | ||
| 375 | IMX_SC_R_OTP = 357, | ||
| 376 | IMX_SC_R_VPU_PID0 = 358, | ||
| 377 | IMX_SC_R_VPU_PID1 = 359, | ||
| 378 | IMX_SC_R_VPU_PID2 = 360, | ||
| 379 | IMX_SC_R_VPU_PID3 = 361, | ||
| 380 | IMX_SC_R_VPU_PID4 = 362, | ||
| 381 | IMX_SC_R_VPU_PID5 = 363, | ||
| 382 | IMX_SC_R_VPU_PID6 = 364, | ||
| 383 | IMX_SC_R_VPU_PID7 = 365, | ||
| 384 | IMX_SC_R_VPU_UART = 366, | ||
| 385 | IMX_SC_R_VPUCORE = 367, | ||
| 386 | IMX_SC_R_VPUCORE_0 = 368, | ||
| 387 | IMX_SC_R_VPUCORE_1 = 369, | ||
| 388 | IMX_SC_R_VPUCORE_2 = 370, | ||
| 389 | IMX_SC_R_VPUCORE_3 = 371, | ||
| 390 | IMX_SC_R_DMA_4_CH0 = 372, | ||
| 391 | IMX_SC_R_DMA_4_CH1 = 373, | ||
| 392 | IMX_SC_R_DMA_4_CH2 = 374, | ||
| 393 | IMX_SC_R_DMA_4_CH3 = 375, | ||
| 394 | IMX_SC_R_DMA_4_CH4 = 376, | ||
| 395 | IMX_SC_R_ISI_CH0 = 377, | ||
| 396 | IMX_SC_R_ISI_CH1 = 378, | ||
| 397 | IMX_SC_R_ISI_CH2 = 379, | ||
| 398 | IMX_SC_R_ISI_CH3 = 380, | ||
| 399 | IMX_SC_R_ISI_CH4 = 381, | ||
| 400 | IMX_SC_R_ISI_CH5 = 382, | ||
| 401 | IMX_SC_R_ISI_CH6 = 383, | ||
| 402 | IMX_SC_R_ISI_CH7 = 384, | ||
| 403 | IMX_SC_R_MJPEG_DEC_S0 = 385, | ||
| 404 | IMX_SC_R_MJPEG_DEC_S1 = 386, | ||
| 405 | IMX_SC_R_MJPEG_DEC_S2 = 387, | ||
| 406 | IMX_SC_R_MJPEG_DEC_S3 = 388, | ||
| 407 | IMX_SC_R_MJPEG_ENC_S0 = 389, | ||
| 408 | IMX_SC_R_MJPEG_ENC_S1 = 390, | ||
| 409 | IMX_SC_R_MJPEG_ENC_S2 = 391, | ||
| 410 | IMX_SC_R_MJPEG_ENC_S3 = 392, | ||
| 411 | IMX_SC_R_MIPI_0 = 393, | ||
| 412 | IMX_SC_R_MIPI_0_PWM_0 = 394, | ||
| 413 | IMX_SC_R_MIPI_0_I2C_0 = 395, | ||
| 414 | IMX_SC_R_MIPI_0_I2C_1 = 396, | ||
| 415 | IMX_SC_R_MIPI_1 = 397, | ||
| 416 | IMX_SC_R_MIPI_1_PWM_0 = 398, | ||
| 417 | IMX_SC_R_MIPI_1_I2C_0 = 399, | ||
| 418 | IMX_SC_R_MIPI_1_I2C_1 = 400, | ||
| 419 | IMX_SC_R_CSI_0 = 401, | ||
| 420 | IMX_SC_R_CSI_0_PWM_0 = 402, | ||
| 421 | IMX_SC_R_CSI_0_I2C_0 = 403, | ||
| 422 | IMX_SC_R_CSI_1 = 404, | ||
| 423 | IMX_SC_R_CSI_1_PWM_0 = 405, | ||
| 424 | IMX_SC_R_CSI_1_I2C_0 = 406, | ||
| 425 | IMX_SC_R_HDMI = 407, | ||
| 426 | IMX_SC_R_HDMI_I2S = 408, | ||
| 427 | IMX_SC_R_HDMI_I2C_0 = 409, | ||
| 428 | IMX_SC_R_HDMI_PLL_0 = 410, | ||
| 429 | IMX_SC_R_HDMI_RX = 411, | ||
| 430 | IMX_SC_R_HDMI_RX_BYPASS = 412, | ||
| 431 | IMX_SC_R_HDMI_RX_I2C_0 = 413, | ||
| 432 | IMX_SC_R_ASRC_0 = 414, | ||
| 433 | IMX_SC_R_ESAI_0 = 415, | ||
| 434 | IMX_SC_R_SPDIF_0 = 416, | ||
| 435 | IMX_SC_R_SPDIF_1 = 417, | ||
| 436 | IMX_SC_R_SAI_3 = 418, | ||
| 437 | IMX_SC_R_SAI_4 = 419, | ||
| 438 | IMX_SC_R_SAI_5 = 420, | ||
| 439 | IMX_SC_R_GPT_5 = 421, | ||
| 440 | IMX_SC_R_GPT_6 = 422, | ||
| 441 | IMX_SC_R_GPT_7 = 423, | ||
| 442 | IMX_SC_R_GPT_8 = 424, | ||
| 443 | IMX_SC_R_GPT_9 = 425, | ||
| 444 | IMX_SC_R_GPT_10 = 426, | ||
| 445 | IMX_SC_R_DMA_2_CH5 = 427, | ||
| 446 | IMX_SC_R_DMA_2_CH6 = 428, | ||
| 447 | IMX_SC_R_DMA_2_CH7 = 429, | ||
| 448 | IMX_SC_R_DMA_2_CH8 = 430, | ||
| 449 | IMX_SC_R_DMA_2_CH9 = 431, | ||
| 450 | IMX_SC_R_DMA_2_CH10 = 432, | ||
| 451 | IMX_SC_R_DMA_2_CH11 = 433, | ||
| 452 | IMX_SC_R_DMA_2_CH12 = 434, | ||
| 453 | IMX_SC_R_DMA_2_CH13 = 435, | ||
| 454 | IMX_SC_R_DMA_2_CH14 = 436, | ||
| 455 | IMX_SC_R_DMA_2_CH15 = 437, | ||
| 456 | IMX_SC_R_DMA_2_CH16 = 438, | ||
| 457 | IMX_SC_R_DMA_2_CH17 = 439, | ||
| 458 | IMX_SC_R_DMA_2_CH18 = 440, | ||
| 459 | IMX_SC_R_DMA_2_CH19 = 441, | ||
| 460 | IMX_SC_R_DMA_2_CH20 = 442, | ||
| 461 | IMX_SC_R_DMA_2_CH21 = 443, | ||
| 462 | IMX_SC_R_DMA_2_CH22 = 444, | ||
| 463 | IMX_SC_R_DMA_2_CH23 = 445, | ||
| 464 | IMX_SC_R_DMA_2_CH24 = 446, | ||
| 465 | IMX_SC_R_DMA_2_CH25 = 447, | ||
| 466 | IMX_SC_R_DMA_2_CH26 = 448, | ||
| 467 | IMX_SC_R_DMA_2_CH27 = 449, | ||
| 468 | IMX_SC_R_DMA_2_CH28 = 450, | ||
| 469 | IMX_SC_R_DMA_2_CH29 = 451, | ||
| 470 | IMX_SC_R_DMA_2_CH30 = 452, | ||
| 471 | IMX_SC_R_DMA_2_CH31 = 453, | ||
| 472 | IMX_SC_R_ASRC_1 = 454, | ||
| 473 | IMX_SC_R_ESAI_1 = 455, | ||
| 474 | IMX_SC_R_SAI_6 = 456, | ||
| 475 | IMX_SC_R_SAI_7 = 457, | ||
| 476 | IMX_SC_R_AMIX = 458, | ||
| 477 | IMX_SC_R_MQS_0 = 459, | ||
| 478 | IMX_SC_R_DMA_3_CH0 = 460, | ||
| 479 | IMX_SC_R_DMA_3_CH1 = 461, | ||
| 480 | IMX_SC_R_DMA_3_CH2 = 462, | ||
| 481 | IMX_SC_R_DMA_3_CH3 = 463, | ||
| 482 | IMX_SC_R_DMA_3_CH4 = 464, | ||
| 483 | IMX_SC_R_DMA_3_CH5 = 465, | ||
| 484 | IMX_SC_R_DMA_3_CH6 = 466, | ||
| 485 | IMX_SC_R_DMA_3_CH7 = 467, | ||
| 486 | IMX_SC_R_DMA_3_CH8 = 468, | ||
| 487 | IMX_SC_R_DMA_3_CH9 = 469, | ||
| 488 | IMX_SC_R_DMA_3_CH10 = 470, | ||
| 489 | IMX_SC_R_DMA_3_CH11 = 471, | ||
| 490 | IMX_SC_R_DMA_3_CH12 = 472, | ||
| 491 | IMX_SC_R_DMA_3_CH13 = 473, | ||
| 492 | IMX_SC_R_DMA_3_CH14 = 474, | ||
| 493 | IMX_SC_R_DMA_3_CH15 = 475, | ||
| 494 | IMX_SC_R_DMA_3_CH16 = 476, | ||
| 495 | IMX_SC_R_DMA_3_CH17 = 477, | ||
| 496 | IMX_SC_R_DMA_3_CH18 = 478, | ||
| 497 | IMX_SC_R_DMA_3_CH19 = 479, | ||
| 498 | IMX_SC_R_DMA_3_CH20 = 480, | ||
| 499 | IMX_SC_R_DMA_3_CH21 = 481, | ||
| 500 | IMX_SC_R_DMA_3_CH22 = 482, | ||
| 501 | IMX_SC_R_DMA_3_CH23 = 483, | ||
| 502 | IMX_SC_R_DMA_3_CH24 = 484, | ||
| 503 | IMX_SC_R_DMA_3_CH25 = 485, | ||
| 504 | IMX_SC_R_DMA_3_CH26 = 486, | ||
| 505 | IMX_SC_R_DMA_3_CH27 = 487, | ||
| 506 | IMX_SC_R_DMA_3_CH28 = 488, | ||
| 507 | IMX_SC_R_DMA_3_CH29 = 489, | ||
| 508 | IMX_SC_R_DMA_3_CH30 = 490, | ||
| 509 | IMX_SC_R_DMA_3_CH31 = 491, | ||
| 510 | IMX_SC_R_AUDIO_PLL_1 = 492, | ||
| 511 | IMX_SC_R_AUDIO_CLK_0 = 493, | ||
| 512 | IMX_SC_R_AUDIO_CLK_1 = 494, | ||
| 513 | IMX_SC_R_MCLK_OUT_0 = 495, | ||
| 514 | IMX_SC_R_MCLK_OUT_1 = 496, | ||
| 515 | IMX_SC_R_PMIC_0 = 497, | ||
| 516 | IMX_SC_R_PMIC_1 = 498, | ||
| 517 | IMX_SC_R_SECO = 499, | ||
| 518 | IMX_SC_R_CAAM_JR1 = 500, | ||
| 519 | IMX_SC_R_CAAM_JR2 = 501, | ||
| 520 | IMX_SC_R_CAAM_JR3 = 502, | ||
| 521 | IMX_SC_R_SECO_MU_2 = 503, | ||
| 522 | IMX_SC_R_SECO_MU_3 = 504, | ||
| 523 | IMX_SC_R_SECO_MU_4 = 505, | ||
| 524 | IMX_SC_R_HDMI_RX_PWM_0 = 506, | ||
| 525 | IMX_SC_R_A35 = 507, | ||
| 526 | IMX_SC_R_A35_0 = 508, | ||
| 527 | IMX_SC_R_A35_1 = 509, | ||
| 528 | IMX_SC_R_A35_2 = 510, | ||
| 529 | IMX_SC_R_A35_3 = 511, | ||
| 530 | IMX_SC_R_DSP = 512, | ||
| 531 | IMX_SC_R_DSP_RAM = 513, | ||
| 532 | IMX_SC_R_CAAM_JR1_OUT = 514, | ||
| 533 | IMX_SC_R_CAAM_JR2_OUT = 515, | ||
| 534 | IMX_SC_R_CAAM_JR3_OUT = 516, | ||
| 535 | IMX_SC_R_VPU_DEC_0 = 517, | ||
| 536 | IMX_SC_R_VPU_ENC_0 = 518, | ||
| 537 | IMX_SC_R_CAAM_JR0 = 519, | ||
| 538 | IMX_SC_R_CAAM_JR0_OUT = 520, | ||
| 539 | IMX_SC_R_PMIC_2 = 521, | ||
| 540 | IMX_SC_R_DBLOGIC = 522, | ||
| 541 | IMX_SC_R_HDMI_PLL_1 = 523, | ||
| 542 | IMX_SC_R_BOARD_R0 = 524, | ||
| 543 | IMX_SC_R_BOARD_R1 = 525, | ||
| 544 | IMX_SC_R_BOARD_R2 = 526, | ||
| 545 | IMX_SC_R_BOARD_R3 = 527, | ||
| 546 | IMX_SC_R_BOARD_R4 = 528, | ||
| 547 | IMX_SC_R_BOARD_R5 = 529, | ||
| 548 | IMX_SC_R_BOARD_R6 = 530, | ||
| 549 | IMX_SC_R_BOARD_R7 = 531, | ||
| 550 | IMX_SC_R_MJPEG_DEC_MP = 532, | ||
| 551 | IMX_SC_R_MJPEG_ENC_MP = 533, | ||
| 552 | IMX_SC_R_VPU_TS_0 = 534, | ||
| 553 | IMX_SC_R_VPU_MU_0 = 535, | ||
| 554 | IMX_SC_R_VPU_MU_1 = 536, | ||
| 555 | IMX_SC_R_VPU_MU_2 = 537, | ||
| 556 | IMX_SC_R_VPU_MU_3 = 538, | ||
| 557 | IMX_SC_R_VPU_ENC_1 = 539, | ||
| 558 | IMX_SC_R_VPU = 540, | ||
| 559 | IMX_SC_R_LAST | ||
| 560 | }; | ||
| 561 | |||
| 562 | /* NOTE - please add by replacing some of the UNUSED from above! */ | ||
| 563 | |||
| 564 | /* | ||
| 565 | * This type is used to indicate a control. | ||
| 566 | */ | ||
| 567 | enum imx_sc_ctrl { | ||
| 568 | IMX_SC_C_TEMP = 0, | ||
| 569 | IMX_SC_C_TEMP_HI = 1, | ||
| 570 | IMX_SC_C_TEMP_LOW = 2, | ||
| 571 | IMX_SC_C_PXL_LINK_MST1_ADDR = 3, | ||
| 572 | IMX_SC_C_PXL_LINK_MST2_ADDR = 4, | ||
| 573 | IMX_SC_C_PXL_LINK_MST_ENB = 5, | ||
| 574 | IMX_SC_C_PXL_LINK_MST1_ENB = 6, | ||
| 575 | IMX_SC_C_PXL_LINK_MST2_ENB = 7, | ||
| 576 | IMX_SC_C_PXL_LINK_SLV1_ADDR = 8, | ||
| 577 | IMX_SC_C_PXL_LINK_SLV2_ADDR = 9, | ||
| 578 | IMX_SC_C_PXL_LINK_MST_VLD = 10, | ||
| 579 | IMX_SC_C_PXL_LINK_MST1_VLD = 11, | ||
| 580 | IMX_SC_C_PXL_LINK_MST2_VLD = 12, | ||
| 581 | IMX_SC_C_SINGLE_MODE = 13, | ||
| 582 | IMX_SC_C_ID = 14, | ||
| 583 | IMX_SC_C_PXL_CLK_POLARITY = 15, | ||
| 584 | IMX_SC_C_LINESTATE = 16, | ||
| 585 | IMX_SC_C_PCIE_G_RST = 17, | ||
| 586 | IMX_SC_C_PCIE_BUTTON_RST = 18, | ||
| 587 | IMX_SC_C_PCIE_PERST = 19, | ||
| 588 | IMX_SC_C_PHY_RESET = 20, | ||
| 589 | IMX_SC_C_PXL_LINK_RATE_CORRECTION = 21, | ||
| 590 | IMX_SC_C_PANIC = 22, | ||
| 591 | IMX_SC_C_PRIORITY_GROUP = 23, | ||
| 592 | IMX_SC_C_TXCLK = 24, | ||
| 593 | IMX_SC_C_CLKDIV = 25, | ||
| 594 | IMX_SC_C_DISABLE_50 = 26, | ||
| 595 | IMX_SC_C_DISABLE_125 = 27, | ||
| 596 | IMX_SC_C_SEL_125 = 28, | ||
| 597 | IMX_SC_C_MODE = 29, | ||
| 598 | IMX_SC_C_SYNC_CTRL0 = 30, | ||
| 599 | IMX_SC_C_KACHUNK_CNT = 31, | ||
| 600 | IMX_SC_C_KACHUNK_SEL = 32, | ||
| 601 | IMX_SC_C_SYNC_CTRL1 = 33, | ||
| 602 | IMX_SC_C_DPI_RESET = 34, | ||
| 603 | IMX_SC_C_MIPI_RESET = 35, | ||
| 604 | IMX_SC_C_DUAL_MODE = 36, | ||
| 605 | IMX_SC_C_VOLTAGE = 37, | ||
| 606 | IMX_SC_C_PXL_LINK_SEL = 38, | ||
| 607 | IMX_SC_C_OFS_SEL = 39, | ||
| 608 | IMX_SC_C_OFS_AUDIO = 40, | ||
| 609 | IMX_SC_C_OFS_PERIPH = 41, | ||
| 610 | IMX_SC_C_OFS_IRQ = 42, | ||
| 611 | IMX_SC_C_RST0 = 43, | ||
| 612 | IMX_SC_C_RST1 = 44, | ||
| 613 | IMX_SC_C_SEL0 = 45, | ||
| 614 | IMX_SC_C_LAST | ||
| 615 | }; | ||
| 616 | |||
| 617 | #endif /* _SC_TYPES_H */ | ||
