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-rw-r--r--include/asm-generic/pgtable.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index c370b261c720..9401f4819891 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -783,6 +783,23 @@ static inline int pmd_clear_huge(pmd_t *pmd)
783} 783}
784#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 784#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
785 785
786#ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
787#ifdef CONFIG_TRANSPARENT_HUGEPAGE
788/*
789 * ARCHes with special requirements for evicting THP backing TLB entries can
790 * implement this. Otherwise also, it can help optimize normal TLB flush in
791 * THP regime. stock flush_tlb_range() typically has optimization to nuke the
792 * entire TLB TLB if flush span is greater than a threshold, which will
793 * likely be true for a single huge page. Thus a single thp flush will
794 * invalidate the entire TLB which is not desitable.
795 * e.g. see arch/arc: flush_pmd_tlb_range
796 */
797#define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
798#else
799#define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG()
800#endif
801#endif
802
786#endif /* !__ASSEMBLY__ */ 803#endif /* !__ASSEMBLY__ */
787 804
788#ifndef io_remap_pfn_range 805#ifndef io_remap_pfn_range