litmus-rt-ext-res.git - LITMUS^RT with extended reservations for Forbidden Zones paper @ RTAS'20

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/* * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ #define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) #define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) #define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) #define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) /*MX53*/ #define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) #define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR) /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 #define MXC_PLL_DP_CONFIG 0x04 #define MXC_PLL_DP_OP 0x08 #define MXC_PLL_DP_MFD 0x0C #define MXC_PLL_DP_MFN 0x10 #define MXC_PLL_DP_MFNMINUS 0x14 #define MXC_PLL_DP_MFNPLUS 0x18 #define MXC_PLL_DP_HFS_OP 0x1C #define MXC_PLL_DP_HFS_MFD 0x20 #define MXC_PLL_DP_HFS_MFN 0x24 #define MXC_PLL_DP_MFN_TOGC 0x28 #define MXC_PLL_DP_DESTAT 0x2c /* PLL Register Bit definitions */ #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 #define MXC_PLL_DP_CTL_ADE 0x800 #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 #define MXC_PLL_DP_CTL_HFSM 0x80 #define MXC_PLL_DP_CTL_PRE 0x40 #define MXC_PLL_DP_CTL_UPEN 0x20 #define MXC_PLL_DP_CTL_RST 0x10 #define MXC_PLL_DP_CTL_RCP 0x8 #define MXC_PLL_DP_CTL_PLM 0x4 #define MXC_PLL_DP_CTL_BRM0 0x2 #define MXC_PLL_DP_CTL_LRF 0x1 #define MXC_PLL_DP_CONFIG_BIST 0x8 #define MXC_PLL_DP_CONFIG_SJC_CE 0x4 #define MXC_PLL_DP_CONFIG_AREN 0x2 #define MXC_PLL_DP_CONFIG_LDREQ 0x1 #define MXC_PLL_DP_OP_MFI_OFFSET 4 #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) #define MXC_PLL_DP_OP_PDF_OFFSET 0 #define MXC_PLL_DP_OP_PDF_MASK 0xF #define MXC_PLL_DP_MFD_OFFSET 0 #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF #define MXC_PLL_DP_MFN_OFFSET 0x0 #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF /* Register addresses of CCM*/ #define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) #define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) #define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) #define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) #define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) #define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) #define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) #define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) #define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) #define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) #define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) #define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) #define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) #define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) #define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) #define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) #define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) #define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) #define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) #define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) #define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) #define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) #define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) #define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) #define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) #define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) #define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) #define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) #define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) #define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) #define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) #define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) #define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) #define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) #define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (1 << 12) #define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) #define MXC_CCM_CCR_CAMP2_EN (1 << 10) #define MXC_CCM_CCR_CAMP1_EN (1 << 9) #define MXC_CCM_CCR_FPM_EN (1 << 8) #define MXC_CCM_CCR_OSCNT_OFFSET (0) #define MXC_CCM_CCR_OSCNT_MASK (0xFF) /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)


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