14 files changed, 86 insertions, 54 deletions

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index aba6e93b0502..80dc988f01e4 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -160,7 +160,7 @@ config PDC_ADMA
 
 config PATA_OCTEON_CF
         tristate "OCTEON Boot Bus Compact Flash support"
-        depends on CPU_CAVIUM_OCTEON
+        depends on CAVIUM_OCTEON_SOC
         help
           This option enables a polled compact flash driver for use with
           compact flash cards attached to the OCTEON boot bus.
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 2f9dbf7568fb..40a865449f35 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -167,7 +167,7 @@ config HW_RANDOM_OMAP
 
 config HW_RANDOM_OCTEON
         tristate "Octeon Random Number Generator support"
-        depends on HW_RANDOM && CPU_CAVIUM_OCTEON
+        depends on HW_RANDOM && CAVIUM_OCTEON_SOC
         default HW_RANDOM
         ---help---
           This driver provides kernel-side support for the Random Number
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index a697a64d5383..878f09005fad 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -349,21 +349,21 @@ config EDAC_OCTEON_PC
 
 config EDAC_OCTEON_L2C
         tristate "Cavium Octeon Secondary Caches (L2C)"
-        depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
+        depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
         help
           Support for error detection and correction on the
           Cavium Octeon family of SOCs.
 
 config EDAC_OCTEON_LMC
         tristate "Cavium Octeon DRAM Memory Controller (LMC)"
-        depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
+        depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
         help
           Support for error detection and correction on the
           Cavium Octeon family of SOCs.
 
 config EDAC_OCTEON_PCI
         tristate "Cavium Octeon PCI Controller"
-        depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
+        depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
         help
           Support for error detection and correction on the
           Cavium Octeon family of SOCs.
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index fdc2ab4af315..dc6dea614abd 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -739,7 +739,7 @@ config I2C_WMT
 
 config I2C_OCTEON
         tristate "Cavium OCTEON I2C bus support"
-        depends on CPU_CAVIUM_OCTEON
+        depends on CAVIUM_OCTEON_SOC
         help
           Say yes if you want to support the I2C serial bus on Cavium
           OCTEON SOC.
diff --git a/drivers/net/ethernet/octeon/Kconfig b/drivers/net/ethernet/octeon/Kconfig
index 3de52ffd2872..a7aa28054cc1 100644
--- a/drivers/net/ethernet/octeon/Kconfig
+++ b/drivers/net/ethernet/octeon/Kconfig
@@ -4,7 +4,7 @@
 
 config OCTEON_MGMT_ETHERNET
         tristate "Octeon Management port ethernet driver (CN5XXX, CN6XXX)"
-        depends on  CPU_CAVIUM_OCTEON
+        depends on CAVIUM_OCTEON_SOC
         select PHYLIB
         select MDIO_OCTEON
         default y
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 3a316b30089f..342561ad3158 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -135,7 +135,7 @@ config MDIO_GPIO
 
 config MDIO_OCTEON
         tristate "Support for MDIO buses on Octeon SOCs"
-        depends on  CPU_CAVIUM_OCTEON
+        depends on CAVIUM_OCTEON_SOC
         default y
         help
 
diff --git a/drivers/rapidio/switches/idt_gen2.c b/drivers/rapidio/switches/idt_gen2.c
index 00a71ebb5cac..9f7fe21580bb 100644
--- a/drivers/rapidio/switches/idt_gen2.c
+++ b/drivers/rapidio/switches/idt_gen2.c
@@ -16,6 +16,8 @@
 #include <linux/rio_drv.h>
 #include <linux/rio_ids.h>
 #include <linux/delay.h>
+
+#include <asm/page.h>
 #include "../rio.h"
 
 #define LOCAL_RTE_CONF_DESTID_SEL       0x010070
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 10f99f45a29b..89cbbabaff44 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -266,7 +266,7 @@ config SPI_OC_TINY
 
 config SPI_OCTEON
         tristate "Cavium OCTEON SPI controller"
-        depends on CPU_CAVIUM_OCTEON
+        depends on CAVIUM_OCTEON_SOC
         help
           SPI host driver for the hardware found on some Cavium OCTEON
           SOCs.
diff --git a/drivers/ssb/Kconfig b/drivers/ssb/Kconfig
index 5ff3a4f19443..36171fd2826b 100644
--- a/drivers/ssb/Kconfig
+++ b/drivers/ssb/Kconfig
@@ -144,7 +144,7 @@ config SSB_SFLASH
 # Assumption: We are on embedded, if we compile the MIPS core.
 config SSB_EMBEDDED
         bool
-        depends on SSB_DRIVER_MIPS
+        depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
         default y
 
 config SSB_DRIVER_EXTIF
diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig
index 9493128e5fd2..6e1d5f8d3ec1 100644
--- a/drivers/staging/octeon/Kconfig
+++ b/drivers/staging/octeon/Kconfig
@@ -1,6 +1,6 @@
 config OCTEON_ETHERNET
         tristate "Cavium Networks Octeon Ethernet support"
-        depends on CPU_CAVIUM_OCTEON && NETDEVICES
+        depends on CAVIUM_OCTEON_SOC && NETDEVICES
         select PHYLIB
         select MDIO_OCTEON
         help
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index d07b6af3a937..76a8daadff47 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -29,6 +29,8 @@
 #include <linux/clk.h>
 #include <linux/pm_runtime.h>
 
+#include <asm/byteorder.h>
+
 #include "8250.h"
 
 /* Offsets for the DesignWare specific registers */
@@ -57,6 +59,7 @@ struct dw8250_data {
         int             last_lcr;
         int             line;
         struct clk      *clk;
+        u8              usr_reg;
 };
 
 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
@@ -77,6 +80,13 @@ static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
         return readb(p->membase + offset);
 }
 
+/* Read Back (rb) version to ensure register access ording. */
+static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
+{
+        dw8250_serial_out(p, offset, value);
+        dw8250_serial_in(p, UART_LCR);
+}
+
 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 {
         struct dw8250_data *d = p->private_data;
@@ -104,7 +114,7 @@ static int dw8250_handle_irq(struct uart_port *p)
                 return 1;
         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
                 /* Clear the USR and write the LCR again. */
-                (void)p->serial_in(p, DW_UART_USR);
+                (void)p->serial_in(p, d->usr_reg);
                 p->serial_out(p, UART_LCR, d->last_lcr);
 
                 return 1;
@@ -125,12 +135,60 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
                 pm_runtime_put_sync_suspend(port->dev);
 }
 
-static int dw8250_probe_of(struct uart_port *p)
+static void dw8250_setup_port(struct uart_8250_port *up)
+{
+        struct uart_port        *p = &up->port;
+        u32                     reg = readl(p->membase + DW_UART_UCV);
+
+        /*
+         * If the Component Version Register returns zero, we know that
+         * ADDITIONAL_FEATURES are not enabled. No need to go any further.
+         */
+        if (!reg)
+                return;
+
+        dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
+                (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
+
+        reg = readl(p->membase + DW_UART_CPR);
+        if (!reg)
+                return;
+
+        /* Select the type based on fifo */
+        if (reg & DW_UART_CPR_FIFO_MODE) {
+                p->type = PORT_16550A;
+                p->flags |= UPF_FIXED_TYPE;
+                p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
+                up->tx_loadsz = p->fifosize;
+                up->capabilities = UART_CAP_FIFO;
+        }
+
+        if (reg & DW_UART_CPR_AFCE_MODE)
+                up->capabilities |= UART_CAP_AFE;
+}
+
+static int dw8250_probe_of(struct uart_port *p,
+                           struct dw8250_data *data)
 {
         struct device_node      *np = p->dev->of_node;
         u32                     val;
-
-        if (!of_property_read_u32(np, "reg-io-width", &val)) {
+        bool has_ucv = true;
+
+        if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
+#ifdef __BIG_ENDIAN
+                /*
+                 * Low order bits of these 64-bit registers, when
+                 * accessed as a byte, are 7 bytes further down in the
+                 * address space in big endian mode.
+                 */
+                p->membase += 7;
+#endif
+                p->serial_out = dw8250_serial_out_rb;
+                p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
+                p->type = PORT_OCTEON;
+                data->usr_reg = 0x27;
+                has_ucv = false;
+        } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
                 switch (val) {
                 case 1:
                         break;
@@ -144,6 +202,8 @@ static int dw8250_probe_of(struct uart_port *p)
                         return -EINVAL;
                 }
         }
+        if (has_ucv)
+                dw8250_setup_port(container_of(p, struct uart_8250_port, port));
 
         if (!of_property_read_u32(np, "reg-shift", &val))
                 p->regshift = val;
@@ -168,6 +228,8 @@ static int dw8250_probe_acpi(struct uart_8250_port *up)
         const struct acpi_device_id *id;
         struct uart_port *p = &up->port;
 
+        dw8250_setup_port(up);
+
         id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
         if (!id)
                 return -ENODEV;
@@ -196,38 +258,6 @@ static inline int dw8250_probe_acpi(struct uart_8250_port *up)
 }
 #endif /* CONFIG_ACPI */
 
-static void dw8250_setup_port(struct uart_8250_port *up)
-{
-        struct uart_port        *p = &up->port;
-        u32                     reg = readl(p->membase + DW_UART_UCV);
-
-        /*
-         * If the Component Version Register returns zero, we know that
-         * ADDITIONAL_FEATURES are not enabled. No need to go any further.
-         */
-        if (!reg)
-                return;
-
-        dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
-                (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
-
-        reg = readl(p->membase + DW_UART_CPR);
-        if (!reg)
-                return;
-
-        /* Select the type based on fifo */
-        if (reg & DW_UART_CPR_FIFO_MODE) {
-                p->type = PORT_16550A;
-                p->flags |= UPF_FIXED_TYPE;
-                p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
-                up->tx_loadsz = p->fifosize;
-                up->capabilities = UART_CAP_FIFO;
-        }
-
-        if (reg & DW_UART_CPR_AFCE_MODE)
-                up->capabilities |= UART_CAP_AFE;
-}
-
 static int dw8250_probe(struct platform_device *pdev)
 {
         struct uart_8250_port uart = {};
@@ -259,6 +289,7 @@ static int dw8250_probe(struct platform_device *pdev)
         if (!data)
                 return -ENOMEM;
 
+        data->usr_reg = DW_UART_USR;
         data->clk = devm_clk_get(&pdev->dev, NULL);
         if (!IS_ERR(data->clk)) {
                 clk_prepare_enable(data->clk);
@@ -270,10 +301,8 @@ static int dw8250_probe(struct platform_device *pdev)
         uart.port.serial_out = dw8250_serial_out;
         uart.port.private_data = data;
 
-        dw8250_setup_port(&uart);
-
         if (pdev->dev.of_node) {
-                err = dw8250_probe_of(&uart.port);
+                err = dw8250_probe_of(&uart.port, data);
                 if (err)
                         return err;
         } else if (ACPI_HANDLE(&pdev->dev)) {
@@ -362,6 +391,7 @@ static const struct dev_pm_ops dw8250_pm_ops = {
 
 static const struct of_device_id dw8250_of_match[] = {
         { .compatible = "snps,dw-apb-uart" },
+        { .compatible = "cavium,octeon-3860-uart" },
         { /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, dw8250_of_match);
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 2817013bceb1..4263d011392c 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -283,7 +283,7 @@ config USB_EHCI_HCD_PLATFORM
 
 config USB_OCTEON_EHCI
         bool "Octeon on-chip EHCI support"
-        depends on CPU_CAVIUM_OCTEON
+        depends on CAVIUM_OCTEON_SOC
         default n
         select USB_EHCI_BIG_ENDIAN_MMIO
         help
@@ -488,7 +488,7 @@ config USB_OHCI_HCD_PLATFORM
 
 config USB_OCTEON_OHCI
         bool "Octeon on-chip OHCI support"
-        depends on CPU_CAVIUM_OCTEON
+        depends on CAVIUM_OCTEON_SOC
         default USB_OCTEON_EHCI
         select USB_OHCI_BIG_ENDIAN_MMIO
         select USB_OHCI_LITTLE_ENDIAN
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 8519bc696a6f..362085d7ad8f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1074,7 +1074,7 @@ config TXX9_WDT
 
 config OCTEON_WDT
         tristate "Cavium OCTEON SOC family Watchdog Timer"
-        depends on CPU_CAVIUM_OCTEON
+        depends on CAVIUM_OCTEON_SOC
         default y
         select EXPORT_UASM if OCTEON_WDT = m
         help
diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c
index 25c7a3f9652d..ea5d84a1fdad 100644
--- a/drivers/watchdog/sb_wdog.c
+++ b/drivers/watchdog/sb_wdog.c
@@ -208,7 +208,7 @@ static long sbwdog_ioctl(struct file *file, unsigned int cmd,
                  * get the remaining count from the ... count register
                  * which is 1*8 before the config register
                  */
-                ret = put_user(__raw_readq(user_dog - 8) / 1000000, p);
+                ret = put_user((u32)__raw_readq(user_dog - 8) / 1000000, p);
                 break;
         }
         return ret;