diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ethernet/broadcom/tg3.c | 21 | ||||
| -rw-r--r-- | drivers/net/ethernet/broadcom/tg3.h | 5 |
2 files changed, 18 insertions, 8 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 1f2dd928888a..0f493c8dc28b 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c | |||
| @@ -9468,6 +9468,14 @@ static void tg3_rss_write_indir_tbl(struct tg3 *tp) | |||
| 9468 | } | 9468 | } |
| 9469 | } | 9469 | } |
| 9470 | 9470 | ||
| 9471 | static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp) | ||
| 9472 | { | ||
| 9473 | if (tg3_asic_rev(tp) == ASIC_REV_5719) | ||
| 9474 | return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719; | ||
| 9475 | else | ||
| 9476 | return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720; | ||
| 9477 | } | ||
| 9478 | |||
| 9471 | /* tp->lock is held. */ | 9479 | /* tp->lock is held. */ |
| 9472 | static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) | 9480 | static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) |
| 9473 | { | 9481 | { |
| @@ -10153,16 +10161,17 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) | |||
| 10153 | tw32_f(RDMAC_MODE, rdmac_mode); | 10161 | tw32_f(RDMAC_MODE, rdmac_mode); |
| 10154 | udelay(40); | 10162 | udelay(40); |
| 10155 | 10163 | ||
| 10156 | if (tg3_asic_rev(tp) == ASIC_REV_5719) { | 10164 | if (tg3_asic_rev(tp) == ASIC_REV_5719 || |
| 10165 | tg3_asic_rev(tp) == ASIC_REV_5720) { | ||
| 10157 | for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) { | 10166 | for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) { |
| 10158 | if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) | 10167 | if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) |
| 10159 | break; | 10168 | break; |
| 10160 | } | 10169 | } |
| 10161 | if (i < TG3_NUM_RDMA_CHANNELS) { | 10170 | if (i < TG3_NUM_RDMA_CHANNELS) { |
| 10162 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); | 10171 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
| 10163 | val |= TG3_LSO_RD_DMA_TX_LENGTH_WA; | 10172 | val |= tg3_lso_rd_dma_workaround_bit(tp); |
| 10164 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); | 10173 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); |
| 10165 | tg3_flag_set(tp, 5719_RDMA_BUG); | 10174 | tg3_flag_set(tp, 5719_5720_RDMA_BUG); |
| 10166 | } | 10175 | } |
| 10167 | } | 10176 | } |
| 10168 | 10177 | ||
| @@ -10526,15 +10535,15 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp) | |||
| 10526 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | 10535 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); |
| 10527 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | 10536 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); |
| 10528 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | 10537 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); |
| 10529 | if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) && | 10538 | if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) && |
| 10530 | (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + | 10539 | (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + |
| 10531 | sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { | 10540 | sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { |
| 10532 | u32 val; | 10541 | u32 val; |
| 10533 | 10542 | ||
| 10534 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); | 10543 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
| 10535 | val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA; | 10544 | val &= ~tg3_lso_rd_dma_workaround_bit(tp); |
| 10536 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); | 10545 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val); |
| 10537 | tg3_flag_clear(tp, 5719_RDMA_BUG); | 10546 | tg3_flag_clear(tp, 5719_5720_RDMA_BUG); |
| 10538 | } | 10547 | } |
| 10539 | 10548 | ||
| 10540 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | 10549 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); |
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index 9b2d3ac2474a..ff6e30eeae35 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h | |||
| @@ -1422,7 +1422,8 @@ | |||
| 1422 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910 | 1422 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910 |
| 1423 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 | 1423 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 |
| 1424 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000 | 1424 | #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000 |
| 1425 | #define TG3_LSO_RD_DMA_TX_LENGTH_WA 0x02000000 | 1425 | #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719 0x02000000 |
| 1426 | #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720 0x00200000 | ||
| 1426 | /* 0x4914 --> 0x4be0 unused */ | 1427 | /* 0x4914 --> 0x4be0 unused */ |
| 1427 | 1428 | ||
| 1428 | #define TG3_NUM_RDMA_CHANNELS 4 | 1429 | #define TG3_NUM_RDMA_CHANNELS 4 |
| @@ -3059,7 +3060,7 @@ enum TG3_FLAGS { | |||
| 3059 | TG3_FLAG_APE_HAS_NCSI, | 3060 | TG3_FLAG_APE_HAS_NCSI, |
| 3060 | TG3_FLAG_TX_TSTAMP_EN, | 3061 | TG3_FLAG_TX_TSTAMP_EN, |
| 3061 | TG3_FLAG_4K_FIFO_LIMIT, | 3062 | TG3_FLAG_4K_FIFO_LIMIT, |
| 3062 | TG3_FLAG_5719_RDMA_BUG, | 3063 | TG3_FLAG_5719_5720_RDMA_BUG, |
| 3063 | TG3_FLAG_RESET_TASK_PENDING, | 3064 | TG3_FLAG_RESET_TASK_PENDING, |
| 3064 | TG3_FLAG_PTP_CAPABLE, | 3065 | TG3_FLAG_PTP_CAPABLE, |
| 3065 | TG3_FLAG_5705_PLUS, | 3066 | TG3_FLAG_5705_PLUS, |
