diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 76e278d679ba..db81e454166b 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c | |||
| @@ -247,10 +247,9 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, | |||
| 247 | { | 247 | { |
| 248 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); | 248 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); |
| 249 | const struct rockchip_pll_rate_table *rate; | 249 | const struct rockchip_pll_rate_table *rate; |
| 250 | unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate); | ||
| 251 | 250 | ||
| 252 | pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", | 251 | pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", |
| 253 | __func__, __clk_get_name(hw->clk), old_rate, drate, prate); | 252 | __func__, __clk_get_name(hw->clk), drate, prate); |
| 254 | 253 | ||
| 255 | /* Get required rate settings from table */ | 254 | /* Get required rate settings from table */ |
| 256 | rate = rockchip_get_pll_settings(pll, drate); | 255 | rate = rockchip_get_pll_settings(pll, drate); |
| @@ -479,10 +478,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, | |||
| 479 | { | 478 | { |
| 480 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); | 479 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); |
| 481 | const struct rockchip_pll_rate_table *rate; | 480 | const struct rockchip_pll_rate_table *rate; |
| 482 | unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); | ||
| 483 | 481 | ||
| 484 | pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", | 482 | pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", |
| 485 | __func__, clk_hw_get_name(hw), old_rate, drate, prate); | 483 | __func__, clk_hw_get_name(hw), drate, prate); |
| 486 | 484 | ||
| 487 | /* Get required rate settings from table */ | 485 | /* Get required rate settings from table */ |
| 488 | rate = rockchip_get_pll_settings(pll, drate); | 486 | rate = rockchip_get_pll_settings(pll, drate); |
| @@ -725,10 +723,9 @@ static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, | |||
| 725 | { | 723 | { |
| 726 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); | 724 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); |
| 727 | const struct rockchip_pll_rate_table *rate; | 725 | const struct rockchip_pll_rate_table *rate; |
| 728 | unsigned long old_rate = rockchip_rk3399_pll_recalc_rate(hw, prate); | ||
| 729 | 726 | ||
| 730 | pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", | 727 | pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", |
| 731 | __func__, __clk_get_name(hw->clk), old_rate, drate, prate); | 728 | __func__, __clk_get_name(hw->clk), drate, prate); |
| 732 | 729 | ||
| 733 | /* Get required rate settings from table */ | 730 | /* Get required rate settings from table */ |
| 734 | rate = rockchip_get_pll_settings(pll, drate); | 731 | rate = rockchip_get_pll_settings(pll, drate); |
