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-rw-r--r--drivers/gpu/drm/i915/i915_irq.c19
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
2 files changed, 19 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e1bfc85d1789..9304ce3e4649 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1778,6 +1778,21 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
1778 } 1778 }
1779 } 1779 }
1780 1780
1781 if (master_ctl & GEN8_DE_PORT_IRQ) {
1782 tmp = I915_READ(GEN8_DE_PORT_IIR);
1783 if (tmp & GEN8_AUX_CHANNEL_A)
1784 dp_aux_irq_handler(dev);
1785 else if (tmp)
1786 DRM_ERROR("Unexpected DE Port interrupt\n");
1787 else
1788 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1789
1790 if (tmp) {
1791 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1792 ret = IRQ_HANDLED;
1793 }
1794 }
1795
1781 for_each_pipe(pipe) { 1796 for_each_pipe(pipe) {
1782 uint32_t pipe_iir; 1797 uint32_t pipe_iir;
1783 1798
@@ -2883,8 +2898,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2883 } 2898 }
2884 POSTING_READ(GEN8_DE_PIPE_ISR(0)); 2899 POSTING_READ(GEN8_DE_PIPE_ISR(0));
2885 2900
2886 I915_WRITE(GEN8_DE_PORT_IMR, ~_PORT_DP_A_HOTPLUG); 2901 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
2887 I915_WRITE(GEN8_DE_PORT_IER, _PORT_DP_A_HOTPLUG); 2902 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
2888 POSTING_READ(GEN8_DE_PORT_IER); 2903 POSTING_READ(GEN8_DE_PORT_IER);
2889} 2904}
2890 2905
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9e7588345017..fe8cb4cc0296 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4073,7 +4073,8 @@
4073#define GEN8_DE_PORT_IMR 0x44444 4073#define GEN8_DE_PORT_IMR 0x44444
4074#define GEN8_DE_PORT_IIR 0x44448 4074#define GEN8_DE_PORT_IIR 0x44448
4075#define GEN8_DE_PORT_IER 0x4444c 4075#define GEN8_DE_PORT_IER 0x4444c
4076#define _PORT_DP_A_HOTPLUG (1 << 3) 4076#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
4077#define GEN8_AUX_CHANNEL_A (1 << 0)
4077 4078
4078#define GEN8_DE_MISC_ISR 0x44460 4079#define GEN8_DE_MISC_ISR 0x44460
4079#define GEN8_DE_MISC_IMR 0x44464 4080#define GEN8_DE_MISC_IMR 0x44464