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-rw-r--r--drivers/ntb/hw/intel/ntb_hw_intel.c620
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_intel.h290
2 files changed, 455 insertions, 455 deletions
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c
index 236b7d33b5af..eeaa1e8f8bd8 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.c
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.c
@@ -72,20 +72,20 @@ MODULE_AUTHOR("Intel Corporation");
72#define bar0_off(base, bar) ((base) + ((bar) << 2)) 72#define bar0_off(base, bar) ((base) + ((bar) << 2))
73#define bar2_off(base, bar) bar0_off(base, (bar) - 2) 73#define bar2_off(base, bar) bar0_off(base, (bar) - 2)
74 74
75static const struct intel_ntb_reg bwd_reg; 75static const struct intel_ntb_reg atom_reg;
76static const struct intel_ntb_alt_reg bwd_pri_reg; 76static const struct intel_ntb_alt_reg atom_pri_reg;
77static const struct intel_ntb_alt_reg bwd_sec_reg; 77static const struct intel_ntb_alt_reg atom_sec_reg;
78static const struct intel_ntb_alt_reg bwd_b2b_reg; 78static const struct intel_ntb_alt_reg atom_b2b_reg;
79static const struct intel_ntb_xlat_reg bwd_pri_xlat; 79static const struct intel_ntb_xlat_reg atom_pri_xlat;
80static const struct intel_ntb_xlat_reg bwd_sec_xlat; 80static const struct intel_ntb_xlat_reg atom_sec_xlat;
81static const struct intel_ntb_reg snb_reg; 81static const struct intel_ntb_reg xeon_reg;
82static const struct intel_ntb_alt_reg snb_pri_reg; 82static const struct intel_ntb_alt_reg xeon_pri_reg;
83static const struct intel_ntb_alt_reg snb_sec_reg; 83static const struct intel_ntb_alt_reg xeon_sec_reg;
84static const struct intel_ntb_alt_reg snb_b2b_reg; 84static const struct intel_ntb_alt_reg xeon_b2b_reg;
85static const struct intel_ntb_xlat_reg snb_pri_xlat; 85static const struct intel_ntb_xlat_reg xeon_pri_xlat;
86static const struct intel_ntb_xlat_reg snb_sec_xlat; 86static const struct intel_ntb_xlat_reg xeon_sec_xlat;
87static struct intel_b2b_addr snb_b2b_usd_addr; 87static struct intel_b2b_addr xeon_b2b_usd_addr;
88static struct intel_b2b_addr snb_b2b_dsd_addr; 88static struct intel_b2b_addr xeon_b2b_dsd_addr;
89static const struct ntb_dev_ops intel_ntb_ops; 89static const struct ntb_dev_ops intel_ntb_ops;
90 90
91static const struct file_operations intel_ntb_debugfs_info; 91static const struct file_operations intel_ntb_debugfs_info;
@@ -105,45 +105,45 @@ MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the "
105 "the mw, so the second half can still be used as a mw. Both " 105 "the mw, so the second half can still be used as a mw. Both "
106 "sides MUST set the same value here!"); 106 "sides MUST set the same value here!");
107 107
108module_param_named(snb_b2b_usd_bar2_addr64, 108module_param_named(xeon_b2b_usd_bar2_addr64,
109 snb_b2b_usd_addr.bar2_addr64, ullong, 0644); 109 xeon_b2b_usd_addr.bar2_addr64, ullong, 0644);
110MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, 110MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64,
111 "SNB B2B USD BAR 2 64-bit address"); 111 "XEON B2B USD BAR 2 64-bit address");
112 112
113module_param_named(snb_b2b_usd_bar4_addr64, 113module_param_named(xeon_b2b_usd_bar4_addr64,
114 snb_b2b_usd_addr.bar4_addr64, ullong, 0644); 114 xeon_b2b_usd_addr.bar4_addr64, ullong, 0644);
115MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, 115MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64,
116 "SNB B2B USD BAR 4 64-bit address"); 116 "XEON B2B USD BAR 4 64-bit address");
117 117
118module_param_named(snb_b2b_usd_bar4_addr32, 118module_param_named(xeon_b2b_usd_bar4_addr32,
119 snb_b2b_usd_addr.bar4_addr32, ullong, 0644); 119 xeon_b2b_usd_addr.bar4_addr32, ullong, 0644);
120MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, 120MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64,
121 "SNB B2B USD split-BAR 4 32-bit address"); 121 "XEON B2B USD split-BAR 4 32-bit address");
122 122
123module_param_named(snb_b2b_usd_bar5_addr32, 123module_param_named(xeon_b2b_usd_bar5_addr32,
124 snb_b2b_usd_addr.bar5_addr32, ullong, 0644); 124 xeon_b2b_usd_addr.bar5_addr32, ullong, 0644);
125MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, 125MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64,
126 "SNB B2B USD split-BAR 5 32-bit address"); 126 "XEON B2B USD split-BAR 5 32-bit address");
127 127
128module_param_named(snb_b2b_dsd_bar2_addr64, 128module_param_named(xeon_b2b_dsd_bar2_addr64,
129 snb_b2b_dsd_addr.bar2_addr64, ullong, 0644); 129 xeon_b2b_dsd_addr.bar2_addr64, ullong, 0644);
130MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, 130MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64,
131 "SNB B2B DSD BAR 2 64-bit address"); 131 "XEON B2B DSD BAR 2 64-bit address");
132 132
133module_param_named(snb_b2b_dsd_bar4_addr64, 133module_param_named(xeon_b2b_dsd_bar4_addr64,
134 snb_b2b_dsd_addr.bar4_addr64, ullong, 0644); 134 xeon_b2b_dsd_addr.bar4_addr64, ullong, 0644);
135MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, 135MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64,
136 "SNB B2B DSD BAR 4 64-bit address"); 136 "XEON B2B DSD BAR 4 64-bit address");
137 137
138module_param_named(snb_b2b_dsd_bar4_addr32, 138module_param_named(xeon_b2b_dsd_bar4_addr32,
139 snb_b2b_dsd_addr.bar4_addr32, ullong, 0644); 139 xeon_b2b_dsd_addr.bar4_addr32, ullong, 0644);
140MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, 140MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64,
141 "SNB B2B DSD split-BAR 4 32-bit address"); 141 "XEON B2B DSD split-BAR 4 32-bit address");
142 142
143module_param_named(snb_b2b_dsd_bar5_addr32, 143module_param_named(xeon_b2b_dsd_bar5_addr32,
144 snb_b2b_dsd_addr.bar5_addr32, ullong, 0644); 144 xeon_b2b_dsd_addr.bar5_addr32, ullong, 0644);
145MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, 145MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64,
146 "SNB B2B DSD split-BAR 5 32-bit address"); 146 "XEON B2B DSD split-BAR 5 32-bit address");
147 147
148#ifndef ioread64 148#ifndef ioread64
149#ifdef readq 149#ifdef readq
@@ -174,7 +174,7 @@ static inline void _iowrite64(u64 val, void __iomem *mmio)
174#endif 174#endif
175#endif 175#endif
176 176
177static inline int pdev_is_bwd(struct pci_dev *pdev) 177static inline int pdev_is_atom(struct pci_dev *pdev)
178{ 178{
179 switch (pdev->device) { 179 switch (pdev->device) {
180 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD: 180 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
@@ -183,7 +183,7 @@ static inline int pdev_is_bwd(struct pci_dev *pdev)
183 return 0; 183 return 0;
184} 184}
185 185
186static inline int pdev_is_snb(struct pci_dev *pdev) 186static inline int pdev_is_xeon(struct pci_dev *pdev)
187{ 187{
188 switch (pdev->device) { 188 switch (pdev->device) {
189 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: 189 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
@@ -636,70 +636,70 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf,
636 off += scnprintf(buf + off, buf_size - off, 636 off += scnprintf(buf + off, buf_size - off,
637 "LMT45 -\t\t\t%#018llx\n", u.v64); 637 "LMT45 -\t\t\t%#018llx\n", u.v64);
638 638
639 if (pdev_is_snb(ndev->ntb.pdev)) { 639 if (pdev_is_xeon(ndev->ntb.pdev)) {
640 if (ntb_topo_is_b2b(ndev->ntb.topo)) { 640 if (ntb_topo_is_b2b(ndev->ntb.topo)) {
641 off += scnprintf(buf + off, buf_size - off, 641 off += scnprintf(buf + off, buf_size - off,
642 "\nNTB Outgoing B2B XLAT:\n"); 642 "\nNTB Outgoing B2B XLAT:\n");
643 643
644 u.v64 = ioread64(mmio + SNB_PBAR23XLAT_OFFSET); 644 u.v64 = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
645 off += scnprintf(buf + off, buf_size - off, 645 off += scnprintf(buf + off, buf_size - off,
646 "B2B XLAT23 -\t\t%#018llx\n", u.v64); 646 "B2B XLAT23 -\t\t%#018llx\n", u.v64);
647 647
648 u.v64 = ioread64(mmio + SNB_PBAR45XLAT_OFFSET); 648 u.v64 = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
649 off += scnprintf(buf + off, buf_size - off, 649 off += scnprintf(buf + off, buf_size - off,
650 "B2B XLAT45 -\t\t%#018llx\n", u.v64); 650 "B2B XLAT45 -\t\t%#018llx\n", u.v64);
651 651
652 u.v64 = ioread64(mmio + SNB_PBAR23LMT_OFFSET); 652 u.v64 = ioread64(mmio + XEON_PBAR23LMT_OFFSET);
653 off += scnprintf(buf + off, buf_size - off, 653 off += scnprintf(buf + off, buf_size - off,
654 "B2B LMT23 -\t\t%#018llx\n", u.v64); 654 "B2B LMT23 -\t\t%#018llx\n", u.v64);
655 655
656 u.v64 = ioread64(mmio + SNB_PBAR45LMT_OFFSET); 656 u.v64 = ioread64(mmio + XEON_PBAR45LMT_OFFSET);
657 off += scnprintf(buf + off, buf_size - off, 657 off += scnprintf(buf + off, buf_size - off,
658 "B2B LMT45 -\t\t%#018llx\n", u.v64); 658 "B2B LMT45 -\t\t%#018llx\n", u.v64);
659 659
660 off += scnprintf(buf + off, buf_size - off, 660 off += scnprintf(buf + off, buf_size - off,
661 "\nNTB Secondary BAR:\n"); 661 "\nNTB Secondary BAR:\n");
662 662
663 u.v64 = ioread64(mmio + SNB_SBAR0BASE_OFFSET); 663 u.v64 = ioread64(mmio + XEON_SBAR0BASE_OFFSET);
664 off += scnprintf(buf + off, buf_size - off, 664 off += scnprintf(buf + off, buf_size - off,
665 "SBAR01 -\t\t%#018llx\n", u.v64); 665 "SBAR01 -\t\t%#018llx\n", u.v64);
666 666
667 u.v64 = ioread64(mmio + SNB_SBAR23BASE_OFFSET); 667 u.v64 = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
668 off += scnprintf(buf + off, buf_size - off, 668 off += scnprintf(buf + off, buf_size - off,
669 "SBAR23 -\t\t%#018llx\n", u.v64); 669 "SBAR23 -\t\t%#018llx\n", u.v64);
670 670
671 u.v64 = ioread64(mmio + SNB_SBAR45BASE_OFFSET); 671 u.v64 = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
672 off += scnprintf(buf + off, buf_size - off, 672 off += scnprintf(buf + off, buf_size - off,
673 "SBAR45 -\t\t%#018llx\n", u.v64); 673 "SBAR45 -\t\t%#018llx\n", u.v64);
674 } 674 }
675 675
676 off += scnprintf(buf + off, buf_size - off, 676 off += scnprintf(buf + off, buf_size - off,
677 "\nSNB NTB Statistics:\n"); 677 "\nXEON NTB Statistics:\n");
678 678
679 u.v16 = ioread16(mmio + SNB_USMEMMISS_OFFSET); 679 u.v16 = ioread16(mmio + XEON_USMEMMISS_OFFSET);
680 off += scnprintf(buf + off, buf_size - off, 680 off += scnprintf(buf + off, buf_size - off,
681 "Upstream Memory Miss -\t%u\n", u.v16); 681 "Upstream Memory Miss -\t%u\n", u.v16);
682 682
683 off += scnprintf(buf + off, buf_size - off, 683 off += scnprintf(buf + off, buf_size - off,
684 "\nSNB NTB Hardware Errors:\n"); 684 "\nXEON NTB Hardware Errors:\n");
685 685
686 if (!pci_read_config_word(ndev->ntb.pdev, 686 if (!pci_read_config_word(ndev->ntb.pdev,
687 SNB_DEVSTS_OFFSET, &u.v16)) 687 XEON_DEVSTS_OFFSET, &u.v16))
688 off += scnprintf(buf + off, buf_size - off, 688 off += scnprintf(buf + off, buf_size - off,
689 "DEVSTS -\t\t%#06x\n", u.v16); 689 "DEVSTS -\t\t%#06x\n", u.v16);
690 690
691 if (!pci_read_config_word(ndev->ntb.pdev, 691 if (!pci_read_config_word(ndev->ntb.pdev,
692 SNB_LINK_STATUS_OFFSET, &u.v16)) 692 XEON_LINK_STATUS_OFFSET, &u.v16))
693 off += scnprintf(buf + off, buf_size - off, 693 off += scnprintf(buf + off, buf_size - off,
694 "LNKSTS -\t\t%#06x\n", u.v16); 694 "LNKSTS -\t\t%#06x\n", u.v16);
695 695
696 if (!pci_read_config_dword(ndev->ntb.pdev, 696 if (!pci_read_config_dword(ndev->ntb.pdev,
697 SNB_UNCERRSTS_OFFSET, &u.v32)) 697 XEON_UNCERRSTS_OFFSET, &u.v32))
698 off += scnprintf(buf + off, buf_size - off, 698 off += scnprintf(buf + off, buf_size - off,
699 "UNCERRSTS -\t\t%#06x\n", u.v32); 699 "UNCERRSTS -\t\t%#06x\n", u.v32);
700 700
701 if (!pci_read_config_dword(ndev->ntb.pdev, 701 if (!pci_read_config_dword(ndev->ntb.pdev,
702 SNB_CORERRSTS_OFFSET, &u.v32)) 702 XEON_CORERRSTS_OFFSET, &u.v32))
703 off += scnprintf(buf + off, buf_size - off, 703 off += scnprintf(buf + off, buf_size - off,
704 "CORERRSTS -\t\t%#06x\n", u.v32); 704 "CORERRSTS -\t\t%#06x\n", u.v32);
705 } 705 }
@@ -1091,67 +1091,67 @@ static int intel_ntb_peer_spad_write(struct ntb_dev *ntb,
1091 ndev->peer_reg->spad); 1091 ndev->peer_reg->spad);
1092} 1092}
1093 1093
1094/* BWD */ 1094/* ATOM */
1095 1095
1096static u64 bwd_db_ioread(void __iomem *mmio) 1096static u64 atom_db_ioread(void __iomem *mmio)
1097{ 1097{
1098 return ioread64(mmio); 1098 return ioread64(mmio);
1099} 1099}
1100 1100
1101static void bwd_db_iowrite(u64 bits, void __iomem *mmio) 1101static void atom_db_iowrite(u64 bits, void __iomem *mmio)
1102{ 1102{
1103 iowrite64(bits, mmio); 1103 iowrite64(bits, mmio);
1104} 1104}
1105 1105
1106static int bwd_poll_link(struct intel_ntb_dev *ndev) 1106static int atom_poll_link(struct intel_ntb_dev *ndev)
1107{ 1107{
1108 u32 ntb_ctl; 1108 u32 ntb_ctl;
1109 1109
1110 ntb_ctl = ioread32(ndev->self_mmio + BWD_NTBCNTL_OFFSET); 1110 ntb_ctl = ioread32(ndev->self_mmio + ATOM_NTBCNTL_OFFSET);
1111 1111
1112 if (ntb_ctl == ndev->ntb_ctl) 1112 if (ntb_ctl == ndev->ntb_ctl)
1113 return 0; 1113 return 0;
1114 1114
1115 ndev->ntb_ctl = ntb_ctl; 1115 ndev->ntb_ctl = ntb_ctl;
1116 1116
1117 ndev->lnk_sta = ioread32(ndev->self_mmio + BWD_LINK_STATUS_OFFSET); 1117 ndev->lnk_sta = ioread32(ndev->self_mmio + ATOM_LINK_STATUS_OFFSET);
1118 1118
1119 return 1; 1119 return 1;
1120} 1120}
1121 1121
1122static int bwd_link_is_up(struct intel_ntb_dev *ndev) 1122static int atom_link_is_up(struct intel_ntb_dev *ndev)
1123{ 1123{
1124 return BWD_NTB_CTL_ACTIVE(ndev->ntb_ctl); 1124 return ATOM_NTB_CTL_ACTIVE(ndev->ntb_ctl);
1125} 1125}
1126 1126
1127static int bwd_link_is_err(struct intel_ntb_dev *ndev) 1127static int atom_link_is_err(struct intel_ntb_dev *ndev)
1128{ 1128{
1129 if (ioread32(ndev->self_mmio + BWD_LTSSMSTATEJMP_OFFSET) 1129 if (ioread32(ndev->self_mmio + ATOM_LTSSMSTATEJMP_OFFSET)
1130 & BWD_LTSSMSTATEJMP_FORCEDETECT) 1130 & ATOM_LTSSMSTATEJMP_FORCEDETECT)
1131 return 1; 1131 return 1;
1132 1132
1133 if (ioread32(ndev->self_mmio + BWD_IBSTERRRCRVSTS0_OFFSET) 1133 if (ioread32(ndev->self_mmio + ATOM_IBSTERRRCRVSTS0_OFFSET)
1134 & BWD_IBIST_ERR_OFLOW) 1134 & ATOM_IBIST_ERR_OFLOW)
1135 return 1; 1135 return 1;
1136 1136
1137 return 0; 1137 return 0;
1138} 1138}
1139 1139
1140static inline enum ntb_topo bwd_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd) 1140static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
1141{ 1141{
1142 switch (ppd & BWD_PPD_TOPO_MASK) { 1142 switch (ppd & ATOM_PPD_TOPO_MASK) {
1143 case BWD_PPD_TOPO_B2B_USD: 1143 case ATOM_PPD_TOPO_B2B_USD:
1144 dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd); 1144 dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd);
1145 return NTB_TOPO_B2B_USD; 1145 return NTB_TOPO_B2B_USD;
1146 1146
1147 case BWD_PPD_TOPO_B2B_DSD: 1147 case ATOM_PPD_TOPO_B2B_DSD:
1148 dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd); 1148 dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd);
1149 return NTB_TOPO_B2B_DSD; 1149 return NTB_TOPO_B2B_DSD;
1150 1150
1151 case BWD_PPD_TOPO_PRI_USD: 1151 case ATOM_PPD_TOPO_PRI_USD:
1152 case BWD_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ 1152 case ATOM_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */
1153 case BWD_PPD_TOPO_SEC_USD: 1153 case ATOM_PPD_TOPO_SEC_USD:
1154 case BWD_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ 1154 case ATOM_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */
1155 dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd); 1155 dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd);
1156 return NTB_TOPO_NONE; 1156 return NTB_TOPO_NONE;
1157 } 1157 }
@@ -1160,28 +1160,28 @@ static inline enum ntb_topo bwd_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
1160 return NTB_TOPO_NONE; 1160 return NTB_TOPO_NONE;
1161} 1161}
1162 1162
1163static void bwd_link_hb(struct work_struct *work) 1163static void atom_link_hb(struct work_struct *work)
1164{ 1164{
1165 struct intel_ntb_dev *ndev = hb_ndev(work); 1165 struct intel_ntb_dev *ndev = hb_ndev(work);
1166 unsigned long poll_ts; 1166 unsigned long poll_ts;
1167 void __iomem *mmio; 1167 void __iomem *mmio;
1168 u32 status32; 1168 u32 status32;
1169 1169
1170 poll_ts = ndev->last_ts + BWD_LINK_HB_TIMEOUT; 1170 poll_ts = ndev->last_ts + ATOM_LINK_HB_TIMEOUT;
1171 1171
1172 /* Delay polling the link status if an interrupt was received, 1172 /* Delay polling the link status if an interrupt was received,
1173 * unless the cached link status says the link is down. 1173 * unless the cached link status says the link is down.
1174 */ 1174 */
1175 if (time_after(poll_ts, jiffies) && bwd_link_is_up(ndev)) { 1175 if (time_after(poll_ts, jiffies) && atom_link_is_up(ndev)) {
1176 schedule_delayed_work(&ndev->hb_timer, poll_ts - jiffies); 1176 schedule_delayed_work(&ndev->hb_timer, poll_ts - jiffies);
1177 return; 1177 return;
1178 } 1178 }
1179 1179
1180 if (bwd_poll_link(ndev)) 1180 if (atom_poll_link(ndev))
1181 ntb_link_event(&ndev->ntb); 1181 ntb_link_event(&ndev->ntb);
1182 1182
1183 if (bwd_link_is_up(ndev) || !bwd_link_is_err(ndev)) { 1183 if (atom_link_is_up(ndev) || !atom_link_is_err(ndev)) {
1184 schedule_delayed_work(&ndev->hb_timer, BWD_LINK_HB_TIMEOUT); 1184 schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT);
1185 return; 1185 return;
1186 } 1186 }
1187 1187
@@ -1190,91 +1190,91 @@ static void bwd_link_hb(struct work_struct *work)
1190 mmio = ndev->self_mmio; 1190 mmio = ndev->self_mmio;
1191 1191
1192 /* Driver resets the NTB ModPhy lanes - magic! */ 1192 /* Driver resets the NTB ModPhy lanes - magic! */
1193 iowrite8(0xe0, mmio + BWD_MODPHY_PCSREG6); 1193 iowrite8(0xe0, mmio + ATOM_MODPHY_PCSREG6);
1194 iowrite8(0x40, mmio + BWD_MODPHY_PCSREG4); 1194 iowrite8(0x40, mmio + ATOM_MODPHY_PCSREG4);
1195 iowrite8(0x60, mmio + BWD_MODPHY_PCSREG4); 1195 iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG4);
1196 iowrite8(0x60, mmio + BWD_MODPHY_PCSREG6); 1196 iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG6);
1197 1197
1198 /* Driver waits 100ms to allow the NTB ModPhy to settle */ 1198 /* Driver waits 100ms to allow the NTB ModPhy to settle */
1199 msleep(100); 1199 msleep(100);
1200 1200
1201 /* Clear AER Errors, write to clear */ 1201 /* Clear AER Errors, write to clear */
1202 status32 = ioread32(mmio + BWD_ERRCORSTS_OFFSET); 1202 status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET);
1203 dev_dbg(ndev_dev(ndev), "ERRCORSTS = %x\n", status32); 1203 dev_dbg(ndev_dev(ndev), "ERRCORSTS = %x\n", status32);
1204 status32 &= PCI_ERR_COR_REP_ROLL; 1204 status32 &= PCI_ERR_COR_REP_ROLL;
1205 iowrite32(status32, mmio + BWD_ERRCORSTS_OFFSET); 1205 iowrite32(status32, mmio + ATOM_ERRCORSTS_OFFSET);
1206 1206
1207 /* Clear unexpected electrical idle event in LTSSM, write to clear */ 1207 /* Clear unexpected electrical idle event in LTSSM, write to clear */
1208 status32 = ioread32(mmio + BWD_LTSSMERRSTS0_OFFSET); 1208 status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET);
1209 dev_dbg(ndev_dev(ndev), "LTSSMERRSTS0 = %x\n", status32); 1209 dev_dbg(ndev_dev(ndev), "LTSSMERRSTS0 = %x\n", status32);
1210 status32 |= BWD_LTSSMERRSTS0_UNEXPECTEDEI; 1210 status32 |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
1211 iowrite32(status32, mmio + BWD_LTSSMERRSTS0_OFFSET); 1211 iowrite32(status32, mmio + ATOM_LTSSMERRSTS0_OFFSET);
1212 1212
1213 /* Clear DeSkew Buffer error, write to clear */ 1213 /* Clear DeSkew Buffer error, write to clear */
1214 status32 = ioread32(mmio + BWD_DESKEWSTS_OFFSET); 1214 status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET);
1215 dev_dbg(ndev_dev(ndev), "DESKEWSTS = %x\n", status32); 1215 dev_dbg(ndev_dev(ndev), "DESKEWSTS = %x\n", status32);
1216 status32 |= BWD_DESKEWSTS_DBERR; 1216 status32 |= ATOM_DESKEWSTS_DBERR;
1217 iowrite32(status32, mmio + BWD_DESKEWSTS_OFFSET); 1217 iowrite32(status32, mmio + ATOM_DESKEWSTS_OFFSET);
1218 1218
1219 status32 = ioread32(mmio + BWD_IBSTERRRCRVSTS0_OFFSET); 1219 status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
1220 dev_dbg(ndev_dev(ndev), "IBSTERRRCRVSTS0 = %x\n", status32); 1220 dev_dbg(ndev_dev(ndev), "IBSTERRRCRVSTS0 = %x\n", status32);
1221 status32 &= BWD_IBIST_ERR_OFLOW; 1221 status32 &= ATOM_IBIST_ERR_OFLOW;
1222 iowrite32(status32, mmio + BWD_IBSTERRRCRVSTS0_OFFSET); 1222 iowrite32(status32, mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
1223 1223
1224 /* Releases the NTB state machine to allow the link to retrain */ 1224 /* Releases the NTB state machine to allow the link to retrain */
1225 status32 = ioread32(mmio + BWD_LTSSMSTATEJMP_OFFSET); 1225 status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET);
1226 dev_dbg(ndev_dev(ndev), "LTSSMSTATEJMP = %x\n", status32); 1226 dev_dbg(ndev_dev(ndev), "LTSSMSTATEJMP = %x\n", status32);
1227 status32 &= ~BWD_LTSSMSTATEJMP_FORCEDETECT; 1227 status32 &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
1228 iowrite32(status32, mmio + BWD_LTSSMSTATEJMP_OFFSET); 1228 iowrite32(status32, mmio + ATOM_LTSSMSTATEJMP_OFFSET);
1229 1229
1230 /* There is a potential race between the 2 NTB devices recovering at the 1230 /* There is a potential race between the 2 NTB devices recovering at the
1231 * same time. If the times are the same, the link will not recover and 1231 * same time. If the times are the same, the link will not recover and
1232 * the driver will be stuck in this loop forever. Add a random interval 1232 * the driver will be stuck in this loop forever. Add a random interval
1233 * to the recovery time to prevent this race. 1233 * to the recovery time to prevent this race.
1234 */ 1234 */
1235 schedule_delayed_work(&ndev->hb_timer, BWD_LINK_RECOVERY_TIME 1235 schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_RECOVERY_TIME
1236 + prandom_u32() % BWD_LINK_RECOVERY_TIME); 1236 + prandom_u32() % ATOM_LINK_RECOVERY_TIME);
1237} 1237}
1238 1238
1239static int bwd_init_isr(struct intel_ntb_dev *ndev) 1239static int atom_init_isr(struct intel_ntb_dev *ndev)
1240{ 1240{
1241 int rc; 1241 int rc;
1242 1242
1243 rc = ndev_init_isr(ndev, 1, BWD_DB_MSIX_VECTOR_COUNT, 1243 rc = ndev_init_isr(ndev, 1, ATOM_DB_MSIX_VECTOR_COUNT,
1244 BWD_DB_MSIX_VECTOR_SHIFT, BWD_DB_TOTAL_SHIFT); 1244 ATOM_DB_MSIX_VECTOR_SHIFT, ATOM_DB_TOTAL_SHIFT);
1245 if (rc) 1245 if (rc)
1246 return rc; 1246 return rc;
1247 1247
1248 /* BWD doesn't have link status interrupt, poll on that platform */ 1248 /* ATOM doesn't have link status interrupt, poll on that platform */
1249 ndev->last_ts = jiffies; 1249 ndev->last_ts = jiffies;
1250 INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_hb); 1250 INIT_DELAYED_WORK(&ndev->hb_timer, atom_link_hb);
1251 schedule_delayed_work(&ndev->hb_timer, BWD_LINK_HB_TIMEOUT); 1251 schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT);
1252 1252
1253 return 0; 1253 return 0;
1254} 1254}
1255 1255
1256static void bwd_deinit_isr(struct intel_ntb_dev *ndev) 1256static void atom_deinit_isr(struct intel_ntb_dev *ndev)
1257{ 1257{
1258 cancel_delayed_work_sync(&ndev->hb_timer); 1258 cancel_delayed_work_sync(&ndev->hb_timer);
1259 ndev_deinit_isr(ndev); 1259 ndev_deinit_isr(ndev);
1260} 1260}
1261 1261
1262static int bwd_init_ntb(struct intel_ntb_dev *ndev) 1262static int atom_init_ntb(struct intel_ntb_dev *ndev)
1263{ 1263{
1264 ndev->mw_count = BWD_MW_COUNT; 1264 ndev->mw_count = ATOM_MW_COUNT;
1265 ndev->spad_count = BWD_SPAD_COUNT; 1265 ndev->spad_count = ATOM_SPAD_COUNT;
1266 ndev->db_count = BWD_DB_COUNT; 1266 ndev->db_count = ATOM_DB_COUNT;
1267 1267
1268 switch (ndev->ntb.topo) { 1268 switch (ndev->ntb.topo) {
1269 case NTB_TOPO_B2B_USD: 1269 case NTB_TOPO_B2B_USD:
1270 case NTB_TOPO_B2B_DSD: 1270 case NTB_TOPO_B2B_DSD:
1271 ndev->self_reg = &bwd_pri_reg; 1271 ndev->self_reg = &atom_pri_reg;
1272 ndev->peer_reg = &bwd_b2b_reg; 1272 ndev->peer_reg = &atom_b2b_reg;
1273 ndev->xlat_reg = &bwd_sec_xlat; 1273 ndev->xlat_reg = &atom_sec_xlat;
1274 1274
1275 /* Enable Bus Master and Memory Space on the secondary side */ 1275 /* Enable Bus Master and Memory Space on the secondary side */
1276 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, 1276 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
1277 ndev->self_mmio + BWD_SPCICMD_OFFSET); 1277 ndev->self_mmio + ATOM_SPCICMD_OFFSET);
1278 1278
1279 break; 1279 break;
1280 1280
@@ -1287,31 +1287,31 @@ static int bwd_init_ntb(struct intel_ntb_dev *ndev)
1287 return 0; 1287 return 0;
1288} 1288}
1289 1289
1290static int bwd_init_dev(struct intel_ntb_dev *ndev) 1290static int atom_init_dev(struct intel_ntb_dev *ndev)
1291{ 1291{
1292 u32 ppd; 1292 u32 ppd;
1293 int rc; 1293 int rc;
1294 1294
1295 rc = pci_read_config_dword(ndev->ntb.pdev, BWD_PPD_OFFSET, &ppd); 1295 rc = pci_read_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET, &ppd);
1296 if (rc) 1296 if (rc)
1297 return -EIO; 1297 return -EIO;
1298 1298
1299 ndev->ntb.topo = bwd_ppd_topo(ndev, ppd); 1299 ndev->ntb.topo = atom_ppd_topo(ndev, ppd);
1300 if (ndev->ntb.topo == NTB_TOPO_NONE) 1300 if (ndev->ntb.topo == NTB_TOPO_NONE)
1301 return -EINVAL; 1301 return -EINVAL;
1302 1302
1303 rc = bwd_init_ntb(ndev); 1303 rc = atom_init_ntb(ndev);
1304 if (rc) 1304 if (rc)
1305 return rc; 1305 return rc;
1306 1306
1307 rc = bwd_init_isr(ndev); 1307 rc = atom_init_isr(ndev);
1308 if (rc) 1308 if (rc)
1309 return rc; 1309 return rc;
1310 1310
1311 if (ndev->ntb.topo != NTB_TOPO_SEC) { 1311 if (ndev->ntb.topo != NTB_TOPO_SEC) {
1312 /* Initiate PCI-E link training */ 1312 /* Initiate PCI-E link training */
1313 rc = pci_write_config_dword(ndev->ntb.pdev, BWD_PPD_OFFSET, 1313 rc = pci_write_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET,
1314 ppd | BWD_PPD_INIT_LINK); 1314 ppd | ATOM_PPD_INIT_LINK);
1315 if (rc) 1315 if (rc)
1316 return rc; 1316 return rc;
1317 } 1317 }
@@ -1319,24 +1319,24 @@ static int bwd_init_dev(struct intel_ntb_dev *ndev)
1319 return 0; 1319 return 0;
1320} 1320}
1321 1321
1322static void bwd_deinit_dev(struct intel_ntb_dev *ndev) 1322static void atom_deinit_dev(struct intel_ntb_dev *ndev)
1323{ 1323{
1324 bwd_deinit_isr(ndev); 1324 atom_deinit_isr(ndev);
1325} 1325}
1326 1326
1327/* SNB */ 1327/* XEON */
1328 1328
1329static u64 snb_db_ioread(void __iomem *mmio) 1329static u64 xeon_db_ioread(void __iomem *mmio)
1330{ 1330{
1331 return (u64)ioread16(mmio); 1331 return (u64)ioread16(mmio);
1332} 1332}
1333 1333
1334static void snb_db_iowrite(u64 bits, void __iomem *mmio) 1334static void xeon_db_iowrite(u64 bits, void __iomem *mmio)
1335{ 1335{
1336 iowrite16((u16)bits, mmio); 1336 iowrite16((u16)bits, mmio);
1337} 1337}
1338 1338
1339static int snb_poll_link(struct intel_ntb_dev *ndev) 1339static int xeon_poll_link(struct intel_ntb_dev *ndev)
1340{ 1340{
1341 u16 reg_val; 1341 u16 reg_val;
1342 int rc; 1342 int rc;
@@ -1346,7 +1346,7 @@ static int snb_poll_link(struct intel_ntb_dev *ndev)
1346 ndev->self_reg->db_bell); 1346 ndev->self_reg->db_bell);
1347 1347
1348 rc = pci_read_config_word(ndev->ntb.pdev, 1348 rc = pci_read_config_word(ndev->ntb.pdev,
1349 SNB_LINK_STATUS_OFFSET, &reg_val); 1349 XEON_LINK_STATUS_OFFSET, &reg_val);
1350 if (rc) 1350 if (rc)
1351 return 0; 1351 return 0;
1352 1352
@@ -1358,7 +1358,7 @@ static int snb_poll_link(struct intel_ntb_dev *ndev)
1358 return 1; 1358 return 1;
1359} 1359}
1360 1360
1361static int snb_link_is_up(struct intel_ntb_dev *ndev) 1361static int xeon_link_is_up(struct intel_ntb_dev *ndev)
1362{ 1362{
1363 if (ndev->ntb.topo == NTB_TOPO_SEC) 1363 if (ndev->ntb.topo == NTB_TOPO_SEC)
1364 return 1; 1364 return 1;
@@ -1366,52 +1366,52 @@ static int snb_link_is_up(struct intel_ntb_dev *ndev)
1366 return NTB_LNK_STA_ACTIVE(ndev->lnk_sta); 1366 return NTB_LNK_STA_ACTIVE(ndev->lnk_sta);
1367} 1367}
1368 1368
1369static inline enum ntb_topo snb_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd) 1369static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd)
1370{ 1370{
1371 switch (ppd & SNB_PPD_TOPO_MASK) { 1371 switch (ppd & XEON_PPD_TOPO_MASK) {
1372 case SNB_PPD_TOPO_B2B_USD: 1372 case XEON_PPD_TOPO_B2B_USD:
1373 return NTB_TOPO_B2B_USD; 1373 return NTB_TOPO_B2B_USD;
1374 1374
1375 case SNB_PPD_TOPO_B2B_DSD: 1375 case XEON_PPD_TOPO_B2B_DSD:
1376 return NTB_TOPO_B2B_DSD; 1376 return NTB_TOPO_B2B_DSD;
1377 1377
1378 case SNB_PPD_TOPO_PRI_USD: 1378 case XEON_PPD_TOPO_PRI_USD:
1379 case SNB_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ 1379 case XEON_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */
1380 return NTB_TOPO_PRI; 1380 return NTB_TOPO_PRI;
1381 1381
1382 case SNB_PPD_TOPO_SEC_USD: 1382 case XEON_PPD_TOPO_SEC_USD:
1383 case SNB_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ 1383 case XEON_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */
1384 return NTB_TOPO_SEC; 1384 return NTB_TOPO_SEC;
1385 } 1385 }
1386 1386
1387 return NTB_TOPO_NONE; 1387 return NTB_TOPO_NONE;
1388} 1388}
1389 1389
1390static inline int snb_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd) 1390static inline int xeon_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd)
1391{ 1391{
1392 if (ppd & SNB_PPD_SPLIT_BAR_MASK) { 1392 if (ppd & XEON_PPD_SPLIT_BAR_MASK) {
1393 dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd); 1393 dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd);
1394 return 1; 1394 return 1;
1395 } 1395 }
1396 return 0; 1396 return 0;
1397} 1397}
1398 1398
1399static int snb_init_isr(struct intel_ntb_dev *ndev) 1399static int xeon_init_isr(struct intel_ntb_dev *ndev)
1400{ 1400{
1401 return ndev_init_isr(ndev, SNB_DB_MSIX_VECTOR_COUNT, 1401 return ndev_init_isr(ndev, XEON_DB_MSIX_VECTOR_COUNT,
1402 SNB_DB_MSIX_VECTOR_COUNT, 1402 XEON_DB_MSIX_VECTOR_COUNT,
1403 SNB_DB_MSIX_VECTOR_SHIFT, 1403 XEON_DB_MSIX_VECTOR_SHIFT,
1404 SNB_DB_TOTAL_SHIFT); 1404 XEON_DB_TOTAL_SHIFT);
1405} 1405}
1406 1406
1407static void snb_deinit_isr(struct intel_ntb_dev *ndev) 1407static void xeon_deinit_isr(struct intel_ntb_dev *ndev)
1408{ 1408{
1409 ndev_deinit_isr(ndev); 1409 ndev_deinit_isr(ndev);
1410} 1410}
1411 1411
1412static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, 1412static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
1413 const struct intel_b2b_addr *addr, 1413 const struct intel_b2b_addr *addr,
1414 const struct intel_b2b_addr *peer_addr) 1414 const struct intel_b2b_addr *peer_addr)
1415{ 1415{
1416 struct pci_dev *pdev; 1416 struct pci_dev *pdev;
1417 void __iomem *mmio; 1417 void __iomem *mmio;
@@ -1438,11 +1438,11 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1438 1438
1439 dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size); 1439 dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size);
1440 1440
1441 if (b2b_mw_share && SNB_B2B_MIN_SIZE <= bar_size >> 1) { 1441 if (b2b_mw_share && XEON_B2B_MIN_SIZE <= bar_size >> 1) {
1442 dev_dbg(ndev_dev(ndev), 1442 dev_dbg(ndev_dev(ndev),
1443 "b2b using first half of bar\n"); 1443 "b2b using first half of bar\n");
1444 ndev->b2b_off = bar_size >> 1; 1444 ndev->b2b_off = bar_size >> 1;
1445 } else if (SNB_B2B_MIN_SIZE <= bar_size) { 1445 } else if (XEON_B2B_MIN_SIZE <= bar_size) {
1446 dev_dbg(ndev_dev(ndev), 1446 dev_dbg(ndev_dev(ndev),
1447 "b2b using whole bar\n"); 1447 "b2b using whole bar\n");
1448 ndev->b2b_off = 0; 1448 ndev->b2b_off = 0;
@@ -1460,7 +1460,7 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1460 * Note: code for each specific bar size register, because the register 1460 * Note: code for each specific bar size register, because the register
1461 * offsets are not in a consistent order (bar5sz comes after ppd, odd). 1461 * offsets are not in a consistent order (bar5sz comes after ppd, odd).
1462 */ 1462 */
1463 pci_read_config_byte(pdev, SNB_PBAR23SZ_OFFSET, &bar_sz); 1463 pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz);
1464 dev_dbg(ndev_dev(ndev), "PBAR23SZ %#x\n", bar_sz); 1464 dev_dbg(ndev_dev(ndev), "PBAR23SZ %#x\n", bar_sz);
1465 if (b2b_bar == 2) { 1465 if (b2b_bar == 2) {
1466 if (ndev->b2b_off) 1466 if (ndev->b2b_off)
@@ -1468,12 +1468,12 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1468 else 1468 else
1469 bar_sz = 0; 1469 bar_sz = 0;
1470 } 1470 }
1471 pci_write_config_byte(pdev, SNB_SBAR23SZ_OFFSET, bar_sz); 1471 pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz);
1472 pci_read_config_byte(pdev, SNB_SBAR23SZ_OFFSET, &bar_sz); 1472 pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz);
1473 dev_dbg(ndev_dev(ndev), "SBAR23SZ %#x\n", bar_sz); 1473 dev_dbg(ndev_dev(ndev), "SBAR23SZ %#x\n", bar_sz);
1474 1474
1475 if (!ndev->bar4_split) { 1475 if (!ndev->bar4_split) {
1476 pci_read_config_byte(pdev, SNB_PBAR45SZ_OFFSET, &bar_sz); 1476 pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz);
1477 dev_dbg(ndev_dev(ndev), "PBAR45SZ %#x\n", bar_sz); 1477 dev_dbg(ndev_dev(ndev), "PBAR45SZ %#x\n", bar_sz);
1478 if (b2b_bar == 4) { 1478 if (b2b_bar == 4) {
1479 if (ndev->b2b_off) 1479 if (ndev->b2b_off)
@@ -1481,11 +1481,11 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1481 else 1481 else
1482 bar_sz = 0; 1482 bar_sz = 0;
1483 } 1483 }
1484 pci_write_config_byte(pdev, SNB_SBAR45SZ_OFFSET, bar_sz); 1484 pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz);
1485 pci_read_config_byte(pdev, SNB_SBAR45SZ_OFFSET, &bar_sz); 1485 pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz);
1486 dev_dbg(ndev_dev(ndev), "SBAR45SZ %#x\n", bar_sz); 1486 dev_dbg(ndev_dev(ndev), "SBAR45SZ %#x\n", bar_sz);
1487 } else { 1487 } else {
1488 pci_read_config_byte(pdev, SNB_PBAR4SZ_OFFSET, &bar_sz); 1488 pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz);
1489 dev_dbg(ndev_dev(ndev), "PBAR4SZ %#x\n", bar_sz); 1489 dev_dbg(ndev_dev(ndev), "PBAR4SZ %#x\n", bar_sz);
1490 if (b2b_bar == 4) { 1490 if (b2b_bar == 4) {
1491 if (ndev->b2b_off) 1491 if (ndev->b2b_off)
@@ -1493,11 +1493,11 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1493 else 1493 else
1494 bar_sz = 0; 1494 bar_sz = 0;
1495 } 1495 }
1496 pci_write_config_byte(pdev, SNB_SBAR4SZ_OFFSET, bar_sz); 1496 pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz);
1497 pci_read_config_byte(pdev, SNB_SBAR4SZ_OFFSET, &bar_sz); 1497 pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz);
1498 dev_dbg(ndev_dev(ndev), "SBAR4SZ %#x\n", bar_sz); 1498 dev_dbg(ndev_dev(ndev), "SBAR4SZ %#x\n", bar_sz);
1499 1499
1500 pci_read_config_byte(pdev, SNB_PBAR5SZ_OFFSET, &bar_sz); 1500 pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz);
1501 dev_dbg(ndev_dev(ndev), "PBAR5SZ %#x\n", bar_sz); 1501 dev_dbg(ndev_dev(ndev), "PBAR5SZ %#x\n", bar_sz);
1502 if (b2b_bar == 5) { 1502 if (b2b_bar == 5) {
1503 if (ndev->b2b_off) 1503 if (ndev->b2b_off)
@@ -1505,8 +1505,8 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1505 else 1505 else
1506 bar_sz = 0; 1506 bar_sz = 0;
1507 } 1507 }
1508 pci_write_config_byte(pdev, SNB_SBAR5SZ_OFFSET, bar_sz); 1508 pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz);
1509 pci_read_config_byte(pdev, SNB_SBAR5SZ_OFFSET, &bar_sz); 1509 pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz);
1510 dev_dbg(ndev_dev(ndev), "SBAR5SZ %#x\n", bar_sz); 1510 dev_dbg(ndev_dev(ndev), "SBAR5SZ %#x\n", bar_sz);
1511 } 1511 }
1512 1512
@@ -1525,7 +1525,7 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1525 return -EIO; 1525 return -EIO;
1526 1526
1527 dev_dbg(ndev_dev(ndev), "SBAR01 %#018llx\n", bar_addr); 1527 dev_dbg(ndev_dev(ndev), "SBAR01 %#018llx\n", bar_addr);
1528 iowrite64(bar_addr, mmio + SNB_SBAR0BASE_OFFSET); 1528 iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET);
1529 1529
1530 /* Other SBAR are normally hit by the PBAR xlat, except for b2b bar. 1530 /* Other SBAR are normally hit by the PBAR xlat, except for b2b bar.
1531 * The b2b bar is either disabled above, or configured half-size, and 1531 * The b2b bar is either disabled above, or configured half-size, and
@@ -1533,96 +1533,96 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1533 */ 1533 */
1534 1534
1535 bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); 1535 bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
1536 iowrite64(bar_addr, mmio + SNB_SBAR23BASE_OFFSET); 1536 iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET);
1537 bar_addr = ioread64(mmio + SNB_SBAR23BASE_OFFSET); 1537 bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
1538 dev_dbg(ndev_dev(ndev), "SBAR23 %#018llx\n", bar_addr); 1538 dev_dbg(ndev_dev(ndev), "SBAR23 %#018llx\n", bar_addr);
1539 1539
1540 if (!ndev->bar4_split) { 1540 if (!ndev->bar4_split) {
1541 bar_addr = addr->bar4_addr64 + 1541 bar_addr = addr->bar4_addr64 +
1542 (b2b_bar == 4 ? ndev->b2b_off : 0); 1542 (b2b_bar == 4 ? ndev->b2b_off : 0);
1543 iowrite64(bar_addr, mmio + SNB_SBAR45BASE_OFFSET); 1543 iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET);
1544 bar_addr = ioread64(mmio + SNB_SBAR45BASE_OFFSET); 1544 bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
1545 dev_dbg(ndev_dev(ndev), "SBAR45 %#018llx\n", bar_addr); 1545 dev_dbg(ndev_dev(ndev), "SBAR45 %#018llx\n", bar_addr);
1546 } else { 1546 } else {
1547 bar_addr = addr->bar4_addr32 + 1547 bar_addr = addr->bar4_addr32 +
1548 (b2b_bar == 4 ? ndev->b2b_off : 0); 1548 (b2b_bar == 4 ? ndev->b2b_off : 0);
1549 iowrite32(bar_addr, mmio + SNB_SBAR4BASE_OFFSET); 1549 iowrite32(bar_addr, mmio + XEON_SBAR4BASE_OFFSET);
1550 bar_addr = ioread32(mmio + SNB_SBAR4BASE_OFFSET); 1550 bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET);
1551 dev_dbg(ndev_dev(ndev), "SBAR4 %#010llx\n", bar_addr); 1551 dev_dbg(ndev_dev(ndev), "SBAR4 %#010llx\n", bar_addr);
1552 1552
1553 bar_addr = addr->bar5_addr32 + 1553 bar_addr = addr->bar5_addr32 +
1554 (b2b_bar == 5 ? ndev->b2b_off : 0); 1554 (b2b_bar == 5 ? ndev->b2b_off : 0);
1555 iowrite32(bar_addr, mmio + SNB_SBAR5BASE_OFFSET); 1555 iowrite32(bar_addr, mmio + XEON_SBAR5BASE_OFFSET);
1556 bar_addr = ioread32(mmio + SNB_SBAR5BASE_OFFSET); 1556 bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET);
1557 dev_dbg(ndev_dev(ndev), "SBAR5 %#010llx\n", bar_addr); 1557 dev_dbg(ndev_dev(ndev), "SBAR5 %#010llx\n", bar_addr);
1558 } 1558 }
1559 1559
1560 /* setup incoming bar limits == base addrs (zero length windows) */ 1560 /* setup incoming bar limits == base addrs (zero length windows) */
1561 1561
1562 bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); 1562 bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
1563 iowrite64(bar_addr, mmio + SNB_SBAR23LMT_OFFSET); 1563 iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET);
1564 bar_addr = ioread64(mmio + SNB_SBAR23LMT_OFFSET); 1564 bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET);
1565 dev_dbg(ndev_dev(ndev), "SBAR23LMT %#018llx\n", bar_addr); 1565 dev_dbg(ndev_dev(ndev), "SBAR23LMT %#018llx\n", bar_addr);
1566 1566
1567 if (!ndev->bar4_split) { 1567 if (!ndev->bar4_split) {
1568 bar_addr = addr->bar4_addr64 + 1568 bar_addr = addr->bar4_addr64 +
1569 (b2b_bar == 4 ? ndev->b2b_off : 0); 1569 (b2b_bar == 4 ? ndev->b2b_off : 0);
1570 iowrite64(bar_addr, mmio + SNB_SBAR45LMT_OFFSET); 1570 iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET);
1571 bar_addr = ioread64(mmio + SNB_SBAR45LMT_OFFSET); 1571 bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET);
1572 dev_dbg(ndev_dev(ndev), "SBAR45LMT %#018llx\n", bar_addr); 1572 dev_dbg(ndev_dev(ndev), "SBAR45LMT %#018llx\n", bar_addr);
1573 } else { 1573 } else {
1574 bar_addr = addr->bar4_addr32 + 1574 bar_addr = addr->bar4_addr32 +
1575 (b2b_bar == 4 ? ndev->b2b_off : 0); 1575 (b2b_bar == 4 ? ndev->b2b_off : 0);
1576 iowrite32(bar_addr, mmio + SNB_SBAR4LMT_OFFSET); 1576 iowrite32(bar_addr, mmio + XEON_SBAR4LMT_OFFSET);
1577 bar_addr = ioread32(mmio + SNB_SBAR4LMT_OFFSET); 1577 bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET);
1578 dev_dbg(ndev_dev(ndev), "SBAR4LMT %#010llx\n", bar_addr); 1578 dev_dbg(ndev_dev(ndev), "SBAR4LMT %#010llx\n", bar_addr);
1579 1579
1580 bar_addr = addr->bar5_addr32 + 1580 bar_addr = addr->bar5_addr32 +
1581 (b2b_bar == 5 ? ndev->b2b_off : 0); 1581 (b2b_bar == 5 ? ndev->b2b_off : 0);
1582 iowrite32(bar_addr, mmio + SNB_SBAR5LMT_OFFSET); 1582 iowrite32(bar_addr, mmio + XEON_SBAR5LMT_OFFSET);
1583 bar_addr = ioread32(mmio + SNB_SBAR5LMT_OFFSET); 1583 bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET);
1584 dev_dbg(ndev_dev(ndev), "SBAR5LMT %#05llx\n", bar_addr); 1584 dev_dbg(ndev_dev(ndev), "SBAR5LMT %#05llx\n", bar_addr);
1585 } 1585 }
1586 1586
1587 /* zero incoming translation addrs */ 1587 /* zero incoming translation addrs */
1588 iowrite64(0, mmio + SNB_SBAR23XLAT_OFFSET); 1588 iowrite64(0, mmio + XEON_SBAR23XLAT_OFFSET);
1589 1589
1590 if (!ndev->bar4_split) { 1590 if (!ndev->bar4_split) {
1591 iowrite64(0, mmio + SNB_SBAR45XLAT_OFFSET); 1591 iowrite64(0, mmio + XEON_SBAR45XLAT_OFFSET);
1592 } else { 1592 } else {
1593 iowrite32(0, mmio + SNB_SBAR4XLAT_OFFSET); 1593 iowrite32(0, mmio + XEON_SBAR4XLAT_OFFSET);
1594 iowrite32(0, mmio + SNB_SBAR5XLAT_OFFSET); 1594 iowrite32(0, mmio + XEON_SBAR5XLAT_OFFSET);
1595 } 1595 }
1596 1596
1597 /* zero outgoing translation limits (whole bar size windows) */ 1597 /* zero outgoing translation limits (whole bar size windows) */
1598 iowrite64(0, mmio + SNB_PBAR23LMT_OFFSET); 1598 iowrite64(0, mmio + XEON_PBAR23LMT_OFFSET);
1599 if (!ndev->bar4_split) { 1599 if (!ndev->bar4_split) {
1600 iowrite64(0, mmio + SNB_PBAR45LMT_OFFSET); 1600 iowrite64(0, mmio + XEON_PBAR45LMT_OFFSET);
1601 } else { 1601 } else {
1602 iowrite32(0, mmio + SNB_PBAR4LMT_OFFSET); 1602 iowrite32(0, mmio + XEON_PBAR4LMT_OFFSET);
1603 iowrite32(0, mmio + SNB_PBAR5LMT_OFFSET); 1603 iowrite32(0, mmio + XEON_PBAR5LMT_OFFSET);
1604 } 1604 }
1605 1605
1606 /* set outgoing translation offsets */ 1606 /* set outgoing translation offsets */
1607 bar_addr = peer_addr->bar2_addr64; 1607 bar_addr = peer_addr->bar2_addr64;
1608 iowrite64(bar_addr, mmio + SNB_PBAR23XLAT_OFFSET); 1608 iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET);
1609 bar_addr = ioread64(mmio + SNB_PBAR23XLAT_OFFSET); 1609 bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
1610 dev_dbg(ndev_dev(ndev), "PBAR23XLAT %#018llx\n", bar_addr); 1610 dev_dbg(ndev_dev(ndev), "PBAR23XLAT %#018llx\n", bar_addr);
1611 1611
1612 if (!ndev->bar4_split) { 1612 if (!ndev->bar4_split) {
1613 bar_addr = peer_addr->bar4_addr64; 1613 bar_addr = peer_addr->bar4_addr64;
1614 iowrite64(bar_addr, mmio + SNB_PBAR45XLAT_OFFSET); 1614 iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET);
1615 bar_addr = ioread64(mmio + SNB_PBAR45XLAT_OFFSET); 1615 bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
1616 dev_dbg(ndev_dev(ndev), "PBAR45XLAT %#018llx\n", bar_addr); 1616 dev_dbg(ndev_dev(ndev), "PBAR45XLAT %#018llx\n", bar_addr);
1617 } else { 1617 } else {
1618 bar_addr = peer_addr->bar4_addr32; 1618 bar_addr = peer_addr->bar4_addr32;
1619 iowrite32(bar_addr, mmio + SNB_PBAR4XLAT_OFFSET); 1619 iowrite32(bar_addr, mmio + XEON_PBAR4XLAT_OFFSET);
1620 bar_addr = ioread32(mmio + SNB_PBAR4XLAT_OFFSET); 1620 bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET);
1621 dev_dbg(ndev_dev(ndev), "PBAR4XLAT %#010llx\n", bar_addr); 1621 dev_dbg(ndev_dev(ndev), "PBAR4XLAT %#010llx\n", bar_addr);
1622 1622
1623 bar_addr = peer_addr->bar5_addr32; 1623 bar_addr = peer_addr->bar5_addr32;
1624 iowrite32(bar_addr, mmio + SNB_PBAR5XLAT_OFFSET); 1624 iowrite32(bar_addr, mmio + XEON_PBAR5XLAT_OFFSET);
1625 bar_addr = ioread32(mmio + SNB_PBAR5XLAT_OFFSET); 1625 bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET);
1626 dev_dbg(ndev_dev(ndev), "PBAR5XLAT %#010llx\n", bar_addr); 1626 dev_dbg(ndev_dev(ndev), "PBAR5XLAT %#010llx\n", bar_addr);
1627 } 1627 }
1628 1628
@@ -1642,13 +1642,13 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1642 1642
1643 /* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */ 1643 /* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */
1644 dev_dbg(ndev_dev(ndev), "B2BXLAT %#018llx\n", bar_addr); 1644 dev_dbg(ndev_dev(ndev), "B2BXLAT %#018llx\n", bar_addr);
1645 iowrite32(bar_addr, mmio + SNB_B2B_XLAT_OFFSETL); 1645 iowrite32(bar_addr, mmio + XEON_B2B_XLAT_OFFSETL);
1646 iowrite32(bar_addr >> 32, mmio + SNB_B2B_XLAT_OFFSETU); 1646 iowrite32(bar_addr >> 32, mmio + XEON_B2B_XLAT_OFFSETU);
1647 1647
1648 if (b2b_bar) { 1648 if (b2b_bar) {
1649 /* map peer ntb mmio config space registers */ 1649 /* map peer ntb mmio config space registers */
1650 ndev->peer_mmio = pci_iomap(pdev, b2b_bar, 1650 ndev->peer_mmio = pci_iomap(pdev, b2b_bar,
1651 SNB_B2B_MIN_SIZE); 1651 XEON_B2B_MIN_SIZE);
1652 if (!ndev->peer_mmio) 1652 if (!ndev->peer_mmio)
1653 return -EIO; 1653 return -EIO;
1654 } 1654 }
@@ -1656,7 +1656,7 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev,
1656 return 0; 1656 return 0;
1657} 1657}
1658 1658
1659static int snb_init_ntb(struct intel_ntb_dev *ndev) 1659static int xeon_init_ntb(struct intel_ntb_dev *ndev)
1660{ 1660{
1661 int rc; 1661 int rc;
1662 u32 ntb_ctl; 1662 u32 ntb_ctl;
@@ -1664,11 +1664,11 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev)
1664 if (ndev->bar4_split) 1664 if (ndev->bar4_split)
1665 ndev->mw_count = HSX_SPLIT_BAR_MW_COUNT; 1665 ndev->mw_count = HSX_SPLIT_BAR_MW_COUNT;
1666 else 1666 else
1667 ndev->mw_count = SNB_MW_COUNT; 1667 ndev->mw_count = XEON_MW_COUNT;
1668 1668
1669 ndev->spad_count = SNB_SPAD_COUNT; 1669 ndev->spad_count = XEON_SPAD_COUNT;
1670 ndev->db_count = SNB_DB_COUNT; 1670 ndev->db_count = XEON_DB_COUNT;
1671 ndev->db_link_mask = SNB_DB_LINK_BIT; 1671 ndev->db_link_mask = XEON_DB_LINK_BIT;
1672 1672
1673 switch (ndev->ntb.topo) { 1673 switch (ndev->ntb.topo) {
1674 case NTB_TOPO_PRI: 1674 case NTB_TOPO_PRI:
@@ -1684,9 +1684,9 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev)
1684 1684
1685 /* use half the spads for the peer */ 1685 /* use half the spads for the peer */
1686 ndev->spad_count >>= 1; 1686 ndev->spad_count >>= 1;
1687 ndev->self_reg = &snb_pri_reg; 1687 ndev->self_reg = &xeon_pri_reg;
1688 ndev->peer_reg = &snb_sec_reg; 1688 ndev->peer_reg = &xeon_sec_reg;
1689 ndev->xlat_reg = &snb_sec_xlat; 1689 ndev->xlat_reg = &xeon_sec_xlat;
1690 break; 1690 break;
1691 1691
1692 case NTB_TOPO_SEC: 1692 case NTB_TOPO_SEC:
@@ -1696,19 +1696,19 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev)
1696 } 1696 }
1697 /* use half the spads for the peer */ 1697 /* use half the spads for the peer */
1698 ndev->spad_count >>= 1; 1698 ndev->spad_count >>= 1;
1699 ndev->self_reg = &snb_sec_reg; 1699 ndev->self_reg = &xeon_sec_reg;
1700 ndev->peer_reg = &snb_pri_reg; 1700 ndev->peer_reg = &xeon_pri_reg;
1701 ndev->xlat_reg = &snb_pri_xlat; 1701 ndev->xlat_reg = &xeon_pri_xlat;
1702 break; 1702 break;
1703 1703
1704 case NTB_TOPO_B2B_USD: 1704 case NTB_TOPO_B2B_USD:
1705 case NTB_TOPO_B2B_DSD: 1705 case NTB_TOPO_B2B_DSD:
1706 ndev->self_reg = &snb_pri_reg; 1706 ndev->self_reg = &xeon_pri_reg;
1707 ndev->peer_reg = &snb_b2b_reg; 1707 ndev->peer_reg = &xeon_b2b_reg;
1708 ndev->xlat_reg = &snb_sec_xlat; 1708 ndev->xlat_reg = &xeon_sec_xlat;
1709 1709
1710 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { 1710 if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
1711 ndev->peer_reg = &snb_pri_reg; 1711 ndev->peer_reg = &xeon_pri_reg;
1712 1712
1713 if (b2b_mw_idx < 0) 1713 if (b2b_mw_idx < 0)
1714 ndev->b2b_idx = b2b_mw_idx + ndev->mw_count; 1714 ndev->b2b_idx = b2b_mw_idx + ndev->mw_count;
@@ -1725,20 +1725,20 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev)
1725 } 1725 }
1726 1726
1727 if (ndev->ntb.topo == NTB_TOPO_B2B_USD) { 1727 if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {
1728 rc = snb_setup_b2b_mw(ndev, 1728 rc = xeon_setup_b2b_mw(ndev,
1729 &snb_b2b_dsd_addr, 1729 &xeon_b2b_dsd_addr,
1730 &snb_b2b_usd_addr); 1730 &xeon_b2b_usd_addr);
1731 } else { 1731 } else {
1732 rc = snb_setup_b2b_mw(ndev, 1732 rc = xeon_setup_b2b_mw(ndev,
1733 &snb_b2b_usd_addr, 1733 &xeon_b2b_usd_addr,
1734 &snb_b2b_dsd_addr); 1734 &xeon_b2b_dsd_addr);
1735 } 1735 }
1736 if (rc) 1736 if (rc)
1737 return rc; 1737 return rc;
1738 1738
1739 /* Enable Bus Master and Memory Space on the secondary side */ 1739 /* Enable Bus Master and Memory Space on the secondary side */
1740 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, 1740 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
1741 ndev->self_mmio + SNB_SPCICMD_OFFSET); 1741 ndev->self_mmio + XEON_SPCICMD_OFFSET);
1742 1742
1743 break; 1743 break;
1744 1744
@@ -1755,7 +1755,7 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev)
1755 return 0; 1755 return 0;
1756} 1756}
1757 1757
1758static int snb_init_dev(struct intel_ntb_dev *ndev) 1758static int xeon_init_dev(struct intel_ntb_dev *ndev)
1759{ 1759{
1760 struct pci_dev *pdev; 1760 struct pci_dev *pdev;
1761 u8 ppd; 1761 u8 ppd;
@@ -1821,20 +1821,20 @@ static int snb_init_dev(struct intel_ntb_dev *ndev)
1821 break; 1821 break;
1822 } 1822 }
1823 1823
1824 ndev->reg = &snb_reg; 1824 ndev->reg = &xeon_reg;
1825 1825
1826 rc = pci_read_config_byte(pdev, SNB_PPD_OFFSET, &ppd); 1826 rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);
1827 if (rc) 1827 if (rc)
1828 return -EIO; 1828 return -EIO;
1829 1829
1830 ndev->ntb.topo = snb_ppd_topo(ndev, ppd); 1830 ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
1831 dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd, 1831 dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd,
1832 ntb_topo_string(ndev->ntb.topo)); 1832 ntb_topo_string(ndev->ntb.topo));
1833 if (ndev->ntb.topo == NTB_TOPO_NONE) 1833 if (ndev->ntb.topo == NTB_TOPO_NONE)
1834 return -EINVAL; 1834 return -EINVAL;
1835 1835
1836 if (ndev->ntb.topo != NTB_TOPO_SEC) { 1836 if (ndev->ntb.topo != NTB_TOPO_SEC) {
1837 ndev->bar4_split = snb_ppd_bar4_split(ndev, ppd); 1837 ndev->bar4_split = xeon_ppd_bar4_split(ndev, ppd);
1838 dev_dbg(ndev_dev(ndev), "ppd %#x bar4_split %d\n", 1838 dev_dbg(ndev_dev(ndev), "ppd %#x bar4_split %d\n",
1839 ppd, ndev->bar4_split); 1839 ppd, ndev->bar4_split);
1840 } else { 1840 } else {
@@ -1849,16 +1849,16 @@ static int snb_init_dev(struct intel_ntb_dev *ndev)
1849 mem, ndev->bar4_split); 1849 mem, ndev->bar4_split);
1850 } 1850 }
1851 1851
1852 rc = snb_init_ntb(ndev); 1852 rc = xeon_init_ntb(ndev);
1853 if (rc) 1853 if (rc)
1854 return rc; 1854 return rc;
1855 1855
1856 return snb_init_isr(ndev); 1856 return xeon_init_isr(ndev);
1857} 1857}
1858 1858
1859static void snb_deinit_dev(struct intel_ntb_dev *ndev) 1859static void xeon_deinit_dev(struct intel_ntb_dev *ndev)
1860{ 1860{
1861 snb_deinit_isr(ndev); 1861 xeon_deinit_isr(ndev);
1862} 1862}
1863 1863
1864static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev) 1864static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev)
@@ -1963,7 +1963,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
1963 1963
1964 node = dev_to_node(&pdev->dev); 1964 node = dev_to_node(&pdev->dev);
1965 1965
1966 if (pdev_is_bwd(pdev)) { 1966 if (pdev_is_atom(pdev)) {
1967 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); 1967 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
1968 if (!ndev) { 1968 if (!ndev) {
1969 rc = -ENOMEM; 1969 rc = -ENOMEM;
@@ -1976,11 +1976,11 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
1976 if (rc) 1976 if (rc)
1977 goto err_init_pci; 1977 goto err_init_pci;
1978 1978
1979 rc = bwd_init_dev(ndev); 1979 rc = atom_init_dev(ndev);
1980 if (rc) 1980 if (rc)
1981 goto err_init_dev; 1981 goto err_init_dev;
1982 1982
1983 } else if (pdev_is_snb(pdev)) { 1983 } else if (pdev_is_xeon(pdev)) {
1984 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); 1984 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
1985 if (!ndev) { 1985 if (!ndev) {
1986 rc = -ENOMEM; 1986 rc = -ENOMEM;
@@ -1993,7 +1993,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
1993 if (rc) 1993 if (rc)
1994 goto err_init_pci; 1994 goto err_init_pci;
1995 1995
1996 rc = snb_init_dev(ndev); 1996 rc = xeon_init_dev(ndev);
1997 if (rc) 1997 if (rc)
1998 goto err_init_dev; 1998 goto err_init_dev;
1999 1999
@@ -2016,10 +2016,10 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
2016 2016
2017err_register: 2017err_register:
2018 ndev_deinit_debugfs(ndev); 2018 ndev_deinit_debugfs(ndev);
2019 if (pdev_is_bwd(pdev)) 2019 if (pdev_is_atom(pdev))
2020 bwd_deinit_dev(ndev); 2020 atom_deinit_dev(ndev);
2021 else if (pdev_is_snb(pdev)) 2021 else if (pdev_is_xeon(pdev))
2022 snb_deinit_dev(ndev); 2022 xeon_deinit_dev(ndev);
2023err_init_dev: 2023err_init_dev:
2024 intel_ntb_deinit_pci(ndev); 2024 intel_ntb_deinit_pci(ndev);
2025err_init_pci: 2025err_init_pci:
@@ -2034,70 +2034,70 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev)
2034 2034
2035 ntb_unregister_device(&ndev->ntb); 2035 ntb_unregister_device(&ndev->ntb);
2036 ndev_deinit_debugfs(ndev); 2036 ndev_deinit_debugfs(ndev);
2037 if (pdev_is_bwd(pdev)) 2037 if (pdev_is_atom(pdev))
2038 bwd_deinit_dev(ndev); 2038 atom_deinit_dev(ndev);
2039 else if (pdev_is_snb(pdev)) 2039 else if (pdev_is_xeon(pdev))
2040 snb_deinit_dev(ndev); 2040 xeon_deinit_dev(ndev);
2041 intel_ntb_deinit_pci(ndev); 2041 intel_ntb_deinit_pci(ndev);
2042 kfree(ndev); 2042 kfree(ndev);
2043} 2043}
2044 2044
2045static const struct intel_ntb_reg bwd_reg = { 2045static const struct intel_ntb_reg atom_reg = {
2046 .poll_link = bwd_poll_link, 2046 .poll_link = atom_poll_link,
2047 .link_is_up = bwd_link_is_up, 2047 .link_is_up = atom_link_is_up,
2048 .db_ioread = bwd_db_ioread, 2048 .db_ioread = atom_db_ioread,
2049 .db_iowrite = bwd_db_iowrite, 2049 .db_iowrite = atom_db_iowrite,
2050 .db_size = sizeof(u64), 2050 .db_size = sizeof(u64),
2051 .ntb_ctl = BWD_NTBCNTL_OFFSET, 2051 .ntb_ctl = ATOM_NTBCNTL_OFFSET,
2052 .mw_bar = {2, 4}, 2052 .mw_bar = {2, 4},
2053}; 2053};
2054 2054
2055static const struct intel_ntb_alt_reg bwd_pri_reg = { 2055static const struct intel_ntb_alt_reg atom_pri_reg = {
2056 .db_bell = BWD_PDOORBELL_OFFSET, 2056 .db_bell = ATOM_PDOORBELL_OFFSET,
2057 .db_mask = BWD_PDBMSK_OFFSET, 2057 .db_mask = ATOM_PDBMSK_OFFSET,
2058 .spad = BWD_SPAD_OFFSET, 2058 .spad = ATOM_SPAD_OFFSET,
2059}; 2059};
2060 2060
2061static const struct intel_ntb_alt_reg bwd_b2b_reg = { 2061static const struct intel_ntb_alt_reg atom_b2b_reg = {
2062 .db_bell = BWD_B2B_DOORBELL_OFFSET, 2062 .db_bell = ATOM_B2B_DOORBELL_OFFSET,
2063 .spad = BWD_B2B_SPAD_OFFSET, 2063 .spad = ATOM_B2B_SPAD_OFFSET,
2064}; 2064};
2065 2065
2066static const struct intel_ntb_xlat_reg bwd_sec_xlat = { 2066static const struct intel_ntb_xlat_reg atom_sec_xlat = {
2067 /* FIXME : .bar0_base = BWD_SBAR0BASE_OFFSET, */ 2067 /* FIXME : .bar0_base = ATOM_SBAR0BASE_OFFSET, */
2068 /* FIXME : .bar2_limit = BWD_SBAR2LMT_OFFSET, */ 2068 /* FIXME : .bar2_limit = ATOM_SBAR2LMT_OFFSET, */
2069 .bar2_xlat = BWD_SBAR2XLAT_OFFSET, 2069 .bar2_xlat = ATOM_SBAR2XLAT_OFFSET,
2070}; 2070};
2071 2071
2072static const struct intel_ntb_reg snb_reg = { 2072static const struct intel_ntb_reg xeon_reg = {
2073 .poll_link = snb_poll_link, 2073 .poll_link = xeon_poll_link,
2074 .link_is_up = snb_link_is_up, 2074 .link_is_up = xeon_link_is_up,
2075 .db_ioread = snb_db_ioread, 2075 .db_ioread = xeon_db_ioread,
2076 .db_iowrite = snb_db_iowrite, 2076 .db_iowrite = xeon_db_iowrite,
2077 .db_size = sizeof(u32), 2077 .db_size = sizeof(u32),
2078 .ntb_ctl = SNB_NTBCNTL_OFFSET, 2078 .ntb_ctl = XEON_NTBCNTL_OFFSET,
2079 .mw_bar = {2, 4, 5}, 2079 .mw_bar = {2, 4, 5},
2080}; 2080};
2081 2081
2082static const struct intel_ntb_alt_reg snb_pri_reg = { 2082static const struct intel_ntb_alt_reg xeon_pri_reg = {
2083 .db_bell = SNB_PDOORBELL_OFFSET, 2083 .db_bell = XEON_PDOORBELL_OFFSET,
2084 .db_mask = SNB_PDBMSK_OFFSET, 2084 .db_mask = XEON_PDBMSK_OFFSET,
2085 .spad = SNB_SPAD_OFFSET, 2085 .spad = XEON_SPAD_OFFSET,
2086}; 2086};
2087 2087
2088static const struct intel_ntb_alt_reg snb_sec_reg = { 2088static const struct intel_ntb_alt_reg xeon_sec_reg = {
2089 .db_bell = SNB_SDOORBELL_OFFSET, 2089 .db_bell = XEON_SDOORBELL_OFFSET,
2090 .db_mask = SNB_SDBMSK_OFFSET, 2090 .db_mask = XEON_SDBMSK_OFFSET,
2091 /* second half of the scratchpads */ 2091 /* second half of the scratchpads */
2092 .spad = SNB_SPAD_OFFSET + (SNB_SPAD_COUNT << 1), 2092 .spad = XEON_SPAD_OFFSET + (XEON_SPAD_COUNT << 1),
2093}; 2093};
2094 2094
2095static const struct intel_ntb_alt_reg snb_b2b_reg = { 2095static const struct intel_ntb_alt_reg xeon_b2b_reg = {
2096 .db_bell = SNB_B2B_DOORBELL_OFFSET, 2096 .db_bell = XEON_B2B_DOORBELL_OFFSET,
2097 .spad = SNB_B2B_SPAD_OFFSET, 2097 .spad = XEON_B2B_SPAD_OFFSET,
2098}; 2098};
2099 2099
2100static const struct intel_ntb_xlat_reg snb_pri_xlat = { 2100static const struct intel_ntb_xlat_reg xeon_pri_xlat = {
2101 /* Note: no primary .bar0_base visible to the secondary side. 2101 /* Note: no primary .bar0_base visible to the secondary side.
2102 * 2102 *
2103 * The secondary side cannot get the base address stored in primary 2103 * The secondary side cannot get the base address stored in primary
@@ -2108,28 +2108,28 @@ static const struct intel_ntb_xlat_reg snb_pri_xlat = {
2108 * window by setting the limit equal to base, nor can it limit the size 2108 * window by setting the limit equal to base, nor can it limit the size
2109 * of the memory window by setting the limit to base + size. 2109 * of the memory window by setting the limit to base + size.
2110 */ 2110 */
2111 .bar2_limit = SNB_PBAR23LMT_OFFSET, 2111 .bar2_limit = XEON_PBAR23LMT_OFFSET,
2112 .bar2_xlat = SNB_PBAR23XLAT_OFFSET, 2112 .bar2_xlat = XEON_PBAR23XLAT_OFFSET,
2113}; 2113};
2114 2114
2115static const struct intel_ntb_xlat_reg snb_sec_xlat = { 2115static const struct intel_ntb_xlat_reg xeon_sec_xlat = {
2116 .bar0_base = SNB_SBAR0BASE_OFFSET, 2116 .bar0_base = XEON_SBAR0BASE_OFFSET,
2117 .bar2_limit = SNB_SBAR23LMT_OFFSET, 2117 .bar2_limit = XEON_SBAR23LMT_OFFSET,
2118 .bar2_xlat = SNB_SBAR23XLAT_OFFSET, 2118 .bar2_xlat = XEON_SBAR23XLAT_OFFSET,
2119}; 2119};
2120 2120
2121static struct intel_b2b_addr snb_b2b_usd_addr = { 2121static struct intel_b2b_addr xeon_b2b_usd_addr = {
2122 .bar2_addr64 = SNB_B2B_BAR2_USD_ADDR64, 2122 .bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64,
2123 .bar4_addr64 = SNB_B2B_BAR4_USD_ADDR64, 2123 .bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64,
2124 .bar4_addr32 = SNB_B2B_BAR4_USD_ADDR32, 2124 .bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32,
2125 .bar5_addr32 = SNB_B2B_BAR5_USD_ADDR32, 2125 .bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32,
2126}; 2126};
2127 2127
2128static struct intel_b2b_addr snb_b2b_dsd_addr = { 2128static struct intel_b2b_addr xeon_b2b_dsd_addr = {
2129 .bar2_addr64 = SNB_B2B_BAR2_DSD_ADDR64, 2129 .bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64,
2130 .bar4_addr64 = SNB_B2B_BAR4_DSD_ADDR64, 2130 .bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64,
2131 .bar4_addr32 = SNB_B2B_BAR4_DSD_ADDR32, 2131 .bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32,
2132 .bar5_addr32 = SNB_B2B_BAR5_DSD_ADDR32, 2132 .bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32,
2133}; 2133};
2134 2134
2135/* operations for primary side of local ntb */ 2135/* operations for primary side of local ntb */
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
index fec689dc95cf..7ddaf387b679 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.h
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
@@ -68,141 +68,141 @@
68#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F 68#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
69#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E 69#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E
70 70
71/* SNB hardware (and JSF, IVT, HSX) */ 71/* Intel Xeon hardware */
72 72
73#define SNB_PBAR23LMT_OFFSET 0x0000 73#define XEON_PBAR23LMT_OFFSET 0x0000
74#define SNB_PBAR45LMT_OFFSET 0x0008 74#define XEON_PBAR45LMT_OFFSET 0x0008
75#define SNB_PBAR4LMT_OFFSET 0x0008 75#define XEON_PBAR4LMT_OFFSET 0x0008
76#define SNB_PBAR5LMT_OFFSET 0x000c 76#define XEON_PBAR5LMT_OFFSET 0x000c
77#define SNB_PBAR23XLAT_OFFSET 0x0010 77#define XEON_PBAR23XLAT_OFFSET 0x0010
78#define SNB_PBAR45XLAT_OFFSET 0x0018 78#define XEON_PBAR45XLAT_OFFSET 0x0018
79#define SNB_PBAR4XLAT_OFFSET 0x0018 79#define XEON_PBAR4XLAT_OFFSET 0x0018
80#define SNB_PBAR5XLAT_OFFSET 0x001c 80#define XEON_PBAR5XLAT_OFFSET 0x001c
81#define SNB_SBAR23LMT_OFFSET 0x0020 81#define XEON_SBAR23LMT_OFFSET 0x0020
82#define SNB_SBAR45LMT_OFFSET 0x0028 82#define XEON_SBAR45LMT_OFFSET 0x0028
83#define SNB_SBAR4LMT_OFFSET 0x0028 83#define XEON_SBAR4LMT_OFFSET 0x0028
84#define SNB_SBAR5LMT_OFFSET 0x002c 84#define XEON_SBAR5LMT_OFFSET 0x002c
85#define SNB_SBAR23XLAT_OFFSET 0x0030 85#define XEON_SBAR23XLAT_OFFSET 0x0030
86#define SNB_SBAR45XLAT_OFFSET 0x0038 86#define XEON_SBAR45XLAT_OFFSET 0x0038
87#define SNB_SBAR4XLAT_OFFSET 0x0038 87#define XEON_SBAR4XLAT_OFFSET 0x0038
88#define SNB_SBAR5XLAT_OFFSET 0x003c 88#define XEON_SBAR5XLAT_OFFSET 0x003c
89#define SNB_SBAR0BASE_OFFSET 0x0040 89#define XEON_SBAR0BASE_OFFSET 0x0040
90#define SNB_SBAR23BASE_OFFSET 0x0048 90#define XEON_SBAR23BASE_OFFSET 0x0048
91#define SNB_SBAR45BASE_OFFSET 0x0050 91#define XEON_SBAR45BASE_OFFSET 0x0050
92#define SNB_SBAR4BASE_OFFSET 0x0050 92#define XEON_SBAR4BASE_OFFSET 0x0050
93#define SNB_SBAR5BASE_OFFSET 0x0054 93#define XEON_SBAR5BASE_OFFSET 0x0054
94#define SNB_SBDF_OFFSET 0x005c 94#define XEON_SBDF_OFFSET 0x005c
95#define SNB_NTBCNTL_OFFSET 0x0058 95#define XEON_NTBCNTL_OFFSET 0x0058
96#define SNB_PDOORBELL_OFFSET 0x0060 96#define XEON_PDOORBELL_OFFSET 0x0060
97#define SNB_PDBMSK_OFFSET 0x0062 97#define XEON_PDBMSK_OFFSET 0x0062
98#define SNB_SDOORBELL_OFFSET 0x0064 98#define XEON_SDOORBELL_OFFSET 0x0064
99#define SNB_SDBMSK_OFFSET 0x0066 99#define XEON_SDBMSK_OFFSET 0x0066
100#define SNB_USMEMMISS_OFFSET 0x0070 100#define XEON_USMEMMISS_OFFSET 0x0070
101#define SNB_SPAD_OFFSET 0x0080 101#define XEON_SPAD_OFFSET 0x0080
102#define SNB_PBAR23SZ_OFFSET 0x00d0 102#define XEON_PBAR23SZ_OFFSET 0x00d0
103#define SNB_PBAR45SZ_OFFSET 0x00d1 103#define XEON_PBAR45SZ_OFFSET 0x00d1
104#define SNB_PBAR4SZ_OFFSET 0x00d1 104#define XEON_PBAR4SZ_OFFSET 0x00d1
105#define SNB_SBAR23SZ_OFFSET 0x00d2 105#define XEON_SBAR23SZ_OFFSET 0x00d2
106#define SNB_SBAR45SZ_OFFSET 0x00d3 106#define XEON_SBAR45SZ_OFFSET 0x00d3
107#define SNB_SBAR4SZ_OFFSET 0x00d3 107#define XEON_SBAR4SZ_OFFSET 0x00d3
108#define SNB_PPD_OFFSET 0x00d4 108#define XEON_PPD_OFFSET 0x00d4
109#define SNB_PBAR5SZ_OFFSET 0x00d5 109#define XEON_PBAR5SZ_OFFSET 0x00d5
110#define SNB_SBAR5SZ_OFFSET 0x00d6 110#define XEON_SBAR5SZ_OFFSET 0x00d6
111#define SNB_WCCNTRL_OFFSET 0x00e0 111#define XEON_WCCNTRL_OFFSET 0x00e0
112#define SNB_UNCERRSTS_OFFSET 0x014c 112#define XEON_UNCERRSTS_OFFSET 0x014c
113#define SNB_CORERRSTS_OFFSET 0x0158 113#define XEON_CORERRSTS_OFFSET 0x0158
114#define SNB_LINK_STATUS_OFFSET 0x01a2 114#define XEON_LINK_STATUS_OFFSET 0x01a2
115#define SNB_SPCICMD_OFFSET 0x0504 115#define XEON_SPCICMD_OFFSET 0x0504
116#define SNB_DEVCTRL_OFFSET 0x0598 116#define XEON_DEVCTRL_OFFSET 0x0598
117#define SNB_DEVSTS_OFFSET 0x059a 117#define XEON_DEVSTS_OFFSET 0x059a
118#define SNB_SLINK_STATUS_OFFSET 0x05a2 118#define XEON_SLINK_STATUS_OFFSET 0x05a2
119#define SNB_B2B_SPAD_OFFSET 0x0100 119#define XEON_B2B_SPAD_OFFSET 0x0100
120#define SNB_B2B_DOORBELL_OFFSET 0x0140 120#define XEON_B2B_DOORBELL_OFFSET 0x0140
121#define SNB_B2B_XLAT_OFFSETL 0x0144 121#define XEON_B2B_XLAT_OFFSETL 0x0144
122#define SNB_B2B_XLAT_OFFSETU 0x0148 122#define XEON_B2B_XLAT_OFFSETU 0x0148
123#define SNB_PPD_CONN_MASK 0x03 123#define XEON_PPD_CONN_MASK 0x03
124#define SNB_PPD_CONN_TRANSPARENT 0x00 124#define XEON_PPD_CONN_TRANSPARENT 0x00
125#define SNB_PPD_CONN_B2B 0x01 125#define XEON_PPD_CONN_B2B 0x01
126#define SNB_PPD_CONN_RP 0x02 126#define XEON_PPD_CONN_RP 0x02
127#define SNB_PPD_DEV_MASK 0x10 127#define XEON_PPD_DEV_MASK 0x10
128#define SNB_PPD_DEV_USD 0x00 128#define XEON_PPD_DEV_USD 0x00
129#define SNB_PPD_DEV_DSD 0x10 129#define XEON_PPD_DEV_DSD 0x10
130#define SNB_PPD_SPLIT_BAR_MASK 0x40 130#define XEON_PPD_SPLIT_BAR_MASK 0x40
131 131
132#define SNB_PPD_TOPO_MASK (SNB_PPD_CONN_MASK | SNB_PPD_DEV_MASK) 132#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
133#define SNB_PPD_TOPO_PRI_USD (SNB_PPD_CONN_RP | SNB_PPD_DEV_USD) 133#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
134#define SNB_PPD_TOPO_PRI_DSD (SNB_PPD_CONN_RP | SNB_PPD_DEV_DSD) 134#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
135#define SNB_PPD_TOPO_SEC_USD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_USD) 135#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
136#define SNB_PPD_TOPO_SEC_DSD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_DSD) 136#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
137#define SNB_PPD_TOPO_B2B_USD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_USD) 137#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
138#define SNB_PPD_TOPO_B2B_DSD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_DSD) 138#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
139 139
140#define SNB_MW_COUNT 2 140#define XEON_MW_COUNT 2
141#define HSX_SPLIT_BAR_MW_COUNT 3 141#define HSX_SPLIT_BAR_MW_COUNT 3
142#define SNB_DB_COUNT 15 142#define XEON_DB_COUNT 15
143#define SNB_DB_LINK 15 143#define XEON_DB_LINK 15
144#define SNB_DB_LINK_BIT BIT_ULL(SNB_DB_LINK) 144#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
145#define SNB_DB_MSIX_VECTOR_COUNT 4 145#define XEON_DB_MSIX_VECTOR_COUNT 4
146#define SNB_DB_MSIX_VECTOR_SHIFT 5 146#define XEON_DB_MSIX_VECTOR_SHIFT 5
147#define SNB_DB_TOTAL_SHIFT 16 147#define XEON_DB_TOTAL_SHIFT 16
148#define SNB_SPAD_COUNT 16 148#define XEON_SPAD_COUNT 16
149 149
150/* BWD hardware */ 150/* Intel Atom hardware */
151 151
152#define BWD_SBAR2XLAT_OFFSET 0x0008 152#define ATOM_SBAR2XLAT_OFFSET 0x0008
153#define BWD_PDOORBELL_OFFSET 0x0020 153#define ATOM_PDOORBELL_OFFSET 0x0020
154#define BWD_PDBMSK_OFFSET 0x0028 154#define ATOM_PDBMSK_OFFSET 0x0028
155#define BWD_NTBCNTL_OFFSET 0x0060 155#define ATOM_NTBCNTL_OFFSET 0x0060
156#define BWD_SPAD_OFFSET 0x0080 156#define ATOM_SPAD_OFFSET 0x0080
157#define BWD_PPD_OFFSET 0x00d4 157#define ATOM_PPD_OFFSET 0x00d4
158#define BWD_PBAR2XLAT_OFFSET 0x8008 158#define ATOM_PBAR2XLAT_OFFSET 0x8008
159#define BWD_B2B_DOORBELL_OFFSET 0x8020 159#define ATOM_B2B_DOORBELL_OFFSET 0x8020
160#define BWD_B2B_SPAD_OFFSET 0x8080 160#define ATOM_B2B_SPAD_OFFSET 0x8080
161#define BWD_SPCICMD_OFFSET 0xb004 161#define ATOM_SPCICMD_OFFSET 0xb004
162#define BWD_LINK_STATUS_OFFSET 0xb052 162#define ATOM_LINK_STATUS_OFFSET 0xb052
163#define BWD_ERRCORSTS_OFFSET 0xb110 163#define ATOM_ERRCORSTS_OFFSET 0xb110
164#define BWD_IP_BASE 0xc000 164#define ATOM_IP_BASE 0xc000
165#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024) 165#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
166#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180) 166#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
167#define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040) 167#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
168#define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324) 168#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
169#define BWD_MODPHY_PCSREG4 0x1c004 169#define ATOM_MODPHY_PCSREG4 0x1c004
170#define BWD_MODPHY_PCSREG6 0x1c006 170#define ATOM_MODPHY_PCSREG6 0x1c006
171 171
172#define BWD_PPD_INIT_LINK 0x0008 172#define ATOM_PPD_INIT_LINK 0x0008
173#define BWD_PPD_CONN_MASK 0x0300 173#define ATOM_PPD_CONN_MASK 0x0300
174#define BWD_PPD_CONN_TRANSPARENT 0x0000 174#define ATOM_PPD_CONN_TRANSPARENT 0x0000
175#define BWD_PPD_CONN_B2B 0x0100 175#define ATOM_PPD_CONN_B2B 0x0100
176#define BWD_PPD_CONN_RP 0x0200 176#define ATOM_PPD_CONN_RP 0x0200
177#define BWD_PPD_DEV_MASK 0x1000 177#define ATOM_PPD_DEV_MASK 0x1000
178#define BWD_PPD_DEV_USD 0x0000 178#define ATOM_PPD_DEV_USD 0x0000
179#define BWD_PPD_DEV_DSD 0x1000 179#define ATOM_PPD_DEV_DSD 0x1000
180#define BWD_PPD_TOPO_MASK (BWD_PPD_CONN_MASK | BWD_PPD_DEV_MASK) 180#define ATOM_PPD_TOPO_MASK (ATOM_PPD_CONN_MASK | ATOM_PPD_DEV_MASK)
181#define BWD_PPD_TOPO_PRI_USD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_USD) 181#define ATOM_PPD_TOPO_PRI_USD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_USD)
182#define BWD_PPD_TOPO_PRI_DSD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_DSD) 182#define ATOM_PPD_TOPO_PRI_DSD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_DSD)
183#define BWD_PPD_TOPO_SEC_USD (BWD_PPD_CONN_RP | BWD_PPD_DEV_USD) 183#define ATOM_PPD_TOPO_SEC_USD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_USD)
184#define BWD_PPD_TOPO_SEC_DSD (BWD_PPD_CONN_RP | BWD_PPD_DEV_DSD) 184#define ATOM_PPD_TOPO_SEC_DSD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_DSD)
185#define BWD_PPD_TOPO_B2B_USD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_USD) 185#define ATOM_PPD_TOPO_B2B_USD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_USD)
186#define BWD_PPD_TOPO_B2B_DSD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_DSD) 186#define ATOM_PPD_TOPO_B2B_DSD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_DSD)
187 187
188#define BWD_MW_COUNT 2 188#define ATOM_MW_COUNT 2
189#define BWD_DB_COUNT 34 189#define ATOM_DB_COUNT 34
190#define BWD_DB_VALID_MASK (BIT_ULL(BWD_DB_COUNT) - 1) 190#define ATOM_DB_VALID_MASK (BIT_ULL(ATOM_DB_COUNT) - 1)
191#define BWD_DB_MSIX_VECTOR_COUNT 34 191#define ATOM_DB_MSIX_VECTOR_COUNT 34
192#define BWD_DB_MSIX_VECTOR_SHIFT 1 192#define ATOM_DB_MSIX_VECTOR_SHIFT 1
193#define BWD_DB_TOTAL_SHIFT 34 193#define ATOM_DB_TOTAL_SHIFT 34
194#define BWD_SPAD_COUNT 16 194#define ATOM_SPAD_COUNT 16
195 195
196#define BWD_NTB_CTL_DOWN_BIT BIT(16) 196#define ATOM_NTB_CTL_DOWN_BIT BIT(16)
197#define BWD_NTB_CTL_ACTIVE(x) !(x & BWD_NTB_CTL_DOWN_BIT) 197#define ATOM_NTB_CTL_ACTIVE(x) !(x & ATOM_NTB_CTL_DOWN_BIT)
198 198
199#define BWD_DESKEWSTS_DBERR BIT(15) 199#define ATOM_DESKEWSTS_DBERR BIT(15)
200#define BWD_LTSSMERRSTS0_UNEXPECTEDEI BIT(20) 200#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI BIT(20)
201#define BWD_LTSSMSTATEJMP_FORCEDETECT BIT(2) 201#define ATOM_LTSSMSTATEJMP_FORCEDETECT BIT(2)
202#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF 202#define ATOM_IBIST_ERR_OFLOW 0x7FFF7FFF
203 203
204#define BWD_LINK_HB_TIMEOUT msecs_to_jiffies(1000) 204#define ATOM_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
205#define BWD_LINK_RECOVERY_TIME msecs_to_jiffies(500) 205#define ATOM_LINK_RECOVERY_TIME msecs_to_jiffies(500)
206 206
207/* Ntb control and link status */ 207/* Ntb control and link status */
208 208
@@ -224,19 +224,19 @@
224 224
225/* Use the following addresses for translation between b2b ntb devices in case 225/* Use the following addresses for translation between b2b ntb devices in case
226 * the hardware default values are not reliable. */ 226 * the hardware default values are not reliable. */
227#define SNB_B2B_BAR0_USD_ADDR 0x1000000000000000ull 227#define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull
228#define SNB_B2B_BAR2_USD_ADDR64 0x2000000000000000ull 228#define XEON_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
229#define SNB_B2B_BAR4_USD_ADDR64 0x4000000000000000ull 229#define XEON_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
230#define SNB_B2B_BAR4_USD_ADDR32 0x20000000u 230#define XEON_B2B_BAR4_USD_ADDR32 0x20000000u
231#define SNB_B2B_BAR5_USD_ADDR32 0x40000000u 231#define XEON_B2B_BAR5_USD_ADDR32 0x40000000u
232#define SNB_B2B_BAR0_DSD_ADDR 0x9000000000000000ull 232#define XEON_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
233#define SNB_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull 233#define XEON_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
234#define SNB_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull 234#define XEON_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
235#define SNB_B2B_BAR4_DSD_ADDR32 0xa0000000u 235#define XEON_B2B_BAR4_DSD_ADDR32 0xa0000000u
236#define SNB_B2B_BAR5_DSD_ADDR32 0xc0000000u 236#define XEON_B2B_BAR5_DSD_ADDR32 0xc0000000u
237 237
238/* The peer ntb secondary config space is 32KB fixed size */ 238/* The peer ntb secondary config space is 32KB fixed size */
239#define SNB_B2B_MIN_SIZE 0x8000 239#define XEON_B2B_MIN_SIZE 0x8000
240 240
241/* flags to indicate hardware errata */ 241/* flags to indicate hardware errata */
242#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0) 242#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-04 12:04:46 -0500