diff options
Diffstat (limited to 'drivers/w1/masters/omap_hdq.c')
-rw-r--r-- | drivers/w1/masters/omap_hdq.c | 30 |
1 files changed, 14 insertions, 16 deletions
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index 291897c881be..4b0fcf3c2d03 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c | |||
@@ -178,6 +178,7 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) | |||
178 | hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); | 178 | hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); |
179 | if (ret == 0) { | 179 | if (ret == 0) { |
180 | dev_dbg(hdq_data->dev, "TX wait elapsed\n"); | 180 | dev_dbg(hdq_data->dev, "TX wait elapsed\n"); |
181 | ret = -ETIMEDOUT; | ||
181 | goto out; | 182 | goto out; |
182 | } | 183 | } |
183 | 184 | ||
@@ -185,7 +186,7 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) | |||
185 | /* check irqstatus */ | 186 | /* check irqstatus */ |
186 | if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) { | 187 | if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) { |
187 | dev_dbg(hdq_data->dev, "timeout waiting for" | 188 | dev_dbg(hdq_data->dev, "timeout waiting for" |
188 | "TXCOMPLETE/RXCOMPLETE, %x", *status); | 189 | " TXCOMPLETE/RXCOMPLETE, %x", *status); |
189 | ret = -ETIMEDOUT; | 190 | ret = -ETIMEDOUT; |
190 | goto out; | 191 | goto out; |
191 | } | 192 | } |
@@ -196,7 +197,7 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) | |||
196 | OMAP_HDQ_FLAG_CLEAR, &tmp_status); | 197 | OMAP_HDQ_FLAG_CLEAR, &tmp_status); |
197 | if (ret) { | 198 | if (ret) { |
198 | dev_dbg(hdq_data->dev, "timeout waiting GO bit" | 199 | dev_dbg(hdq_data->dev, "timeout waiting GO bit" |
199 | "return to zero, %x", tmp_status); | 200 | " return to zero, %x", tmp_status); |
200 | } | 201 | } |
201 | 202 | ||
202 | out: | 203 | out: |
@@ -339,7 +340,7 @@ static int omap_hdq_break(struct hdq_data *hdq_data) | |||
339 | &tmp_status); | 340 | &tmp_status); |
340 | if (ret) | 341 | if (ret) |
341 | dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits" | 342 | dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits" |
342 | "return to zero, %x", tmp_status); | 343 | " return to zero, %x", tmp_status); |
343 | 344 | ||
344 | out: | 345 | out: |
345 | mutex_unlock(&hdq_data->hdq_mutex); | 346 | mutex_unlock(&hdq_data->hdq_mutex); |
@@ -351,7 +352,6 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) | |||
351 | { | 352 | { |
352 | int ret = 0; | 353 | int ret = 0; |
353 | u8 status; | 354 | u8 status; |
354 | unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT; | ||
355 | 355 | ||
356 | ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); | 356 | ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); |
357 | if (ret < 0) { | 357 | if (ret < 0) { |
@@ -369,22 +369,20 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) | |||
369 | OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO, | 369 | OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO, |
370 | OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO); | 370 | OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO); |
371 | /* | 371 | /* |
372 | * The RX comes immediately after TX. It | 372 | * The RX comes immediately after TX. |
373 | * triggers another interrupt before we | ||
374 | * sleep. So we have to wait for RXCOMPLETE bit. | ||
375 | */ | 373 | */ |
376 | while (!(hdq_data->hdq_irqstatus | 374 | wait_event_timeout(hdq_wait_queue, |
377 | & OMAP_HDQ_INT_STATUS_RXCOMPLETE) | 375 | (hdq_data->hdq_irqstatus |
378 | && time_before(jiffies, timeout)) { | 376 | & OMAP_HDQ_INT_STATUS_RXCOMPLETE), |
379 | schedule_timeout_uninterruptible(1); | 377 | OMAP_HDQ_TIMEOUT); |
380 | } | 378 | |
381 | hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0, | 379 | hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0, |
382 | OMAP_HDQ_CTRL_STATUS_DIR); | 380 | OMAP_HDQ_CTRL_STATUS_DIR); |
383 | status = hdq_data->hdq_irqstatus; | 381 | status = hdq_data->hdq_irqstatus; |
384 | /* check irqstatus */ | 382 | /* check irqstatus */ |
385 | if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) { | 383 | if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) { |
386 | dev_dbg(hdq_data->dev, "timeout waiting for" | 384 | dev_dbg(hdq_data->dev, "timeout waiting for" |
387 | "RXCOMPLETE, %x", status); | 385 | " RXCOMPLETE, %x", status); |
388 | ret = -ETIMEDOUT; | 386 | ret = -ETIMEDOUT; |
389 | goto out; | 387 | goto out; |
390 | } | 388 | } |
@@ -394,7 +392,7 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) | |||
394 | out: | 392 | out: |
395 | mutex_unlock(&hdq_data->hdq_mutex); | 393 | mutex_unlock(&hdq_data->hdq_mutex); |
396 | rtn: | 394 | rtn: |
397 | return 0; | 395 | return ret; |
398 | 396 | ||
399 | } | 397 | } |
400 | 398 | ||
@@ -456,7 +454,7 @@ static int omap_hdq_put(struct hdq_data *hdq_data) | |||
456 | 454 | ||
457 | if (0 == hdq_data->hdq_usecount) { | 455 | if (0 == hdq_data->hdq_usecount) { |
458 | dev_dbg(hdq_data->dev, "attempt to decrement use count" | 456 | dev_dbg(hdq_data->dev, "attempt to decrement use count" |
459 | "when it is zero"); | 457 | " when it is zero"); |
460 | ret = -EINVAL; | 458 | ret = -EINVAL; |
461 | } else { | 459 | } else { |
462 | hdq_data->hdq_usecount--; | 460 | hdq_data->hdq_usecount--; |
@@ -524,7 +522,7 @@ static void omap_w1_write_byte(void *_hdq, u8 byte) | |||
524 | mutex_unlock(&hdq_data->hdq_mutex); | 522 | mutex_unlock(&hdq_data->hdq_mutex); |
525 | 523 | ||
526 | ret = hdq_write_byte(hdq_data, byte, &status); | 524 | ret = hdq_write_byte(hdq_data, byte, &status); |
527 | if (ret == 0) { | 525 | if (ret < 0) { |
528 | dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status); | 526 | dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status); |
529 | return; | 527 | return; |
530 | } | 528 | } |