diff options
Diffstat (limited to 'drivers/usb/host/xhci.h')
-rw-r--r-- | drivers/usb/host/xhci.h | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index e4d7d3d06a75..866e141d4972 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h | |||
@@ -718,11 +718,12 @@ struct xhci_ep_ctx { | |||
718 | /* bits 10:14 are Max Primary Streams */ | 718 | /* bits 10:14 are Max Primary Streams */ |
719 | /* bit 15 is Linear Stream Array */ | 719 | /* bit 15 is Linear Stream Array */ |
720 | /* Interval - period between requests to an endpoint - 125u increments. */ | 720 | /* Interval - period between requests to an endpoint - 125u increments. */ |
721 | #define EP_INTERVAL(p) (((p) & 0xff) << 16) | 721 | #define EP_INTERVAL(p) (((p) & 0xff) << 16) |
722 | #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) | 722 | #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) |
723 | #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) | 723 | #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) |
724 | #define EP_MAXPSTREAMS_MASK (0x1f << 10) | 724 | #define EP_MAXPSTREAMS_MASK (0x1f << 10) |
725 | #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) | 725 | #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) |
726 | #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) | ||
726 | /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ | 727 | /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ |
727 | #define EP_HAS_LSA (1 << 15) | 728 | #define EP_HAS_LSA (1 << 15) |
728 | /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ | 729 | /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ |
@@ -1825,6 +1826,7 @@ struct xhci_hcd { | |||
1825 | #define XHCI_U2_DISABLE_WAKE (1 << 27) | 1826 | #define XHCI_U2_DISABLE_WAKE (1 << 27) |
1826 | #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) | 1827 | #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) |
1827 | #define XHCI_HW_LPM_DISABLE (1 << 29) | 1828 | #define XHCI_HW_LPM_DISABLE (1 << 29) |
1829 | #define XHCI_SUSPEND_DELAY (1 << 30) | ||
1828 | 1830 | ||
1829 | unsigned int num_active_eps; | 1831 | unsigned int num_active_eps; |
1830 | unsigned int limit_active_eps; | 1832 | unsigned int limit_active_eps; |
@@ -2549,21 +2551,22 @@ static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq, | |||
2549 | u8 burst; | 2551 | u8 burst; |
2550 | u8 cerr; | 2552 | u8 cerr; |
2551 | u8 mult; | 2553 | u8 mult; |
2552 | u8 lsa; | 2554 | |
2553 | u8 hid; | 2555 | bool lsa; |
2556 | bool hid; | ||
2554 | 2557 | ||
2555 | esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | | 2558 | esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | |
2556 | CTX_TO_MAX_ESIT_PAYLOAD(tx_info); | 2559 | CTX_TO_MAX_ESIT_PAYLOAD(tx_info); |
2557 | 2560 | ||
2558 | ep_state = info & EP_STATE_MASK; | 2561 | ep_state = info & EP_STATE_MASK; |
2559 | max_pstr = info & EP_MAXPSTREAMS_MASK; | 2562 | max_pstr = CTX_TO_EP_MAXPSTREAMS(info); |
2560 | interval = CTX_TO_EP_INTERVAL(info); | 2563 | interval = CTX_TO_EP_INTERVAL(info); |
2561 | mult = CTX_TO_EP_MULT(info) + 1; | 2564 | mult = CTX_TO_EP_MULT(info) + 1; |
2562 | lsa = info & EP_HAS_LSA; | 2565 | lsa = !!(info & EP_HAS_LSA); |
2563 | 2566 | ||
2564 | cerr = (info2 & (3 << 1)) >> 1; | 2567 | cerr = (info2 & (3 << 1)) >> 1; |
2565 | ep_type = CTX_TO_EP_TYPE(info2); | 2568 | ep_type = CTX_TO_EP_TYPE(info2); |
2566 | hid = info2 & (1 << 7); | 2569 | hid = !!(info2 & (1 << 7)); |
2567 | burst = CTX_TO_MAX_BURST(info2); | 2570 | burst = CTX_TO_MAX_BURST(info2); |
2568 | maxp = MAX_PACKET_DECODED(info2); | 2571 | maxp = MAX_PACKET_DECODED(info2); |
2569 | 2572 | ||