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path: root/drivers/usb/dwc2/params.c
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Diffstat (limited to 'drivers/usb/dwc2/params.c')
-rw-r--r--drivers/usb/dwc2/params.c1454
1 files changed, 369 insertions, 1085 deletions
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index bcd1e19b4076..2990c347289f 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -38,1157 +38,499 @@
38 38
39#include "core.h" 39#include "core.h"
40 40
41static const struct dwc2_core_params params_hi6220 = { 41static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
42 .otg_cap = 2, /* No HNP/SRP capable */
43 .otg_ver = 0, /* 1.3 */
44 .dma_desc_enable = 0,
45 .dma_desc_fs_enable = 0,
46 .speed = 0, /* High Speed */
47 .enable_dynamic_fifo = 1,
48 .en_multiple_tx_fifo = 1,
49 .host_rx_fifo_size = 512,
50 .host_nperio_tx_fifo_size = 512,
51 .host_perio_tx_fifo_size = 512,
52 .max_transfer_size = 65535,
53 .max_packet_count = 511,
54 .host_channels = 16,
55 .phy_type = 1, /* UTMI */
56 .phy_utmi_width = 8,
57 .phy_ulpi_ddr = 0, /* Single */
58 .phy_ulpi_ext_vbus = 0,
59 .i2c_enable = 0,
60 .ulpi_fs_ls = 0,
61 .host_support_fs_ls_low_power = 0,
62 .host_ls_low_power_phy_clk = 0, /* 48 MHz */
63 .ts_dline = 0,
64 .reload_ctl = 0,
65 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
66 GAHBCFG_HBSTLEN_SHIFT,
67 .uframe_sched = 0,
68 .external_id_pin_ctl = -1,
69 .hibernation = -1,
70};
71
72static const struct dwc2_core_params params_bcm2835 = {
73 .otg_cap = 0, /* HNP/SRP capable */
74 .otg_ver = 0, /* 1.3 */
75 .dma_desc_enable = 0,
76 .dma_desc_fs_enable = 0,
77 .speed = 0, /* High Speed */
78 .enable_dynamic_fifo = 1,
79 .en_multiple_tx_fifo = 1,
80 .host_rx_fifo_size = 774, /* 774 DWORDs */
81 .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
82 .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
83 .max_transfer_size = 65535,
84 .max_packet_count = 511,
85 .host_channels = 8,
86 .phy_type = 1, /* UTMI */
87 .phy_utmi_width = 8, /* 8 bits */
88 .phy_ulpi_ddr = 0, /* Single */
89 .phy_ulpi_ext_vbus = 0,
90 .i2c_enable = 0,
91 .ulpi_fs_ls = 0,
92 .host_support_fs_ls_low_power = 0,
93 .host_ls_low_power_phy_clk = 0, /* 48 MHz */
94 .ts_dline = 0,
95 .reload_ctl = 0,
96 .ahbcfg = 0x10,
97 .uframe_sched = 0,
98 .external_id_pin_ctl = -1,
99 .hibernation = -1,
100};
101
102static const struct dwc2_core_params params_rk3066 = {
103 .otg_cap = 2, /* non-HNP/non-SRP */
104 .otg_ver = -1,
105 .dma_desc_enable = 0,
106 .dma_desc_fs_enable = 0,
107 .speed = -1,
108 .enable_dynamic_fifo = 1,
109 .en_multiple_tx_fifo = -1,
110 .host_rx_fifo_size = 525, /* 525 DWORDs */
111 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
112 .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
113 .max_transfer_size = -1,
114 .max_packet_count = -1,
115 .host_channels = -1,
116 .phy_type = -1,
117 .phy_utmi_width = -1,
118 .phy_ulpi_ddr = -1,
119 .phy_ulpi_ext_vbus = -1,
120 .i2c_enable = -1,
121 .ulpi_fs_ls = -1,
122 .host_support_fs_ls_low_power = -1,
123 .host_ls_low_power_phy_clk = -1,
124 .ts_dline = -1,
125 .reload_ctl = -1,
126 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
127 GAHBCFG_HBSTLEN_SHIFT,
128 .uframe_sched = -1,
129 .external_id_pin_ctl = -1,
130 .hibernation = -1,
131};
132
133static const struct dwc2_core_params params_ltq = {
134 .otg_cap = 2, /* non-HNP/non-SRP */
135 .otg_ver = -1,
136 .dma_desc_enable = -1,
137 .dma_desc_fs_enable = -1,
138 .speed = -1,
139 .enable_dynamic_fifo = -1,
140 .en_multiple_tx_fifo = -1,
141 .host_rx_fifo_size = 288, /* 288 DWORDs */
142 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
143 .host_perio_tx_fifo_size = 96, /* 96 DWORDs */
144 .max_transfer_size = 65535,
145 .max_packet_count = 511,
146 .host_channels = -1,
147 .phy_type = -1,
148 .phy_utmi_width = -1,
149 .phy_ulpi_ddr = -1,
150 .phy_ulpi_ext_vbus = -1,
151 .i2c_enable = -1,
152 .ulpi_fs_ls = -1,
153 .host_support_fs_ls_low_power = -1,
154 .host_ls_low_power_phy_clk = -1,
155 .ts_dline = -1,
156 .reload_ctl = -1,
157 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
158 GAHBCFG_HBSTLEN_SHIFT,
159 .uframe_sched = -1,
160 .external_id_pin_ctl = -1,
161 .hibernation = -1,
162};
163
164static const struct dwc2_core_params params_amlogic = {
165 .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
166 .otg_ver = -1,
167 .dma_desc_enable = 0,
168 .dma_desc_fs_enable = 0,
169 .speed = DWC2_SPEED_PARAM_HIGH,
170 .enable_dynamic_fifo = 1,
171 .en_multiple_tx_fifo = -1,
172 .host_rx_fifo_size = 512,
173 .host_nperio_tx_fifo_size = 500,
174 .host_perio_tx_fifo_size = 500,
175 .max_transfer_size = -1,
176 .max_packet_count = -1,
177 .host_channels = 16,
178 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
179 .phy_utmi_width = -1,
180 .phy_ulpi_ddr = -1,
181 .phy_ulpi_ext_vbus = -1,
182 .i2c_enable = -1,
183 .ulpi_fs_ls = -1,
184 .host_support_fs_ls_low_power = -1,
185 .host_ls_low_power_phy_clk = -1,
186 .ts_dline = -1,
187 .reload_ctl = 1,
188 .ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
189 GAHBCFG_HBSTLEN_SHIFT,
190 .uframe_sched = 0,
191 .external_id_pin_ctl = -1,
192 .hibernation = -1,
193};
194
195static const struct dwc2_core_params params_default = {
196 .otg_cap = -1,
197 .otg_ver = -1,
198
199 /*
200 * Disable descriptor dma mode by default as the HW can support
201 * it, but does not support it for SPLIT transactions.
202 * Disable it for FS devices as well.
203 */
204 .dma_desc_enable = 0,
205 .dma_desc_fs_enable = 0,
206
207 .speed = -1,
208 .enable_dynamic_fifo = -1,
209 .en_multiple_tx_fifo = -1,
210 .host_rx_fifo_size = -1,
211 .host_nperio_tx_fifo_size = -1,
212 .host_perio_tx_fifo_size = -1,
213 .max_transfer_size = -1,
214 .max_packet_count = -1,
215 .host_channels = -1,
216 .phy_type = -1,
217 .phy_utmi_width = -1,
218 .phy_ulpi_ddr = -1,
219 .phy_ulpi_ext_vbus = -1,
220 .i2c_enable = -1,
221 .ulpi_fs_ls = -1,
222 .host_support_fs_ls_low_power = -1,
223 .host_ls_low_power_phy_clk = -1,
224 .ts_dline = -1,
225 .reload_ctl = -1,
226 .ahbcfg = -1,
227 .uframe_sched = -1,
228 .external_id_pin_ctl = -1,
229 .hibernation = -1,
230};
231
232const struct of_device_id dwc2_of_match_table[] = {
233 { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
234 { .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
235 { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
236 { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
237 { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
238 { .compatible = "snps,dwc2", .data = NULL },
239 { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
240 { .compatible = "amlogic,meson8b-usb", .data = &params_amlogic },
241 { .compatible = "amlogic,meson-gxbb-usb", .data = &params_amlogic },
242 { .compatible = "amcc,dwc-otg", .data = NULL },
243 {},
244};
245MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
246
247static void dwc2_get_device_property(struct dwc2_hsotg *hsotg,
248 char *property, u8 size, u64 *value)
249{ 42{
250 u32 val32; 43 struct dwc2_core_params *p = &hsotg->params;
251
252 switch (size) {
253 case 0:
254 *value = device_property_read_bool(hsotg->dev, property);
255 break;
256 case 1:
257 case 2:
258 case 4:
259 if (device_property_read_u32(hsotg->dev, property, &val32))
260 return;
261
262 *value = val32;
263 break;
264 case 8:
265 if (device_property_read_u64(hsotg->dev, property, value))
266 return;
267 44
268 break; 45 p->host_rx_fifo_size = 774;
269 default: 46 p->max_transfer_size = 65535;
270 /* 47 p->max_packet_count = 511;
271 * The size is checked by the only function that calls 48 p->ahbcfg = 0x10;
272 * this so this should never happen. 49 p->uframe_sched = false;
273 */
274 WARN_ON(1);
275 return;
276 }
277} 50}
278 51
279static void dwc2_set_core_param(void *param, u8 size, u64 value) 52static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
280{ 53{
281 switch (size) { 54 struct dwc2_core_params *p = &hsotg->params;
282 case 0:
283 *((bool *)param) = !!value;
284 break;
285 case 1:
286 *((u8 *)param) = (u8)value;
287 break;
288 case 2:
289 *((u16 *)param) = (u16)value;
290 break;
291 case 4:
292 *((u32 *)param) = (u32)value;
293 break;
294 case 8:
295 *((u64 *)param) = (u64)value;
296 break;
297 default:
298 /*
299 * The size is checked by the only function that calls
300 * this so this should never happen.
301 */
302 WARN_ON(1);
303 return;
304 }
305}
306 55
307/** 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
308 * dwc2_set_param() - Set a core parameter 57 p->speed = DWC2_SPEED_PARAM_HIGH;
309 * 58 p->host_rx_fifo_size = 512;
310 * @hsotg: Programming view of the DWC_otg controller 59 p->host_nperio_tx_fifo_size = 512;
311 * @param: Pointer to the parameter to set 60 p->host_perio_tx_fifo_size = 512;
312 * @lookup: True if the property should be looked up 61 p->max_transfer_size = 65535;
313 * @property: The device property to read 62 p->max_packet_count = 511;
314 * @legacy: The param value to set if @property is not available. This 63 p->host_channels = 16;
315 * will typically be the legacy value set in the static 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
316 * params structure. 65 p->phy_utmi_width = 8;
317 * @def: The default value 66 p->i2c_enable = false;
318 * @min: The minimum value 67 p->reload_ctl = false;
319 * @max: The maximum value 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
320 * @size: The size of the core parameter in bytes, or 0 for bool. 69 GAHBCFG_HBSTLEN_SHIFT;
321 * 70 p->uframe_sched = false;
322 * This function looks up @property and sets the @param to that value. 71 p->change_speed_quirk = true;
323 * If the property doesn't exist it uses the passed-in @value. It will 72}
324 * verify that the value falls between @min and @max. If it doesn't, 73
325 * it will output an error and set the parameter to either @def or, 74static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
326 * failing that, to @min.
327 *
328 * The @size is used to write to @param and to query the device
329 * properties so that this same function can be used with different
330 * types of parameters.
331 */
332static void dwc2_set_param(struct dwc2_hsotg *hsotg, void *param,
333 bool lookup, char *property, u64 legacy,
334 u64 def, u64 min, u64 max, u8 size)
335{ 75{
336 u64 sizemax; 76 struct dwc2_core_params *p = &hsotg->params;
337 u64 value;
338
339 if (WARN_ON(!hsotg || !param || !property))
340 return;
341
342 if (WARN((size > 8) || ((size & (size - 1)) != 0),
343 "Invalid size %d for %s\n", size, property))
344 return;
345
346 dev_vdbg(hsotg->dev, "%s: Setting %s: legacy=%llu, def=%llu, min=%llu, max=%llu, size=%d\n",
347 __func__, property, legacy, def, min, max, size);
348
349 sizemax = (1ULL << (size * 8)) - 1;
350 value = legacy;
351
352 /* Override legacy settings. */
353 if (lookup)
354 dwc2_get_device_property(hsotg, property, size, &value);
355
356 /*
357 * While the value is not valid, try setting it to the default
358 * value, and failing that, set it to the minimum.
359 */
360 while ((value < min) || (value > max)) {
361 /* Print an error unless the value is set to auto. */
362 if (value != sizemax)
363 dev_err(hsotg->dev, "Invalid value %llu for param %s\n",
364 value, property);
365 77
366 /* 78 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
367 * If we are already the default, just set it to the 79 p->host_rx_fifo_size = 525;
368 * minimum. 80 p->host_nperio_tx_fifo_size = 128;
369 */ 81 p->host_perio_tx_fifo_size = 256;
370 if (value == def) { 82 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
371 dev_vdbg(hsotg->dev, "%s: setting value to min=%llu\n", 83 GAHBCFG_HBSTLEN_SHIFT;
372 __func__, min); 84}
373 value = min;
374 break;
375 }
376 85
377 /* Try the default value */ 86static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
378 dev_vdbg(hsotg->dev, "%s: setting value to default=%llu\n", 87{
379 __func__, def); 88 struct dwc2_core_params *p = &hsotg->params;
380 value = def;
381 }
382 89
383 dev_dbg(hsotg->dev, "Setting %s to %llu\n", property, value); 90 p->otg_cap = 2;
384 dwc2_set_core_param(param, size, value); 91 p->host_rx_fifo_size = 288;
92 p->host_nperio_tx_fifo_size = 128;
93 p->host_perio_tx_fifo_size = 96;
94 p->max_transfer_size = 65535;
95 p->max_packet_count = 511;
96 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
97 GAHBCFG_HBSTLEN_SHIFT;
385} 98}
386 99
387/** 100static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
388 * dwc2_set_param_u32() - Set a u32 parameter
389 *
390 * See dwc2_set_param().
391 */
392static void dwc2_set_param_u32(struct dwc2_hsotg *hsotg, u32 *param,
393 bool lookup, char *property, u16 legacy,
394 u16 def, u16 min, u16 max)
395{ 101{
396 dwc2_set_param(hsotg, param, lookup, property, 102 struct dwc2_core_params *p = &hsotg->params;
397 legacy, def, min, max, 4); 103
104 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
105 p->speed = DWC2_SPEED_PARAM_HIGH;
106 p->host_rx_fifo_size = 512;
107 p->host_nperio_tx_fifo_size = 500;
108 p->host_perio_tx_fifo_size = 500;
109 p->host_channels = 16;
110 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
111 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
112 GAHBCFG_HBSTLEN_SHIFT;
113 p->uframe_sched = false;
398} 114}
399 115
400/** 116static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
401 * dwc2_set_param_bool() - Set a bool parameter
402 *
403 * See dwc2_set_param().
404 *
405 * Note: there is no 'legacy' argument here because there is no legacy
406 * source of bool params.
407 */
408static void dwc2_set_param_bool(struct dwc2_hsotg *hsotg, bool *param,
409 bool lookup, char *property,
410 bool def, bool min, bool max)
411{ 117{
412 dwc2_set_param(hsotg, param, lookup, property, 118 struct dwc2_core_params *p = &hsotg->params;
413 def, def, min, max, 0); 119
120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
414} 121}
415 122
416#define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) 123const struct of_device_id dwc2_of_match_table[] = {
124 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
125 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
126 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
127 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
128 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
129 { .compatible = "snps,dwc2" },
130 { .compatible = "samsung,s3c6400-hsotg" },
131 { .compatible = "amlogic,meson8b-usb",
132 .data = dwc2_set_amlogic_params },
133 { .compatible = "amlogic,meson-gxbb-usb",
134 .data = dwc2_set_amlogic_params },
135 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
136 {},
137};
138MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
417 139
418/* Parameter access functions */ 140static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
419static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
420{ 141{
421 int valid = 1; 142 u8 val;
422 143
423 switch (val) { 144 switch (hsotg->hw_params.op_mode) {
424 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 145 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
425 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 146 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
426 valid = 0;
427 break; 147 break;
428 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 148 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
429 switch (hsotg->hw_params.op_mode) { 149 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
430 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 150 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
431 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 151 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
432 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
433 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
434 break;
435 default:
436 valid = 0;
437 break;
438 }
439 break;
440 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
441 /* always valid */
442 break; 152 break;
443 default: 153 default:
444 valid = 0; 154 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
445 break; 155 break;
446 } 156 }
447 157
448 if (!valid) {
449 if (val >= 0)
450 dev_err(hsotg->dev,
451 "%d invalid for otg_cap parameter. Check HW configuration.\n",
452 val);
453 switch (hsotg->hw_params.op_mode) {
454 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
455 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
456 break;
457 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
458 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
459 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
460 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
461 break;
462 default:
463 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
464 break;
465 }
466 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
467 }
468
469 hsotg->params.otg_cap = val; 158 hsotg->params.otg_cap = val;
470} 159}
471 160
472static void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) 161static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
473{ 162{
474 int valid = 1; 163 int val;
164 u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
475 165
476 if (val > 0 && (hsotg->params.host_dma <= 0 || 166 val = DWC2_PHY_TYPE_PARAM_FS;
477 !hsotg->hw_params.dma_desc_enable)) 167 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
478 valid = 0; 168 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
479 if (val < 0) 169 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
480 valid = 0; 170 val = DWC2_PHY_TYPE_PARAM_UTMI;
481 171 else
482 if (!valid) { 172 val = DWC2_PHY_TYPE_PARAM_ULPI;
483 if (val >= 0)
484 dev_err(hsotg->dev,
485 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
486 val);
487 val = (hsotg->params.host_dma > 0 &&
488 hsotg->hw_params.dma_desc_enable);
489 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
490 } 173 }
491 174
492 hsotg->params.dma_desc_enable = val; 175 if (dwc2_is_fs_iot(hsotg))
493} 176 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
494
495static void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
496{
497 int valid = 1;
498
499 if (val > 0 && (hsotg->params.host_dma <= 0 ||
500 !hsotg->hw_params.dma_desc_enable))
501 valid = 0;
502 if (val < 0)
503 valid = 0;
504
505 if (!valid) {
506 if (val >= 0)
507 dev_err(hsotg->dev,
508 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
509 val);
510 val = (hsotg->params.host_dma > 0 &&
511 hsotg->hw_params.dma_desc_enable);
512 }
513 177
514 hsotg->params.dma_desc_fs_enable = val; 178 hsotg->params.phy_type = val;
515 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
516} 179}
517 180
518static void 181static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
519dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
520 int val)
521{ 182{
522 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 183 int val;
523 if (val >= 0) {
524 dev_err(hsotg->dev,
525 "Wrong value for host_support_fs_low_power\n");
526 dev_err(hsotg->dev,
527 "host_support_fs_low_power must be 0 or 1\n");
528 }
529 val = 0;
530 dev_dbg(hsotg->dev,
531 "Setting host_support_fs_low_power to %d\n", val);
532 }
533 184
534 hsotg->params.host_support_fs_ls_low_power = val; 185 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
535} 186 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
536
537static void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
538 int val)
539{
540 int valid = 1;
541 187
542 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) 188 if (dwc2_is_fs_iot(hsotg))
543 valid = 0; 189 val = DWC2_SPEED_PARAM_FULL;
544 if (val < 0)
545 valid = 0;
546 190
547 if (!valid) { 191 if (dwc2_is_hs_iot(hsotg))
548 if (val >= 0) 192 val = DWC2_SPEED_PARAM_HIGH;
549 dev_err(hsotg->dev,
550 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
551 val);
552 val = hsotg->hw_params.enable_dynamic_fifo;
553 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
554 }
555 193
556 hsotg->params.enable_dynamic_fifo = val; 194 hsotg->params.speed = val;
557} 195}
558 196
559static void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) 197static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
560{ 198{
561 int valid = 1; 199 int val;
562 200
563 if (val < 16 || val > hsotg->hw_params.rx_fifo_size) 201 val = (hsotg->hw_params.utmi_phy_data_width ==
564 valid = 0; 202 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
565
566 if (!valid) {
567 if (val >= 0)
568 dev_err(hsotg->dev,
569 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
570 val);
571 val = hsotg->hw_params.rx_fifo_size;
572 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
573 }
574 203
575 hsotg->params.host_rx_fifo_size = val; 204 hsotg->params.phy_utmi_width = val;
576} 205}
577 206
578static void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 207static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
579 int val)
580{ 208{
581 int valid = 1; 209 struct dwc2_core_params *p = &hsotg->params;
582 210 int depth_average;
583 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) 211 int fifo_count;
584 valid = 0; 212 int i;
585 213
586 if (!valid) { 214 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
587 if (val >= 0)
588 dev_err(hsotg->dev,
589 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
590 val);
591 val = hsotg->hw_params.host_nperio_tx_fifo_size;
592 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
593 val);
594 }
595 215
596 hsotg->params.host_nperio_tx_fifo_size = val; 216 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
217 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
218 for (i = 1; i <= fifo_count; i++)
219 p->g_tx_fifo_size[i] = depth_average;
597} 220}
598 221
599static void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 222/**
600 int val) 223 * dwc2_set_default_params() - Set all core parameters to their
224 * auto-detected default values.
225 */
226static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
601{ 227{
602 int valid = 1; 228 struct dwc2_hw_params *hw = &hsotg->hw_params;
229 struct dwc2_core_params *p = &hsotg->params;
230 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
603 231
604 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) 232 dwc2_set_param_otg_cap(hsotg);
605 valid = 0; 233 dwc2_set_param_phy_type(hsotg);
234 dwc2_set_param_speed(hsotg);
235 dwc2_set_param_phy_utmi_width(hsotg);
236 p->phy_ulpi_ddr = false;
237 p->phy_ulpi_ext_vbus = false;
238
239 p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
240 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
241 p->i2c_enable = hw->i2c_enable;
242 p->ulpi_fs_ls = false;
243 p->ts_dline = false;
244 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
245 p->uframe_sched = true;
246 p->external_id_pin_ctl = false;
247 p->hibernation = false;
248 p->max_packet_count = hw->max_packet_count;
249 p->max_transfer_size = hw->max_transfer_size;
250 p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT;
606 251
607 if (!valid) { 252 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
608 if (val >= 0) 253 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
609 dev_err(hsotg->dev, 254 p->host_dma = dma_capable;
610 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", 255 p->dma_desc_enable = false;
611 val); 256 p->dma_desc_fs_enable = false;
612 val = hsotg->hw_params.host_perio_tx_fifo_size; 257 p->host_support_fs_ls_low_power = false;
613 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", 258 p->host_ls_low_power_phy_clk = false;
614 val); 259 p->host_channels = hw->host_channels;
260 p->host_rx_fifo_size = hw->rx_fifo_size;
261 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
262 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
615 } 263 }
616 264
617 hsotg->params.host_perio_tx_fifo_size = val; 265 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
618} 266 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
619 267 p->g_dma = dma_capable;
620static void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) 268 p->g_dma_desc = hw->dma_desc_enable;
621{
622 int valid = 1;
623
624 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
625 valid = 0;
626 269
627 if (!valid) { 270 /*
628 if (val >= 0) 271 * The values for g_rx_fifo_size (2048) and
629 dev_err(hsotg->dev, 272 * g_np_tx_fifo_size (1024) come from the legacy s3c
630 "%d invalid for max_transfer_size. Check HW configuration.\n", 273 * gadget driver. These defaults have been hard-coded
631 val); 274 * for some time so many platforms depend on these
632 val = hsotg->hw_params.max_transfer_size; 275 * values. Leave them as defaults for now and only
633 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); 276 * auto-detect if the hardware does not support the
277 * default.
278 */
279 p->g_rx_fifo_size = 2048;
280 p->g_np_tx_fifo_size = 1024;
281 dwc2_set_param_tx_fifo_sizes(hsotg);
634 } 282 }
635
636 hsotg->params.max_transfer_size = val;
637} 283}
638 284
639static void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) 285/**
286 * dwc2_get_device_properties() - Read in device properties.
287 *
288 * Read in the device properties and adjust core parameters if needed.
289 */
290static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
640{ 291{
641 int valid = 1; 292 struct dwc2_core_params *p = &hsotg->params;
642 293 int num;
643 if (val < 15 || val > hsotg->hw_params.max_packet_count)
644 valid = 0;
645 294
646 if (!valid) { 295 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
647 if (val >= 0) 296 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
648 dev_err(hsotg->dev, 297 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
649 "%d invalid for max_packet_count. Check HW configuration.\n", 298 &p->g_rx_fifo_size);
650 val); 299
651 val = hsotg->hw_params.max_packet_count; 300 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
652 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); 301 &p->g_np_tx_fifo_size);
302
303 num = device_property_read_u32_array(hsotg->dev,
304 "g-tx-fifo-size",
305 NULL, 0);
306
307 if (num > 0) {
308 num = min(num, 15);
309 memset(p->g_tx_fifo_size, 0,
310 sizeof(p->g_tx_fifo_size));
311 device_property_read_u32_array(hsotg->dev,
312 "g-tx-fifo-size",
313 &p->g_tx_fifo_size[1],
314 num);
315 }
653 } 316 }
654
655 hsotg->params.max_packet_count = val;
656} 317}
657 318
658static void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) 319static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
659{ 320{
660 int valid = 1; 321 int valid = 1;
661 322
662 if (val < 1 || val > hsotg->hw_params.host_channels) 323 switch (hsotg->params.otg_cap) {
324 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
325 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
326 valid = 0;
327 break;
328 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
329 switch (hsotg->hw_params.op_mode) {
330 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
331 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
332 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
333 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
334 break;
335 default:
336 valid = 0;
337 break;
338 }
339 break;
340 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
341 /* always valid */
342 break;
343 default:
663 valid = 0; 344 valid = 0;
664 345 break;
665 if (!valid) {
666 if (val >= 0)
667 dev_err(hsotg->dev,
668 "%d invalid for host_channels. Check HW configuration.\n",
669 val);
670 val = hsotg->hw_params.host_channels;
671 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
672 } 346 }
673 347
674 hsotg->params.host_channels = val; 348 if (!valid)
349 dwc2_set_param_otg_cap(hsotg);
675} 350}
676 351
677static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 352static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
678{ 353{
679 int valid = 0; 354 int valid = 0;
680 u32 hs_phy_type, fs_phy_type; 355 u32 hs_phy_type;
681 356 u32 fs_phy_type;
682 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
683 DWC2_PHY_TYPE_PARAM_ULPI)) {
684 if (val >= 0) {
685 dev_err(hsotg->dev, "Wrong value for phy_type\n");
686 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
687 }
688
689 valid = 0;
690 }
691 357
692 hs_phy_type = hsotg->hw_params.hs_phy_type; 358 hs_phy_type = hsotg->hw_params.hs_phy_type;
693 fs_phy_type = hsotg->hw_params.fs_phy_type; 359 fs_phy_type = hsotg->hw_params.fs_phy_type;
694 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
695 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
696 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
697 valid = 1;
698 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
699 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
700 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
701 valid = 1;
702 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
703 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
704 valid = 1;
705
706 if (!valid) {
707 if (val >= 0)
708 dev_err(hsotg->dev,
709 "%d invalid for phy_type. Check HW configuration.\n",
710 val);
711 val = DWC2_PHY_TYPE_PARAM_FS;
712 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
713 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
714 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
715 val = DWC2_PHY_TYPE_PARAM_UTMI;
716 else
717 val = DWC2_PHY_TYPE_PARAM_ULPI;
718 }
719 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
720 }
721
722 hsotg->params.phy_type = val;
723}
724
725static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
726{
727 return hsotg->params.phy_type;
728}
729
730static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
731{
732 int valid = 1;
733
734 if (DWC2_OUT_OF_BOUNDS(val, 0, 2)) {
735 if (val >= 0) {
736 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
737 dev_err(hsotg->dev, "max_speed parameter must be 0, 1, or 2\n");
738 }
739 valid = 0;
740 }
741
742 if (dwc2_is_hs_iot(hsotg) &&
743 val == DWC2_SPEED_PARAM_LOW)
744 valid = 0;
745
746 if (val == DWC2_SPEED_PARAM_HIGH &&
747 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
748 valid = 0;
749 360
750 if (!valid) { 361 switch (hsotg->params.phy_type) {
751 if (val >= 0) 362 case DWC2_PHY_TYPE_PARAM_FS:
752 dev_err(hsotg->dev, 363 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
753 "%d invalid for speed parameter. Check HW configuration.\n", 364 valid = 1;
754 val); 365 break;
755 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? 366 case DWC2_PHY_TYPE_PARAM_UTMI:
756 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 367 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
757 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); 368 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
369 valid = 1;
370 break;
371 case DWC2_PHY_TYPE_PARAM_ULPI:
372 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
373 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
374 valid = 1;
375 break;
376 default:
377 break;
758 } 378 }
759 379
760 hsotg->params.speed = val; 380 if (!valid)
381 dwc2_set_param_phy_type(hsotg);
761} 382}
762 383
763static void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 384static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
764 int val)
765{ 385{
766 int valid = 1; 386 int valid = 1;
387 int phy_type = hsotg->params.phy_type;
388 int speed = hsotg->params.speed;
767 389
768 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, 390 switch (speed) {
769 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { 391 case DWC2_SPEED_PARAM_HIGH:
770 if (val >= 0) { 392 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
771 dev_err(hsotg->dev, 393 (phy_type == DWC2_PHY_TYPE_PARAM_FS))
772 "Wrong value for host_ls_low_power_phy_clk parameter\n"); 394 valid = 0;
773 dev_err(hsotg->dev, 395 break;
774 "host_ls_low_power_phy_clk must be 0 or 1\n"); 396 case DWC2_SPEED_PARAM_FULL:
775 } 397 case DWC2_SPEED_PARAM_LOW:
776 valid = 0; 398 break;
777 } 399 default:
778
779 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
780 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
781 valid = 0; 400 valid = 0;
782 401 break;
783 if (!valid) {
784 if (val >= 0)
785 dev_err(hsotg->dev,
786 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
787 val);
788 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
789 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
790 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
791 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
792 val);
793 }
794
795 hsotg->params.host_ls_low_power_phy_clk = val;
796}
797
798static void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
799{
800 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
801 if (val >= 0) {
802 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
803 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
804 }
805 val = 0;
806 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
807 }
808
809 hsotg->params.phy_ulpi_ddr = val;
810}
811
812static void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
813{
814 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
815 if (val >= 0) {
816 dev_err(hsotg->dev,
817 "Wrong value for phy_ulpi_ext_vbus\n");
818 dev_err(hsotg->dev,
819 "phy_ulpi_ext_vbus must be 0 or 1\n");
820 }
821 val = 0;
822 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
823 } 402 }
824 403
825 hsotg->params.phy_ulpi_ext_vbus = val; 404 if (!valid)
405 dwc2_set_param_speed(hsotg);
826} 406}
827 407
828static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) 408static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
829{ 409{
830 int valid = 0; 410 int valid = 0;
411 int param = hsotg->params.phy_utmi_width;
412 int width = hsotg->hw_params.utmi_phy_data_width;
831 413
832 switch (hsotg->hw_params.utmi_phy_data_width) { 414 switch (width) {
833 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 415 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
834 valid = (val == 8); 416 valid = (param == 8);
835 break; 417 break;
836 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 418 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
837 valid = (val == 16); 419 valid = (param == 16);
838 break; 420 break;
839 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 421 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
840 valid = (val == 8 || val == 16); 422 valid = (param == 8 || param == 16);
841 break; 423 break;
842 } 424 }
843 425
844 if (!valid) { 426 if (!valid)
845 if (val >= 0) { 427 dwc2_set_param_phy_utmi_width(hsotg);
846 dev_err(hsotg->dev,
847 "%d invalid for phy_utmi_width. Check HW configuration.\n",
848 val);
849 }
850 val = (hsotg->hw_params.utmi_phy_data_width ==
851 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
852 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
853 }
854
855 hsotg->params.phy_utmi_width = val;
856}
857
858static void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
859{
860 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
861 if (val >= 0) {
862 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
863 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
864 }
865 val = 0;
866 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
867 }
868
869 hsotg->params.ulpi_fs_ls = val;
870}
871
872static void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
873{
874 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
875 if (val >= 0) {
876 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
877 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
878 }
879 val = 0;
880 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
881 }
882
883 hsotg->params.ts_dline = val;
884}
885
886static void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
887{
888 int valid = 1;
889
890 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
891 if (val >= 0) {
892 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
893 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
894 }
895
896 valid = 0;
897 }
898
899 if (val == 1 && !(hsotg->hw_params.i2c_enable))
900 valid = 0;
901
902 if (!valid) {
903 if (val >= 0)
904 dev_err(hsotg->dev,
905 "%d invalid for i2c_enable. Check HW configuration.\n",
906 val);
907 val = hsotg->hw_params.i2c_enable;
908 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
909 }
910
911 hsotg->params.i2c_enable = val;
912}
913
914static void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
915 int val)
916{
917 int valid = 1;
918
919 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
920 if (val >= 0) {
921 dev_err(hsotg->dev,
922 "Wrong value for en_multiple_tx_fifo,\n");
923 dev_err(hsotg->dev,
924 "en_multiple_tx_fifo must be 0 or 1\n");
925 }
926 valid = 0;
927 }
928
929 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
930 valid = 0;
931
932 if (!valid) {
933 if (val >= 0)
934 dev_err(hsotg->dev,
935 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
936 val);
937 val = hsotg->hw_params.en_multiple_tx_fifo;
938 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
939 }
940
941 hsotg->params.en_multiple_tx_fifo = val;
942} 428}
943 429
944static void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) 430static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
945{ 431{
946 int valid = 1; 432 int fifo_count;
947 433 int fifo;
948 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 434 int min;
949 if (val >= 0) { 435 u32 total = 0;
950 dev_err(hsotg->dev, 436 u32 dptxfszn;
951 "'%d' invalid for parameter reload_ctl\n", val);
952 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
953 }
954 valid = 0;
955 }
956
957 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
958 valid = 0;
959
960 if (!valid) {
961 if (val >= 0)
962 dev_err(hsotg->dev,
963 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
964 val);
965 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
966 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
967 }
968 437
969 hsotg->params.reload_ctl = val; 438 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
970} 439 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
971 440
972static void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 441 for (fifo = 1; fifo <= fifo_count; fifo++)
973{ 442 total += hsotg->params.g_tx_fifo_size[fifo];
974 if (val != -1)
975 hsotg->params.ahbcfg = val;
976 else
977 hsotg->params.ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
978 GAHBCFG_HBSTLEN_SHIFT;
979}
980 443
981static void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 444 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
982{ 445 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
983 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 446 __func__);
984 if (val >= 0) { 447 dwc2_set_param_tx_fifo_sizes(hsotg);
985 dev_err(hsotg->dev,
986 "'%d' invalid for parameter otg_ver\n", val);
987 dev_err(hsotg->dev,
988 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
989 }
990 val = 0;
991 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
992 } 448 }
993 449
994 hsotg->params.otg_ver = val; 450 for (fifo = 1; fifo <= fifo_count; fifo++) {
995} 451 dptxfszn = (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) &
452 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
996 453
997static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) 454 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
998{ 455 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) {
999 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 456 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
1000 if (val >= 0) { 457 __func__, fifo,
1001 dev_err(hsotg->dev, 458 hsotg->params.g_tx_fifo_size[fifo]);
1002 "'%d' invalid for parameter uframe_sched\n", 459 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
1003 val);
1004 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
1005 } 460 }
1006 val = 1;
1007 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
1008 } 461 }
1009
1010 hsotg->params.uframe_sched = val;
1011} 462}
1012 463
1013static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, 464#define CHECK_RANGE(_param, _min, _max, _def) do { \
1014 int val) 465 if ((hsotg->params._param) < (_min) || \
1015{ 466 (hsotg->params._param) > (_max)) { \
1016 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 467 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
1017 if (val >= 0) { 468 __func__, #_param, hsotg->params._param); \
1018 dev_err(hsotg->dev, 469 hsotg->params._param = (_def); \
1019 "'%d' invalid for parameter external_id_pin_ctl\n", 470 } \
1020 val); 471 } while (0)
1021 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
1022 }
1023 val = 0;
1024 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
1025 }
1026 472
1027 hsotg->params.external_id_pin_ctl = val; 473#define CHECK_BOOL(_param, _check) do { \
1028} 474 if (hsotg->params._param && !(_check)) { \
475 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
476 __func__, #_param, hsotg->params._param); \
477 hsotg->params._param = false; \
478 } \
479 } while (0)
1029 480
1030static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg, 481static void dwc2_check_params(struct dwc2_hsotg *hsotg)
1031 int val)
1032{
1033 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1034 if (val >= 0) {
1035 dev_err(hsotg->dev,
1036 "'%d' invalid for parameter hibernation\n",
1037 val);
1038 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
1039 }
1040 val = 0;
1041 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
1042 }
1043
1044 hsotg->params.hibernation = val;
1045}
1046
1047static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
1048{
1049 int i;
1050 int num;
1051 char *property = "g-tx-fifo-size";
1052 struct dwc2_core_params *p = &hsotg->params;
1053
1054 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
1055
1056 /* Read tx fifo sizes */
1057 num = device_property_read_u32_array(hsotg->dev, property, NULL, 0);
1058
1059 if (num > 0) {
1060 device_property_read_u32_array(hsotg->dev, property,
1061 &p->g_tx_fifo_size[1],
1062 num);
1063 } else {
1064 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
1065
1066 memcpy(&p->g_tx_fifo_size[1],
1067 p_tx_fifo,
1068 sizeof(p_tx_fifo));
1069
1070 num = ARRAY_SIZE(p_tx_fifo);
1071 }
1072
1073 for (i = 0; i < num; i++) {
1074 if ((i + 1) >= ARRAY_SIZE(p->g_tx_fifo_size))
1075 break;
1076
1077 dev_dbg(hsotg->dev, "Setting %s[%d] to %d\n",
1078 property, i + 1, p->g_tx_fifo_size[i + 1]);
1079 }
1080}
1081
1082static void dwc2_set_gadget_dma(struct dwc2_hsotg *hsotg)
1083{ 482{
1084 struct dwc2_hw_params *hw = &hsotg->hw_params; 483 struct dwc2_hw_params *hw = &hsotg->hw_params;
1085 struct dwc2_core_params *p = &hsotg->params; 484 struct dwc2_core_params *p = &hsotg->params;
1086 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 485 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
1087 486
1088 /* Buffer DMA */ 487 dwc2_check_param_otg_cap(hsotg);
1089 dwc2_set_param_bool(hsotg, &p->g_dma, 488 dwc2_check_param_phy_type(hsotg);
1090 false, "gadget-dma", 489 dwc2_check_param_speed(hsotg);
1091 dma_capable, false, 490 dwc2_check_param_phy_utmi_width(hsotg);
1092 dma_capable); 491 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
1093 492 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
1094 /* DMA Descriptor */ 493 CHECK_BOOL(i2c_enable, hw->i2c_enable);
1095 dwc2_set_param_bool(hsotg, &p->g_dma_desc, false, 494 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
1096 "gadget-dma-desc", 495 CHECK_RANGE(max_packet_count,
1097 !!hw->dma_desc_enable, false, 496 15, hw->max_packet_count,
1098 !!hw->dma_desc_enable); 497 hw->max_packet_count);
1099} 498 CHECK_RANGE(max_transfer_size,
499 2047, hw->max_transfer_size,
500 hw->max_transfer_size);
1100 501
1101/**
1102 * dwc2_set_parameters() - Set all core parameters.
1103 *
1104 * @hsotg: Programming view of the DWC_otg controller
1105 * @params: The parameters to set
1106 */
1107static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1108 const struct dwc2_core_params *params)
1109{
1110 struct dwc2_hw_params *hw = &hsotg->hw_params;
1111 struct dwc2_core_params *p = &hsotg->params;
1112 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
1113
1114 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
1115 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 502 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
1116 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 503 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
1117 dev_dbg(hsotg->dev, "Setting HOST parameters\n"); 504 CHECK_BOOL(host_dma, dma_capable);
1118 505 CHECK_BOOL(dma_desc_enable, p->host_dma);
1119 dwc2_set_param_bool(hsotg, &p->host_dma, 506 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
1120 false, "host-dma", 507 CHECK_BOOL(host_ls_low_power_phy_clk,
1121 dma_capable, false, 508 p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
1122 dma_capable); 509 CHECK_RANGE(host_channels,
1123 dwc2_set_param_host_rx_fifo_size(hsotg, 510 1, hw->host_channels,
1124 params->host_rx_fifo_size); 511 hw->host_channels);
1125 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, 512 CHECK_RANGE(host_rx_fifo_size,
1126 params->host_nperio_tx_fifo_size); 513 16, hw->rx_fifo_size,
1127 dwc2_set_param_host_perio_tx_fifo_size(hsotg, 514 hw->rx_fifo_size);
1128 params->host_perio_tx_fifo_size); 515 CHECK_RANGE(host_nperio_tx_fifo_size,
516 16, hw->host_nperio_tx_fifo_size,
517 hw->host_nperio_tx_fifo_size);
518 CHECK_RANGE(host_perio_tx_fifo_size,
519 16, hw->host_perio_tx_fifo_size,
520 hw->host_perio_tx_fifo_size);
1129 } 521 }
1130 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
1131 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
1132
1133 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
1134 params->host_support_fs_ls_low_power);
1135 dwc2_set_param_enable_dynamic_fifo(hsotg,
1136 params->enable_dynamic_fifo);
1137 dwc2_set_param_max_transfer_size(hsotg,
1138 params->max_transfer_size);
1139 dwc2_set_param_max_packet_count(hsotg,
1140 params->max_packet_count);
1141 dwc2_set_param_host_channels(hsotg, params->host_channels);
1142 dwc2_set_param_phy_type(hsotg, params->phy_type);
1143 dwc2_set_param_speed(hsotg, params->speed);
1144 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
1145 params->host_ls_low_power_phy_clk);
1146 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
1147 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
1148 params->phy_ulpi_ext_vbus);
1149 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
1150 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
1151 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
1152 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
1153 dwc2_set_param_en_multiple_tx_fifo(hsotg,
1154 params->en_multiple_tx_fifo);
1155 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
1156 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
1157 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
1158 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
1159 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
1160 dwc2_set_param_hibernation(hsotg, params->hibernation);
1161 522
1162 /*
1163 * Set devicetree-only parameters. These parameters do not
1164 * take any values from @params.
1165 */
1166 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 523 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
1167 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 524 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
1168 dev_dbg(hsotg->dev, "Setting peripheral device properties\n"); 525 CHECK_BOOL(g_dma, dma_capable);
1169 526 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
1170 dwc2_set_gadget_dma(hsotg); 527 CHECK_RANGE(g_rx_fifo_size,
1171 528 16, hw->rx_fifo_size,
1172 /* 529 hw->rx_fifo_size);
1173 * The values for g_rx_fifo_size (2048) and 530 CHECK_RANGE(g_np_tx_fifo_size,
1174 * g_np_tx_fifo_size (1024) come from the legacy s3c 531 16, hw->dev_nperio_tx_fifo_size,
1175 * gadget driver. These defaults have been hard-coded 532 hw->dev_nperio_tx_fifo_size);
1176 * for some time so many platforms depend on these 533 dwc2_check_param_tx_fifo_sizes(hsotg);
1177 * values. Leave them as defaults for now and only
1178 * auto-detect if the hardware does not support the
1179 * default.
1180 */
1181 dwc2_set_param_u32(hsotg, &p->g_rx_fifo_size,
1182 true, "g-rx-fifo-size", 2048,
1183 hw->rx_fifo_size,
1184 16, hw->rx_fifo_size);
1185
1186 dwc2_set_param_u32(hsotg, &p->g_np_tx_fifo_size,
1187 true, "g-np-tx-fifo-size", 1024,
1188 hw->dev_nperio_tx_fifo_size,
1189 16, hw->dev_nperio_tx_fifo_size);
1190
1191 dwc2_set_param_tx_fifo_sizes(hsotg);
1192 } 534 }
1193} 535}
1194 536
@@ -1211,8 +553,6 @@ static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
1211 553
1212 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 554 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1213 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 555 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
1214 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1215 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
1216 556
1217 if (forced) 557 if (forced)
1218 dwc2_clear_force_mode(hsotg); 558 dwc2_clear_force_mode(hsotg);
@@ -1240,7 +580,6 @@ static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
1240 forced = dwc2_force_mode_if_needed(hsotg, false); 580 forced = dwc2_force_mode_if_needed(hsotg, false);
1241 581
1242 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 582 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1243 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1244 583
1245 if (forced) 584 if (forced)
1246 dwc2_clear_force_mode(hsotg); 585 dwc2_clear_force_mode(hsotg);
@@ -1286,12 +625,6 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
1286 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 625 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
1287 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 626 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
1288 627
1289 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
1290 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
1291 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
1292 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
1293 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
1294
1295 /* 628 /*
1296 * Host specific hardware parameters. Reading these parameters 629 * Host specific hardware parameters. Reading these parameters
1297 * requires the controller to be in host mode. The mode will 630 * requires the controller to be in host mode. The mode will
@@ -1351,73 +684,24 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
1351 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 684 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1352 GRXFSIZ_DEPTH_SHIFT; 685 GRXFSIZ_DEPTH_SHIFT;
1353 686
1354 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
1355 dev_dbg(hsotg->dev, " op_mode=%d\n",
1356 hw->op_mode);
1357 dev_dbg(hsotg->dev, " arch=%d\n",
1358 hw->arch);
1359 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
1360 hw->dma_desc_enable);
1361 dev_dbg(hsotg->dev, " power_optimized=%d\n",
1362 hw->power_optimized);
1363 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
1364 hw->i2c_enable);
1365 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
1366 hw->hs_phy_type);
1367 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
1368 hw->fs_phy_type);
1369 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
1370 hw->utmi_phy_data_width);
1371 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
1372 hw->num_dev_ep);
1373 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
1374 hw->num_dev_perio_in_ep);
1375 dev_dbg(hsotg->dev, " host_channels=%d\n",
1376 hw->host_channels);
1377 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
1378 hw->max_transfer_size);
1379 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
1380 hw->max_packet_count);
1381 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
1382 hw->nperio_tx_q_depth);
1383 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
1384 hw->host_perio_tx_q_depth);
1385 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
1386 hw->dev_token_q_depth);
1387 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
1388 hw->enable_dynamic_fifo);
1389 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
1390 hw->en_multiple_tx_fifo);
1391 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
1392 hw->total_fifo_size);
1393 dev_dbg(hsotg->dev, " rx_fifo_size=%d\n",
1394 hw->rx_fifo_size);
1395 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
1396 hw->host_nperio_tx_fifo_size);
1397 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
1398 hw->host_perio_tx_fifo_size);
1399 dev_dbg(hsotg->dev, "\n");
1400
1401 return 0; 687 return 0;
1402} 688}
1403 689
1404int dwc2_init_params(struct dwc2_hsotg *hsotg) 690int dwc2_init_params(struct dwc2_hsotg *hsotg)
1405{ 691{
1406 const struct of_device_id *match; 692 const struct of_device_id *match;
1407 struct dwc2_core_params params; 693 void (*set_params)(void *data);
694
695 dwc2_set_default_params(hsotg);
696 dwc2_get_device_properties(hsotg);
1408 697
1409 match = of_match_device(dwc2_of_match_table, hsotg->dev); 698 match = of_match_device(dwc2_of_match_table, hsotg->dev);
1410 if (match && match->data) 699 if (match && match->data) {
1411 params = *((struct dwc2_core_params *)match->data); 700 set_params = match->data;
1412 else 701 set_params(hsotg);
1413 params = params_default;
1414
1415 if (dwc2_is_fs_iot(hsotg)) {
1416 params.speed = DWC2_SPEED_PARAM_FULL;
1417 params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
1418 } 702 }
1419 703
1420 dwc2_set_parameters(hsotg, &params); 704 dwc2_check_params(hsotg);
1421 705
1422 return 0; 706 return 0;
1423} 707}
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 17:53:39 -0400