1 files changed, 201 insertions, 10 deletions

diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 476b768c633e..c1d81dcd7819 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
         .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
         .tmu_inten = EXYNOS_TMU_REG_INTEN,
-        .inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+        .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 };
 
 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
@@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
         .tmu_inten = EXYNOS_TMU_REG_INTEN,
-        .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
-        .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
-        .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
-        .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
@@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+        .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
+        .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+        .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+        .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
         .emul_con = EXYNOS_EMUL_CON,
         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -194,6 +194,197 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5260)
+static const struct exynos_tmu_registers exynos5260_tmu_registers = {
+        .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+        .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+        .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+        .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+        .tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
+        .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+        .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+        .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+        .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+        .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+        .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+        .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+        .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+        .tmu_status = EXYNOS_TMU_REG_STATUS,
+        .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+        .threshold_th0 = EXYNOS_THD_TEMP_RISE,
+        .threshold_th1 = EXYNOS_THD_TEMP_FALL,
+        .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
+        .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+        .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+        .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+        .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+        .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+        .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
+        .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
+        .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
+        .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+        .intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
+        .intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
+        .emul_con = EXYNOS5260_EMUL_CON,
+        .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+        .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+        .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5260_TMU_DATA   \
+        .threshold_falling = 10, \
+        .trigger_levels[0] = 85, \
+        .trigger_levels[1] = 103, \
+        .trigger_levels[2] = 110, \
+        .trigger_levels[3] = 120, \
+        .trigger_enable[0] = true, \
+        .trigger_enable[1] = true, \
+        .trigger_enable[2] = true, \
+        .trigger_enable[3] = false, \
+        .trigger_type[0] = THROTTLE_ACTIVE, \
+        .trigger_type[1] = THROTTLE_ACTIVE, \
+        .trigger_type[2] = SW_TRIP, \
+        .trigger_type[3] = HW_TRIP, \
+        .max_trigger_level = 4, \
+        .gain = 8, \
+        .reference_voltage = 16, \
+        .noise_cancel_mode = 4, \
+        .cal_type = TYPE_ONE_POINT_TRIMMING, \
+        .efuse_value = 55, \
+        .min_efuse_value = 40, \
+        .max_efuse_value = 100, \
+        .first_point_trim = 25, \
+        .second_point_trim = 85, \
+        .default_temp_offset = 50, \
+        .freq_tab[0] = { \
+                .freq_clip_max = 800 * 1000, \
+                .temp_level = 85, \
+        }, \
+        .freq_tab[1] = { \
+                .freq_clip_max = 200 * 1000, \
+                .temp_level = 103, \
+        }, \
+        .freq_tab_count = 2, \
+        .registers = &exynos5260_tmu_registers, \
+
+#define EXYNOS5260_TMU_DATA \
+        __EXYNOS5260_TMU_DATA \
+        .type = SOC_ARCH_EXYNOS5260, \
+        .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+                        TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+                        TMU_SUPPORT_EMUL_TIME)
+
+struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
+        .tmu_data = {
+                { EXYNOS5260_TMU_DATA },
+                { EXYNOS5260_TMU_DATA },
+                { EXYNOS5260_TMU_DATA },
+                { EXYNOS5260_TMU_DATA },
+                { EXYNOS5260_TMU_DATA },
+        },
+        .tmu_count = 5,
+};
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+        .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+        .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+        .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+        .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+        .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+        .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+        .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+        .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+        .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+        .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+        .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+        .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+        .tmu_status = EXYNOS_TMU_REG_STATUS,
+        .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+        .threshold_th0 = EXYNOS_THD_TEMP_RISE,
+        .threshold_th1 = EXYNOS_THD_TEMP_FALL,
+        .tmu_inten = EXYNOS_TMU_REG_INTEN,
+        .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+        .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+        .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+        /* INTEN_RISE3 Not availble in exynos5420 */
+        .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+        .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+        .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+        .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+        .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
+        .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+        .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+        .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+        .emul_con = EXYNOS_EMUL_CON,
+        .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+        .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+        .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA   \
+        .threshold_falling = 10, \
+        .trigger_levels[0] = 85, \
+        .trigger_levels[1] = 103, \
+        .trigger_levels[2] = 110, \
+        .trigger_levels[3] = 120, \
+        .trigger_enable[0] = true, \
+        .trigger_enable[1] = true, \
+        .trigger_enable[2] = true, \
+        .trigger_enable[3] = false, \
+        .trigger_type[0] = THROTTLE_ACTIVE, \
+        .trigger_type[1] = THROTTLE_ACTIVE, \
+        .trigger_type[2] = SW_TRIP, \
+        .trigger_type[3] = HW_TRIP, \
+        .max_trigger_level = 4, \
+        .gain = 8, \
+        .reference_voltage = 16, \
+        .noise_cancel_mode = 4, \
+        .cal_type = TYPE_ONE_POINT_TRIMMING, \
+        .efuse_value = 55, \
+        .min_efuse_value = 40, \
+        .max_efuse_value = 100, \
+        .first_point_trim = 25, \
+        .second_point_trim = 85, \
+        .default_temp_offset = 50, \
+        .freq_tab[0] = { \
+                .freq_clip_max = 800 * 1000, \
+                .temp_level = 85, \
+        }, \
+        .freq_tab[1] = { \
+                .freq_clip_max = 200 * 1000, \
+                .temp_level = 103, \
+        }, \
+        .freq_tab_count = 2, \
+        .registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+        __EXYNOS5420_TMU_DATA \
+        .type = SOC_ARCH_EXYNOS5250, \
+        .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+                        TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+                        TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+        __EXYNOS5420_TMU_DATA \
+        .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
+        .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+                        TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+                        TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+        .tmu_data = {
+                { EXYNOS5420_TMU_DATA },
+                { EXYNOS5420_TMU_DATA },
+                { EXYNOS5420_TMU_DATA_SHARED },
+                { EXYNOS5420_TMU_DATA_SHARED },
+                { EXYNOS5420_TMU_DATA_SHARED },
+        },
+        .tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
@@ -217,10 +408,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
-        .inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
-        .inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
-        .inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
-        .inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
@@ -228,6 +415,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+        .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
+        .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
+        .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
+        .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
@@ -255,7 +446,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
         .type = SOC_ARCH_EXYNOS5440, \
         .registers = &exynos5440_tmu_registers, \
         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-                        TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+                        TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
         .tmu_data = {