diff options
Diffstat (limited to 'drivers/spi/spi-fsl-dspi.c')
-rw-r--r-- | drivers/spi/spi-fsl-dspi.c | 307 |
1 files changed, 220 insertions, 87 deletions
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 5fe54cda309f..86bcdd68c1fe 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/module.h> | 24 | #include <linux/module.h> |
25 | #include <linux/of.h> | 25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | 26 | #include <linux/of_device.h> |
27 | #include <linux/pinctrl/consumer.h> | ||
27 | #include <linux/platform_device.h> | 28 | #include <linux/platform_device.h> |
28 | #include <linux/pm_runtime.h> | 29 | #include <linux/pm_runtime.h> |
29 | #include <linux/regmap.h> | 30 | #include <linux/regmap.h> |
@@ -47,6 +48,7 @@ | |||
47 | #define SPI_MCR_CLR_RXF (1 << 10) | 48 | #define SPI_MCR_CLR_RXF (1 << 10) |
48 | 49 | ||
49 | #define SPI_TCR 0x08 | 50 | #define SPI_TCR 0x08 |
51 | #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) | ||
50 | 52 | ||
51 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) | 53 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) |
52 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) | 54 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
@@ -67,9 +69,11 @@ | |||
67 | 69 | ||
68 | #define SPI_SR 0x2c | 70 | #define SPI_SR 0x2c |
69 | #define SPI_SR_EOQF 0x10000000 | 71 | #define SPI_SR_EOQF 0x10000000 |
72 | #define SPI_SR_TCFQF 0x80000000 | ||
70 | 73 | ||
71 | #define SPI_RSER 0x30 | 74 | #define SPI_RSER 0x30 |
72 | #define SPI_RSER_EOQFE 0x10000000 | 75 | #define SPI_RSER_EOQFE 0x10000000 |
76 | #define SPI_RSER_TCFQE 0x80000000 | ||
73 | 77 | ||
74 | #define SPI_PUSHR 0x34 | 78 | #define SPI_PUSHR 0x34 |
75 | #define SPI_PUSHR_CONT (1 << 31) | 79 | #define SPI_PUSHR_CONT (1 << 31) |
@@ -102,12 +106,35 @@ | |||
102 | #define SPI_CS_ASSERT 0x02 | 106 | #define SPI_CS_ASSERT 0x02 |
103 | #define SPI_CS_DROP 0x04 | 107 | #define SPI_CS_DROP 0x04 |
104 | 108 | ||
109 | #define SPI_TCR_TCNT_MAX 0x10000 | ||
110 | |||
105 | struct chip_data { | 111 | struct chip_data { |
106 | u32 mcr_val; | 112 | u32 mcr_val; |
107 | u32 ctar_val; | 113 | u32 ctar_val; |
108 | u16 void_write_data; | 114 | u16 void_write_data; |
109 | }; | 115 | }; |
110 | 116 | ||
117 | enum dspi_trans_mode { | ||
118 | DSPI_EOQ_MODE = 0, | ||
119 | DSPI_TCFQ_MODE, | ||
120 | }; | ||
121 | |||
122 | struct fsl_dspi_devtype_data { | ||
123 | enum dspi_trans_mode trans_mode; | ||
124 | }; | ||
125 | |||
126 | static const struct fsl_dspi_devtype_data vf610_data = { | ||
127 | .trans_mode = DSPI_EOQ_MODE, | ||
128 | }; | ||
129 | |||
130 | static const struct fsl_dspi_devtype_data ls1021a_v1_data = { | ||
131 | .trans_mode = DSPI_TCFQ_MODE, | ||
132 | }; | ||
133 | |||
134 | static const struct fsl_dspi_devtype_data ls2085a_data = { | ||
135 | .trans_mode = DSPI_TCFQ_MODE, | ||
136 | }; | ||
137 | |||
111 | struct fsl_dspi { | 138 | struct fsl_dspi { |
112 | struct spi_master *master; | 139 | struct spi_master *master; |
113 | struct platform_device *pdev; | 140 | struct platform_device *pdev; |
@@ -128,9 +155,12 @@ struct fsl_dspi { | |||
128 | u8 cs; | 155 | u8 cs; |
129 | u16 void_write_data; | 156 | u16 void_write_data; |
130 | u32 cs_change; | 157 | u32 cs_change; |
158 | struct fsl_dspi_devtype_data *devtype_data; | ||
131 | 159 | ||
132 | wait_queue_head_t waitq; | 160 | wait_queue_head_t waitq; |
133 | u32 waitflags; | 161 | u32 waitflags; |
162 | |||
163 | u32 spi_tcnt; | ||
134 | }; | 164 | }; |
135 | 165 | ||
136 | static inline int is_double_byte_mode(struct fsl_dspi *dspi) | 166 | static inline int is_double_byte_mode(struct fsl_dspi *dspi) |
@@ -213,63 +243,60 @@ static void ns_delay_scale(char *psc, char *sc, int delay_ns, | |||
213 | } | 243 | } |
214 | } | 244 | } |
215 | 245 | ||
216 | static int dspi_transfer_write(struct fsl_dspi *dspi) | 246 | static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word) |
217 | { | 247 | { |
218 | int tx_count = 0; | ||
219 | int tx_word; | ||
220 | u16 d16; | 248 | u16 d16; |
221 | u8 d8; | ||
222 | u32 dspi_pushr = 0; | ||
223 | int first = 1; | ||
224 | 249 | ||
225 | tx_word = is_double_byte_mode(dspi); | 250 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) |
251 | d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx; | ||
252 | else | ||
253 | d16 = dspi->void_write_data; | ||
226 | 254 | ||
227 | /* If we are in word mode, but only have a single byte to transfer | 255 | dspi->tx += tx_word + 1; |
228 | * then switch to byte mode temporarily. Will switch back at the | 256 | dspi->len -= tx_word + 1; |
229 | * end of the transfer. | ||
230 | */ | ||
231 | if (tx_word && (dspi->len == 1)) { | ||
232 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; | ||
233 | regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), | ||
234 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); | ||
235 | tx_word = 0; | ||
236 | } | ||
237 | 257 | ||
238 | while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { | 258 | return SPI_PUSHR_TXDATA(d16) | |
239 | if (tx_word) { | 259 | SPI_PUSHR_PCS(dspi->cs) | |
240 | if (dspi->len == 1) | 260 | SPI_PUSHR_CTAS(dspi->cs) | |
241 | break; | 261 | SPI_PUSHR_CONT; |
262 | } | ||
242 | 263 | ||
243 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) { | 264 | static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word) |
244 | d16 = *(u16 *)dspi->tx; | 265 | { |
245 | dspi->tx += 2; | 266 | u16 d; |
246 | } else { | 267 | unsigned int val; |
247 | d16 = dspi->void_write_data; | ||
248 | } | ||
249 | 268 | ||
250 | dspi_pushr = SPI_PUSHR_TXDATA(d16) | | 269 | regmap_read(dspi->regmap, SPI_POPR, &val); |
251 | SPI_PUSHR_PCS(dspi->cs) | | 270 | d = SPI_POPR_RXDATA(val); |
252 | SPI_PUSHR_CTAS(dspi->cs) | | ||
253 | SPI_PUSHR_CONT; | ||
254 | 271 | ||
255 | dspi->len -= 2; | 272 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
256 | } else { | 273 | rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d); |
257 | if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) { | ||
258 | 274 | ||
259 | d8 = *(u8 *)dspi->tx; | 275 | dspi->rx += rx_word + 1; |
260 | dspi->tx++; | 276 | } |
261 | } else { | ||
262 | d8 = (u8)dspi->void_write_data; | ||
263 | } | ||
264 | 277 | ||
265 | dspi_pushr = SPI_PUSHR_TXDATA(d8) | | 278 | static int dspi_eoq_write(struct fsl_dspi *dspi) |
266 | SPI_PUSHR_PCS(dspi->cs) | | 279 | { |
267 | SPI_PUSHR_CTAS(dspi->cs) | | 280 | int tx_count = 0; |
268 | SPI_PUSHR_CONT; | 281 | int tx_word; |
282 | u32 dspi_pushr = 0; | ||
283 | |||
284 | tx_word = is_double_byte_mode(dspi); | ||
269 | 285 | ||
270 | dspi->len--; | 286 | while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { |
287 | /* If we are in word mode, only have a single byte to transfer | ||
288 | * switch to byte mode temporarily. Will switch back at the | ||
289 | * end of the transfer. | ||
290 | */ | ||
291 | if (tx_word && (dspi->len == 1)) { | ||
292 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; | ||
293 | regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), | ||
294 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); | ||
295 | tx_word = 0; | ||
271 | } | 296 | } |
272 | 297 | ||
298 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); | ||
299 | |||
273 | if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { | 300 | if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { |
274 | /* last transfer in the transfer */ | 301 | /* last transfer in the transfer */ |
275 | dspi_pushr |= SPI_PUSHR_EOQ; | 302 | dspi_pushr |= SPI_PUSHR_EOQ; |
@@ -278,11 +305,6 @@ static int dspi_transfer_write(struct fsl_dspi *dspi) | |||
278 | } else if (tx_word && (dspi->len == 1)) | 305 | } else if (tx_word && (dspi->len == 1)) |
279 | dspi_pushr |= SPI_PUSHR_EOQ; | 306 | dspi_pushr |= SPI_PUSHR_EOQ; |
280 | 307 | ||
281 | if (first) { | ||
282 | first = 0; | ||
283 | dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */ | ||
284 | } | ||
285 | |||
286 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); | 308 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); |
287 | 309 | ||
288 | tx_count++; | 310 | tx_count++; |
@@ -291,40 +313,55 @@ static int dspi_transfer_write(struct fsl_dspi *dspi) | |||
291 | return tx_count * (tx_word + 1); | 313 | return tx_count * (tx_word + 1); |
292 | } | 314 | } |
293 | 315 | ||
294 | static int dspi_transfer_read(struct fsl_dspi *dspi) | 316 | static int dspi_eoq_read(struct fsl_dspi *dspi) |
295 | { | 317 | { |
296 | int rx_count = 0; | 318 | int rx_count = 0; |
297 | int rx_word = is_double_byte_mode(dspi); | 319 | int rx_word = is_double_byte_mode(dspi); |
298 | u16 d; | ||
299 | 320 | ||
300 | while ((dspi->rx < dspi->rx_end) | 321 | while ((dspi->rx < dspi->rx_end) |
301 | && (rx_count < DSPI_FIFO_SIZE)) { | 322 | && (rx_count < DSPI_FIFO_SIZE)) { |
302 | if (rx_word) { | 323 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) |
303 | unsigned int val; | 324 | rx_word = 0; |
304 | 325 | ||
305 | if ((dspi->rx_end - dspi->rx) == 1) | 326 | dspi_data_from_popr(dspi, rx_word); |
306 | break; | 327 | rx_count++; |
328 | } | ||
307 | 329 | ||
308 | regmap_read(dspi->regmap, SPI_POPR, &val); | 330 | return rx_count; |
309 | d = SPI_POPR_RXDATA(val); | 331 | } |
310 | 332 | ||
311 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) | 333 | static int dspi_tcfq_write(struct fsl_dspi *dspi) |
312 | *(u16 *)dspi->rx = d; | 334 | { |
313 | dspi->rx += 2; | 335 | int tx_word; |
336 | u32 dspi_pushr = 0; | ||
314 | 337 | ||
315 | } else { | 338 | tx_word = is_double_byte_mode(dspi); |
316 | unsigned int val; | ||
317 | 339 | ||
318 | regmap_read(dspi->regmap, SPI_POPR, &val); | 340 | if (tx_word && (dspi->len == 1)) { |
319 | d = SPI_POPR_RXDATA(val); | 341 | dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; |
320 | if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) | 342 | regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), |
321 | *(u8 *)dspi->rx = d; | 343 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8)); |
322 | dspi->rx++; | 344 | tx_word = 0; |
323 | } | ||
324 | rx_count++; | ||
325 | } | 345 | } |
326 | 346 | ||
327 | return rx_count; | 347 | dspi_pushr = dspi_data_to_pushr(dspi, tx_word); |
348 | |||
349 | if ((dspi->cs_change) && (!dspi->len)) | ||
350 | dspi_pushr &= ~SPI_PUSHR_CONT; | ||
351 | |||
352 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr); | ||
353 | |||
354 | return tx_word + 1; | ||
355 | } | ||
356 | |||
357 | static void dspi_tcfq_read(struct fsl_dspi *dspi) | ||
358 | { | ||
359 | int rx_word = is_double_byte_mode(dspi); | ||
360 | |||
361 | if (rx_word && (dspi->rx_end - dspi->rx) == 1) | ||
362 | rx_word = 0; | ||
363 | |||
364 | dspi_data_from_popr(dspi, rx_word); | ||
328 | } | 365 | } |
329 | 366 | ||
330 | static int dspi_transfer_one_message(struct spi_master *master, | 367 | static int dspi_transfer_one_message(struct spi_master *master, |
@@ -334,6 +371,12 @@ static int dspi_transfer_one_message(struct spi_master *master, | |||
334 | struct spi_device *spi = message->spi; | 371 | struct spi_device *spi = message->spi; |
335 | struct spi_transfer *transfer; | 372 | struct spi_transfer *transfer; |
336 | int status = 0; | 373 | int status = 0; |
374 | enum dspi_trans_mode trans_mode; | ||
375 | u32 spi_tcr; | ||
376 | |||
377 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); | ||
378 | dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | ||
379 | |||
337 | message->actual_length = 0; | 380 | message->actual_length = 0; |
338 | 381 | ||
339 | list_for_each_entry(transfer, &message->transfers, transfer_list) { | 382 | list_for_each_entry(transfer, &message->transfers, transfer_list) { |
@@ -341,10 +384,10 @@ static int dspi_transfer_one_message(struct spi_master *master, | |||
341 | dspi->cur_msg = message; | 384 | dspi->cur_msg = message; |
342 | dspi->cur_chip = spi_get_ctldata(spi); | 385 | dspi->cur_chip = spi_get_ctldata(spi); |
343 | dspi->cs = spi->chip_select; | 386 | dspi->cs = spi->chip_select; |
387 | dspi->cs_change = 0; | ||
344 | if (dspi->cur_transfer->transfer_list.next | 388 | if (dspi->cur_transfer->transfer_list.next |
345 | == &dspi->cur_msg->transfers) | 389 | == &dspi->cur_msg->transfers) |
346 | transfer->cs_change = 1; | 390 | dspi->cs_change = 1; |
347 | dspi->cs_change = transfer->cs_change; | ||
348 | dspi->void_write_data = dspi->cur_chip->void_write_data; | 391 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
349 | 392 | ||
350 | dspi->dataflags = 0; | 393 | dspi->dataflags = 0; |
@@ -370,8 +413,22 @@ static int dspi_transfer_one_message(struct spi_master *master, | |||
370 | regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), | 413 | regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), |
371 | dspi->cur_chip->ctar_val); | 414 | dspi->cur_chip->ctar_val); |
372 | 415 | ||
373 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); | 416 | trans_mode = dspi->devtype_data->trans_mode; |
374 | message->actual_length += dspi_transfer_write(dspi); | 417 | switch (trans_mode) { |
418 | case DSPI_EOQ_MODE: | ||
419 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); | ||
420 | dspi_eoq_write(dspi); | ||
421 | break; | ||
422 | case DSPI_TCFQ_MODE: | ||
423 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); | ||
424 | dspi_tcfq_write(dspi); | ||
425 | break; | ||
426 | default: | ||
427 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | ||
428 | trans_mode); | ||
429 | status = -EINVAL; | ||
430 | goto out; | ||
431 | } | ||
375 | 432 | ||
376 | if (wait_event_interruptible(dspi->waitq, dspi->waitflags)) | 433 | if (wait_event_interruptible(dspi->waitq, dspi->waitflags)) |
377 | dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); | 434 | dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); |
@@ -381,6 +438,7 @@ static int dspi_transfer_one_message(struct spi_master *master, | |||
381 | udelay(transfer->delay_usecs); | 438 | udelay(transfer->delay_usecs); |
382 | } | 439 | } |
383 | 440 | ||
441 | out: | ||
384 | message->status = status; | 442 | message->status = status; |
385 | spi_finalize_current_message(master); | 443 | spi_finalize_current_message(master); |
386 | 444 | ||
@@ -460,27 +518,89 @@ static void dspi_cleanup(struct spi_device *spi) | |||
460 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) | 518 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
461 | { | 519 | { |
462 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; | 520 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; |
463 | |||
464 | struct spi_message *msg = dspi->cur_msg; | 521 | struct spi_message *msg = dspi->cur_msg; |
522 | enum dspi_trans_mode trans_mode; | ||
523 | u32 spi_sr, spi_tcr; | ||
524 | u32 spi_tcnt, tcnt_diff; | ||
525 | int tx_word; | ||
465 | 526 | ||
466 | regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF); | 527 | regmap_read(dspi->regmap, SPI_SR, &spi_sr); |
467 | dspi_transfer_read(dspi); | 528 | regmap_write(dspi->regmap, SPI_SR, spi_sr); |
468 | 529 | ||
469 | if (!dspi->len) { | 530 | |
531 | if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { | ||
532 | tx_word = is_double_byte_mode(dspi); | ||
533 | |||
534 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); | ||
535 | spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); | ||
536 | /* | ||
537 | * The width of SPI Transfer Counter in SPI_TCR is 16bits, | ||
538 | * so the max couner is 65535. When the counter reach 65535, | ||
539 | * it will wrap around, counter reset to zero. | ||
540 | * spi_tcnt my be less than dspi->spi_tcnt, it means the | ||
541 | * counter already wrapped around. | ||
542 | * SPI Transfer Counter is a counter of transmitted frames. | ||
543 | * The size of frame maybe two bytes. | ||
544 | */ | ||
545 | tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt) | ||
546 | % SPI_TCR_TCNT_MAX; | ||
547 | tcnt_diff *= (tx_word + 1); | ||
470 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) | 548 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) |
471 | regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), | 549 | tcnt_diff--; |
472 | SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16)); | 550 | |
551 | msg->actual_length += tcnt_diff; | ||
552 | |||
553 | dspi->spi_tcnt = spi_tcnt; | ||
554 | |||
555 | trans_mode = dspi->devtype_data->trans_mode; | ||
556 | switch (trans_mode) { | ||
557 | case DSPI_EOQ_MODE: | ||
558 | dspi_eoq_read(dspi); | ||
559 | break; | ||
560 | case DSPI_TCFQ_MODE: | ||
561 | dspi_tcfq_read(dspi); | ||
562 | break; | ||
563 | default: | ||
564 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", | ||
565 | trans_mode); | ||
566 | return IRQ_HANDLED; | ||
567 | } | ||
473 | 568 | ||
474 | dspi->waitflags = 1; | 569 | if (!dspi->len) { |
475 | wake_up_interruptible(&dspi->waitq); | 570 | if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) { |
476 | } else | 571 | regmap_update_bits(dspi->regmap, |
477 | msg->actual_length += dspi_transfer_write(dspi); | 572 | SPI_CTAR(dspi->cs), |
573 | SPI_FRAME_BITS_MASK, | ||
574 | SPI_FRAME_BITS(16)); | ||
575 | dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM; | ||
576 | } | ||
577 | |||
578 | dspi->waitflags = 1; | ||
579 | wake_up_interruptible(&dspi->waitq); | ||
580 | } else { | ||
581 | switch (trans_mode) { | ||
582 | case DSPI_EOQ_MODE: | ||
583 | dspi_eoq_write(dspi); | ||
584 | break; | ||
585 | case DSPI_TCFQ_MODE: | ||
586 | dspi_tcfq_write(dspi); | ||
587 | break; | ||
588 | default: | ||
589 | dev_err(&dspi->pdev->dev, | ||
590 | "unsupported trans_mode %u\n", | ||
591 | trans_mode); | ||
592 | } | ||
593 | } | ||
594 | } | ||
478 | 595 | ||
479 | return IRQ_HANDLED; | 596 | return IRQ_HANDLED; |
480 | } | 597 | } |
481 | 598 | ||
482 | static const struct of_device_id fsl_dspi_dt_ids[] = { | 599 | static const struct of_device_id fsl_dspi_dt_ids[] = { |
483 | { .compatible = "fsl,vf610-dspi", .data = NULL, }, | 600 | { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, }, |
601 | { .compatible = "fsl,ls1021a-v1.0-dspi", | ||
602 | .data = (void *)&ls1021a_v1_data, }, | ||
603 | { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, }, | ||
484 | { /* sentinel */ } | 604 | { /* sentinel */ } |
485 | }; | 605 | }; |
486 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); | 606 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); |
@@ -494,6 +614,8 @@ static int dspi_suspend(struct device *dev) | |||
494 | spi_master_suspend(master); | 614 | spi_master_suspend(master); |
495 | clk_disable_unprepare(dspi->clk); | 615 | clk_disable_unprepare(dspi->clk); |
496 | 616 | ||
617 | pinctrl_pm_select_sleep_state(dev); | ||
618 | |||
497 | return 0; | 619 | return 0; |
498 | } | 620 | } |
499 | 621 | ||
@@ -502,6 +624,8 @@ static int dspi_resume(struct device *dev) | |||
502 | struct spi_master *master = dev_get_drvdata(dev); | 624 | struct spi_master *master = dev_get_drvdata(dev); |
503 | struct fsl_dspi *dspi = spi_master_get_devdata(master); | 625 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
504 | 626 | ||
627 | pinctrl_pm_select_default_state(dev); | ||
628 | |||
505 | clk_prepare_enable(dspi->clk); | 629 | clk_prepare_enable(dspi->clk); |
506 | spi_master_resume(master); | 630 | spi_master_resume(master); |
507 | 631 | ||
@@ -526,6 +650,8 @@ static int dspi_probe(struct platform_device *pdev) | |||
526 | struct resource *res; | 650 | struct resource *res; |
527 | void __iomem *base; | 651 | void __iomem *base; |
528 | int ret = 0, cs_num, bus_num; | 652 | int ret = 0, cs_num, bus_num; |
653 | const struct of_device_id *of_id = | ||
654 | of_match_device(fsl_dspi_dt_ids, &pdev->dev); | ||
529 | 655 | ||
530 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); | 656 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); |
531 | if (!master) | 657 | if (!master) |
@@ -559,6 +685,13 @@ static int dspi_probe(struct platform_device *pdev) | |||
559 | } | 685 | } |
560 | master->bus_num = bus_num; | 686 | master->bus_num = bus_num; |
561 | 687 | ||
688 | dspi->devtype_data = (struct fsl_dspi_devtype_data *)of_id->data; | ||
689 | if (!dspi->devtype_data) { | ||
690 | dev_err(&pdev->dev, "can't get devtype_data\n"); | ||
691 | ret = -EFAULT; | ||
692 | goto out_master_put; | ||
693 | } | ||
694 | |||
562 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 695 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
563 | base = devm_ioremap_resource(&pdev->dev, res); | 696 | base = devm_ioremap_resource(&pdev->dev, res); |
564 | if (IS_ERR(base)) { | 697 | if (IS_ERR(base)) { |
@@ -566,7 +699,7 @@ static int dspi_probe(struct platform_device *pdev) | |||
566 | goto out_master_put; | 699 | goto out_master_put; |
567 | } | 700 | } |
568 | 701 | ||
569 | dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base, | 702 | dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, |
570 | &dspi_regmap_config); | 703 | &dspi_regmap_config); |
571 | if (IS_ERR(dspi->regmap)) { | 704 | if (IS_ERR(dspi->regmap)) { |
572 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", | 705 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", |