1 files changed, 67 insertions, 65 deletions

diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index 72c0bce5a75c..689d2c1cbead 100644
--- a/drivers/pwm/pwm-lpss.c
+++ b/drivers/pwm/pwm-lpss.c
@@ -15,6 +15,7 @@
 
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/iopoll.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pm_runtime.h>
@@ -37,30 +38,6 @@ struct pwm_lpss_chip {
         const struct pwm_lpss_boardinfo *info;
 };
 
-/* BayTrail */
-const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
-        .clk_rate = 25000000,
-        .npwm = 1,
-        .base_unit_bits = 16,
-};
-EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
-
-/* Braswell */
-const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
-        .clk_rate = 19200000,
-        .npwm = 1,
-        .base_unit_bits = 16,
-};
-EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
-
-/* Broxton */
-const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
-        .clk_rate = 19200000,
-        .npwm = 4,
-        .base_unit_bits = 22,
-};
-EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
-
 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
 {
         return container_of(chip, struct pwm_lpss_chip, chip);
@@ -80,17 +57,42 @@ static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
         writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
 }
 
-static void pwm_lpss_update(struct pwm_device *pwm)
+static int pwm_lpss_update(struct pwm_device *pwm)
 {
+        struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
+        const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
+        const unsigned int ms = 500 * USEC_PER_MSEC;
+        u32 val;
+        int err;
+
         pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
-        /* Give it some time to propagate */
-        usleep_range(10, 50);
+
+        /*
+         * PWM Configuration register has SW_UPDATE bit that is set when a new
+         * configuration is written to the register. The bit is automatically
+         * cleared at the start of the next output cycle by the IP block.
+         *
+         * If one writes a new configuration to the register while it still has
+         * the bit enabled, PWM may freeze. That is, while one can still write
+         * to the register, it won't have an effect. Thus, we try to sleep long
+         * enough that the bit gets cleared and make sure the bit is not
+         * enabled while we update the configuration.
+         */
+        err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
+        if (err)
+                dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
+
+        return err;
 }
 
-static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
-                           int duty_ns, int period_ns)
+static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
+{
+        return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
+}
+
+static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
+                             int duty_ns, int period_ns)
 {
-        struct pwm_lpss_chip *lpwm = to_lpwm(chip);
         unsigned long long on_time_div;
         unsigned long c = lpwm->info->clk_rate, base_unit_range;
         unsigned long long base_unit, freq = NSEC_PER_SEC;
@@ -102,62 +104,62 @@ static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
          * The equation is:
          * base_unit = round(base_unit_range * freq / c)
          */
-        base_unit_range = BIT(lpwm->info->base_unit_bits);
+        base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
         freq *= base_unit_range;
 
         base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
 
-        if (duty_ns <= 0)
-                duty_ns = 1;
         on_time_div = 255ULL * duty_ns;
         do_div(on_time_div, period_ns);
         on_time_div = 255ULL - on_time_div;
 
-        pm_runtime_get_sync(chip->dev);
-
         ctrl = pwm_lpss_read(pwm);
         ctrl &= ~PWM_ON_TIME_DIV_MASK;
-        ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
-        base_unit &= (base_unit_range - 1);
+        ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
+        base_unit &= base_unit_range;
         ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
         ctrl |= on_time_div;
         pwm_lpss_write(pwm, ctrl);
-
-        /*
-         * If the PWM is already enabled we need to notify the hardware
-         * about the change by setting PWM_SW_UPDATE.
-         */
-        if (pwm_is_enabled(pwm))
-                pwm_lpss_update(pwm);
-
-        pm_runtime_put(chip->dev);
-
-        return 0;
 }
 
-static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+                          struct pwm_state *state)
 {
-        pm_runtime_get_sync(chip->dev);
+        struct pwm_lpss_chip *lpwm = to_lpwm(chip);
+        int ret;
 
-        /*
-         * Hardware must first see PWM_SW_UPDATE before the PWM can be
-         * enabled.
-         */
-        pwm_lpss_update(pwm);
-        pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
-        return 0;
-}
+        if (state->enabled) {
+                if (!pwm_is_enabled(pwm)) {
+                        pm_runtime_get_sync(chip->dev);
+                        ret = pwm_lpss_is_updating(pwm);
+                        if (ret) {
+                                pm_runtime_put(chip->dev);
+                                return ret;
+                        }
+                        pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
+                        ret = pwm_lpss_update(pwm);
+                        if (ret) {
+                                pm_runtime_put(chip->dev);
+                                return ret;
+                        }
+                        pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
+                } else {
+                        ret = pwm_lpss_is_updating(pwm);
+                        if (ret)
+                                return ret;
+                        pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
+                        return pwm_lpss_update(pwm);
+                }
+        } else if (pwm_is_enabled(pwm)) {
+                pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
+                pm_runtime_put(chip->dev);
+        }
 
-static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
-        pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
-        pm_runtime_put(chip->dev);
+        return 0;
 }
 
 static const struct pwm_ops pwm_lpss_ops = {
-        .config = pwm_lpss_config,
-        .enable = pwm_lpss_enable,
-        .disable = pwm_lpss_disable,
+        .apply = pwm_lpss_apply,
         .owner = THIS_MODULE,
 };