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path: root/drivers/platform/x86/mlx-platform.c
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Diffstat (limited to 'drivers/platform/x86/mlx-platform.c')
-rw-r--r--drivers/platform/x86/mlx-platform.c23
1 files changed, 21 insertions, 2 deletions
diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
index 2e9f9e4302b2..e87fe34eadf5 100644
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -77,6 +77,8 @@
77#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 77#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
78#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 78#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
79 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 79 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
80#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
81#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc0
80#define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04 82#define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04
81#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 83#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
82#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 84#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
@@ -295,14 +297,29 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
295 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 297 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
296}; 298};
297 299
300static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
301 {
302 .label = "pwr1",
303 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
304 .mask = BIT(0),
305 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
306 },
307 {
308 .label = "pwr2",
309 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
310 .mask = BIT(1),
311 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
312 },
313};
314
298/* Platform hotplug MSN21xx system family data */ 315/* Platform hotplug MSN21xx system family data */
299static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 316static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = {
300 { 317 {
301 .data = mlxplat_mlxcpld_default_pwr_items_data, 318 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data,
302 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 319 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
303 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 320 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
304 .mask = MLXPLAT_CPLD_PWR_MASK, 321 .mask = MLXPLAT_CPLD_PWR_MASK,
305 .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr), 322 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data),
306 .inversed = 0, 323 .inversed = 0,
307 .health = false, 324 .health = false,
308 }, 325 },
@@ -314,6 +331,8 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {
314 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 331 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items),
315 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 332 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
316 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 333 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
334 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
335 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
317}; 336};
318 337
319static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 338static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)