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path: root/drivers/platform/x86/intel_pmc_ipc.c
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Diffstat (limited to 'drivers/platform/x86/intel_pmc_ipc.c')
-rw-r--r--drivers/platform/x86/intel_pmc_ipc.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c
index 0a39b0f17bbe..e4d4dfe3e1d1 100644
--- a/drivers/platform/x86/intel_pmc_ipc.c
+++ b/drivers/platform/x86/intel_pmc_ipc.c
@@ -57,10 +57,6 @@
57#define IPC_WRITE_BUFFER 0x80 57#define IPC_WRITE_BUFFER 0x80
58#define IPC_READ_BUFFER 0x90 58#define IPC_READ_BUFFER 0x90
59 59
60/* PMC Global Control Registers */
61#define GCR_TELEM_DEEP_S0IX_OFFSET 0x1078
62#define GCR_TELEM_SHLW_S0IX_OFFSET 0x1080
63
64/* Residency with clock rate at 19.2MHz to usecs */ 60/* Residency with clock rate at 19.2MHz to usecs */
65#define S0IX_RESIDENCY_IN_USECS(d, s) \ 61#define S0IX_RESIDENCY_IN_USECS(d, s) \
66({ \ 62({ \
@@ -202,7 +198,7 @@ static inline u32 ipc_data_readl(u32 offset)
202 198
203static inline u64 gcr_data_readq(u32 offset) 199static inline u64 gcr_data_readq(u32 offset)
204{ 200{
205 return readq(ipcdev.ipc_base + offset); 201 return readq(ipcdev.gcr_mem_base + offset);
206} 202}
207 203
208static inline int is_gcr_valid(u32 offset) 204static inline int is_gcr_valid(u32 offset)
@@ -902,8 +898,8 @@ int intel_pmc_s0ix_counter_read(u64 *data)
902 if (!ipcdev.has_gcr_regs) 898 if (!ipcdev.has_gcr_regs)
903 return -EACCES; 899 return -EACCES;
904 900
905 deep = gcr_data_readq(GCR_TELEM_DEEP_S0IX_OFFSET); 901 deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);
906 shlw = gcr_data_readq(GCR_TELEM_SHLW_S0IX_OFFSET); 902 shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);
907 903
908 *data = S0IX_RESIDENCY_IN_USECS(deep, shlw); 904 *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);
909 905