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path: root/drivers/pinctrl/sunxi
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Diffstat (limited to 'drivers/pinctrl/sunxi')
-rw-r--r--drivers/pinctrl/sunxi/Kconfig24
-rw-r--r--drivers/pinctrl/sunxi/Makefile2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c4
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c217
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c142
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c593
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c187
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h44
12 files changed, 1075 insertions, 142 deletions
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 73e0a305ea13..a5e10f777ed2 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -1,36 +1,42 @@
1if ARCH_SUNXI 1if ARCH_SUNXI
2 2
3config PINCTRL_SUNXI
4 bool
5
6config PINCTRL_SUNXI_COMMON 3config PINCTRL_SUNXI_COMMON
7 bool 4 bool
8 select PINMUX 5 select PINMUX
9 select GENERIC_PINCONF 6 select GENERIC_PINCONF
10 7
11config PINCTRL_SUN4I_A10 8config PINCTRL_SUN4I_A10
12 def_bool PINCTRL_SUNXI || MACH_SUN4I 9 def_bool MACH_SUN4I
13 select PINCTRL_SUNXI_COMMON 10 select PINCTRL_SUNXI_COMMON
14 11
15config PINCTRL_SUN5I_A10S 12config PINCTRL_SUN5I_A10S
16 def_bool PINCTRL_SUNXI || MACH_SUN5I 13 def_bool MACH_SUN5I
17 select PINCTRL_SUNXI_COMMON 14 select PINCTRL_SUNXI_COMMON
18 15
19config PINCTRL_SUN5I_A13 16config PINCTRL_SUN5I_A13
20 def_bool PINCTRL_SUNXI || MACH_SUN5I 17 def_bool MACH_SUN5I
21 select PINCTRL_SUNXI_COMMON 18 select PINCTRL_SUNXI_COMMON
22 19
23config PINCTRL_SUN6I_A31 20config PINCTRL_SUN6I_A31
24 def_bool PINCTRL_SUNXI || MACH_SUN6I 21 def_bool MACH_SUN6I
25 select PINCTRL_SUNXI_COMMON 22 select PINCTRL_SUNXI_COMMON
26 23
27config PINCTRL_SUN6I_A31_R 24config PINCTRL_SUN6I_A31_R
28 def_bool PINCTRL_SUNXI || MACH_SUN6I 25 def_bool MACH_SUN6I
29 depends on RESET_CONTROLLER 26 depends on RESET_CONTROLLER
30 select PINCTRL_SUNXI_COMMON 27 select PINCTRL_SUNXI_COMMON
31 28
32config PINCTRL_SUN7I_A20 29config PINCTRL_SUN7I_A20
33 def_bool PINCTRL_SUNXI || MACH_SUN7I 30 def_bool MACH_SUN7I
31 select PINCTRL_SUNXI_COMMON
32
33config PINCTRL_SUN8I_A23
34 def_bool MACH_SUN8I
35 select PINCTRL_SUNXI_COMMON
36
37config PINCTRL_SUN8I_A23_R
38 def_bool MACH_SUN8I
39 depends on RESET_CONTROLLER
34 select PINCTRL_SUNXI_COMMON 40 select PINCTRL_SUNXI_COMMON
35 41
36endif 42endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 0f4461cbe11d..e797efb02901 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o 8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o 9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o 10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
11obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
12obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index fa1ff7c7e357..86b608bedca6 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -1010,6 +1010,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
1010static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 1010static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1011 .pins = sun4i_a10_pins, 1011 .pins = sun4i_a10_pins,
1012 .npins = ARRAY_SIZE(sun4i_a10_pins), 1012 .npins = ARRAY_SIZE(sun4i_a10_pins),
1013 .irq_banks = 1,
1013}; 1014};
1014 1015
1015static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) 1016static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
index 164d743f526c..2fa7430cabaf 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
@@ -661,6 +661,7 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = { 661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
662 .pins = sun5i_a10s_pins, 662 .pins = sun5i_a10s_pins,
663 .npins = ARRAY_SIZE(sun5i_a10s_pins), 663 .npins = ARRAY_SIZE(sun5i_a10s_pins),
664 .irq_banks = 1,
664}; 665};
665 666
666static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev) 667static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
index 1188a2b7b988..e47c33dbae3a 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
@@ -330,15 +330,12 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
330 /* Hole */ 330 /* Hole */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
332 SUNXI_FUNCTION(0x0, "gpio_in"), 332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ 333 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
335 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 334 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
336 SUNXI_FUNCTION(0x0, "gpio_in"), 335 SUNXI_FUNCTION(0x0, "gpio_in"),
337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ 336 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 337 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
340 SUNXI_FUNCTION(0x0, "gpio_in"), 338 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ 339 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 340 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
344 SUNXI_FUNCTION(0x0, "gpio_in"), 341 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -382,6 +379,7 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
382static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { 379static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
383 .pins = sun5i_a13_pins, 380 .pins = sun5i_a13_pins,
384 .npins = ARRAY_SIZE(sun5i_a13_pins), 381 .npins = ARRAY_SIZE(sun5i_a13_pins),
382 .irq_banks = 1,
385}; 383};
386 384
387static int sun5i_a13_pinctrl_probe(struct platform_device *pdev) 385static int sun5i_a13_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index 8fcba48e0a42..9a2517b65113 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -93,6 +93,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
93 .pins = sun6i_a31_r_pins, 93 .pins = sun6i_a31_r_pins,
94 .npins = ARRAY_SIZE(sun6i_a31_r_pins), 94 .npins = ARRAY_SIZE(sun6i_a31_r_pins),
95 .pin_base = PL_BASE, 95 .pin_base = PL_BASE,
96 .irq_banks = 2,
96}; 97};
97 98
98static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) 99static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index 8dea5856458b..a2b4b85c5ad5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -24,208 +24,244 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
24 SUNXI_FUNCTION(0x1, "gpio_out"), 24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ 25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */ 26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
27 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 27 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"), 30 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"), 31 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ 32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
32 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */ 33 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
33 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 34 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
35 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"), 37 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"), 38 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ 39 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
38 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */ 40 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
39 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 41 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"), 44 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"), 45 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ 46 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
44 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */ 47 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
45 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 48 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"), 51 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"), 52 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ 53 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
50 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */ 54 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
51 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 55 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
56 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 57 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"), 58 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"), 59 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ 60 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
56 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */ 61 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
57 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 62 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
63 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"), 65 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"), 66 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ 67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
62 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */ 68 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
63 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 69 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
70 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"), 72 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"), 73 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ 74 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
68 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */ 75 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
69 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 76 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"), 79 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"), 80 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ 81 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
74 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */ 82 SUNXI_FUNCTION(0x3, "lcd1"), /* D8 */
83 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"), 85 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"), 86 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ 87 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
79 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */ 88 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
80 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ 89 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
81 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */ 90 SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
83 SUNXI_FUNCTION(0x0, "gpio_in"), 93 SUNXI_FUNCTION(0x0, "gpio_in"),
84 SUNXI_FUNCTION(0x1, "gpio_out"), 94 SUNXI_FUNCTION(0x1, "gpio_out"),
85 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ 95 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
86 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */ 96 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
87 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ 97 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
88 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */ 98 SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
99 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 100 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
90 SUNXI_FUNCTION(0x0, "gpio_in"), 101 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"), 102 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ 103 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
93 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */ 104 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
94 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ 105 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
95 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */ 106 SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
107 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 108 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
97 SUNXI_FUNCTION(0x0, "gpio_in"), 109 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"), 110 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ 111 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
100 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */ 112 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
101 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ 113 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
102 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */ 114 SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
115 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), 116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
104 SUNXI_FUNCTION(0x0, "gpio_in"), 117 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out"), 118 SUNXI_FUNCTION(0x1, "gpio_out"),
106 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ 119 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
107 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */ 120 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
108 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ 121 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
109 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */ 122 SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
123 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), 124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
111 SUNXI_FUNCTION(0x0, "gpio_in"), 125 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"), 126 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ 127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
114 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */ 128 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
115 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ 129 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
116 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */ 130 SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
131 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), 132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
118 SUNXI_FUNCTION(0x0, "gpio_in"), 133 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"), 134 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ 135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
121 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */ 136 SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
137 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), 138 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
123 SUNXI_FUNCTION(0x0, "gpio_in"), 139 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"), 140 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ 141 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
126 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */ 142 SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
143 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), 144 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
128 SUNXI_FUNCTION(0x0, "gpio_in"), 145 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"), 146 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ 147 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
131 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */ 148 SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
149 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), 150 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
133 SUNXI_FUNCTION(0x0, "gpio_in"), 151 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"), 152 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ 153 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
136 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */ 154 SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
155 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), 156 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
138 SUNXI_FUNCTION(0x0, "gpio_in"), 157 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"), 158 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ 159 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
141 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */ 160 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
142 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */ 161 SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
162 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), 163 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
144 SUNXI_FUNCTION(0x0, "gpio_in"), 164 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"), 165 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ 166 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
147 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */ 167 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
148 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */ 168 SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
169 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), 170 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
150 SUNXI_FUNCTION(0x0, "gpio_in"), 171 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"), 172 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ 173 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
153 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */ 174 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
154 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */ 175 SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
176 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22), 177 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
156 SUNXI_FUNCTION(0x0, "gpio_in"), 178 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"), 179 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ 180 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
159 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */ 181 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
160 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */ 182 SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
183 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
161 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23), 184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
162 SUNXI_FUNCTION(0x0, "gpio_in"), 185 SUNXI_FUNCTION(0x0, "gpio_in"),
163 SUNXI_FUNCTION(0x1, "gpio_out"), 186 SUNXI_FUNCTION(0x1, "gpio_out"),
164 SUNXI_FUNCTION(0x2, "gmac"), /* COL */ 187 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
165 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */ 188 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
166 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */ 189 SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
190 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24), 191 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
168 SUNXI_FUNCTION(0x0, "gpio_in"), 192 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"), 193 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ 194 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
171 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */ 195 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
172 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */ 196 SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
197 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25), 198 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
174 SUNXI_FUNCTION(0x0, "gpio_in"), 199 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"), 200 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ 201 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
177 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */ 202 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
178 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */ 203 SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
204 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26), 205 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
180 SUNXI_FUNCTION(0x0, "gpio_in"), 206 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"), 207 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ 208 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
183 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */ 209 SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
210 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), 211 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
185 SUNXI_FUNCTION(0x0, "gpio_in"), 212 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"), 213 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ 214 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
188 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */ 215 SUNXI_FUNCTION(0x3, "lcd1"), /* VSYNC */
216 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
189 /* Hole */ 217 /* Hole */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 218 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
191 SUNXI_FUNCTION(0x0, "gpio_in"), 219 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"), 220 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ 221 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
194 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 222 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
195 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */ 223 SUNXI_FUNCTION(0x4, "csi"), /* MCLK1 */
224 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
197 SUNXI_FUNCTION(0x0, "gpio_in"), 226 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"), 227 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */ 228 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
229 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
201 SUNXI_FUNCTION(0x0, "gpio_in"), 231 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"), 232 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */ 233 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
234 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 235 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
205 SUNXI_FUNCTION(0x0, "gpio_in"), 236 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"), 237 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */ 238 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
239 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 240 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
209 SUNXI_FUNCTION(0x0, "gpio_in"), 241 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"), 242 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ 243 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
212 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ 244 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
245 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
214 SUNXI_FUNCTION(0x0, "gpio_in"), 247 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"), 248 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ 249 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
217 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 250 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
218 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */ 251 SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
252 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
219 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 253 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
220 SUNXI_FUNCTION(0x0, "gpio_in"), 254 SUNXI_FUNCTION(0x0, "gpio_in"),
221 SUNXI_FUNCTION(0x1, "gpio_out"), 255 SUNXI_FUNCTION(0x1, "gpio_out"),
222 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ 256 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
223 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 257 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
224 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */ 258 SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
259 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 260 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
226 SUNXI_FUNCTION(0x0, "gpio_in"), 261 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"), 262 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */ 263 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
264 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
229 /* Hole */ 265 /* Hole */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 266 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
231 SUNXI_FUNCTION(0x0, "gpio_in"), 267 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -510,86 +546,103 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
510 SUNXI_FUNCTION(0x0, "gpio_in"), 546 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"), 547 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 548 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
513 SUNXI_FUNCTION(0x3, "ts")), /* CLK */ 549 SUNXI_FUNCTION(0x3, "ts"), /* CLK */
550 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 551 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
515 SUNXI_FUNCTION(0x0, "gpio_in"), 552 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"), 553 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 554 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
518 SUNXI_FUNCTION(0x3, "ts")), /* ERR */ 555 SUNXI_FUNCTION(0x3, "ts"), /* ERR */
556 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
520 SUNXI_FUNCTION(0x0, "gpio_in"), 558 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"), 559 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 560 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
523 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ 561 SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
562 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 563 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
525 SUNXI_FUNCTION(0x0, "gpio_in"), 564 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"), 565 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 566 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
528 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ 567 SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
568 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
530 SUNXI_FUNCTION(0x0, "gpio_in"), 570 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"), 571 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 572 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
533 SUNXI_FUNCTION(0x3, "uart5")), /* TX */ 573 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
574 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 575 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
535 SUNXI_FUNCTION(0x0, "gpio_in"), 576 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"), 577 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 578 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
538 SUNXI_FUNCTION(0x3, "uart5")), /* RX */ 579 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
580 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 581 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
540 SUNXI_FUNCTION(0x0, "gpio_in"), 582 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"), 583 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 584 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
543 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */ 585 SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
586 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 587 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
545 SUNXI_FUNCTION(0x0, "gpio_in"), 588 SUNXI_FUNCTION(0x0, "gpio_in"),
546 SUNXI_FUNCTION(0x1, "gpio_out"), 589 SUNXI_FUNCTION(0x1, "gpio_out"),
547 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 590 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
548 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */ 591 SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
592 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
549 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 593 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
550 SUNXI_FUNCTION(0x0, "gpio_in"), 594 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out"), 595 SUNXI_FUNCTION(0x1, "gpio_out"),
552 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 596 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
553 SUNXI_FUNCTION(0x3, "ts")), /* D0 */ 597 SUNXI_FUNCTION(0x3, "ts"), /* D0 */
598 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
554 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 599 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
555 SUNXI_FUNCTION(0x0, "gpio_in"), 600 SUNXI_FUNCTION(0x0, "gpio_in"),
556 SUNXI_FUNCTION(0x1, "gpio_out"), 601 SUNXI_FUNCTION(0x1, "gpio_out"),
557 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 602 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
558 SUNXI_FUNCTION(0x3, "ts")), /* D1 */ 603 SUNXI_FUNCTION(0x3, "ts"), /* D1 */
604 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
559 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 605 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
560 SUNXI_FUNCTION(0x0, "gpio_in"), 606 SUNXI_FUNCTION(0x0, "gpio_in"),
561 SUNXI_FUNCTION(0x1, "gpio_out"), 607 SUNXI_FUNCTION(0x1, "gpio_out"),
562 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 608 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
563 SUNXI_FUNCTION(0x3, "ts")), /* D2 */ 609 SUNXI_FUNCTION(0x3, "ts"), /* D2 */
610 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 611 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
565 SUNXI_FUNCTION(0x0, "gpio_in"), 612 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"), 613 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 614 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
568 SUNXI_FUNCTION(0x3, "ts")), /* D3 */ 615 SUNXI_FUNCTION(0x3, "ts"), /* D3 */
616 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 617 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
570 SUNXI_FUNCTION(0x0, "gpio_in"), 618 SUNXI_FUNCTION(0x0, "gpio_in"),
571 SUNXI_FUNCTION(0x1, "gpio_out"), 619 SUNXI_FUNCTION(0x1, "gpio_out"),
572 SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 620 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
573 SUNXI_FUNCTION(0x3, "ts")), /* D4 */ 621 SUNXI_FUNCTION(0x3, "ts"), /* D4 */
622 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 623 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
575 SUNXI_FUNCTION(0x0, "gpio_in"), 624 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"), 625 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 626 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
578 SUNXI_FUNCTION(0x3, "ts")), /* D5 */ 627 SUNXI_FUNCTION(0x3, "ts"), /* D5 */
628 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 629 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
580 SUNXI_FUNCTION(0x0, "gpio_in"), 630 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"), 631 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 632 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
583 SUNXI_FUNCTION(0x3, "ts")), /* D6 */ 633 SUNXI_FUNCTION(0x3, "ts"), /* D6 */
634 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
584 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 635 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
585 SUNXI_FUNCTION(0x0, "gpio_in"), 636 SUNXI_FUNCTION(0x0, "gpio_in"),
586 SUNXI_FUNCTION(0x1, "gpio_out"), 637 SUNXI_FUNCTION(0x1, "gpio_out"),
587 SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 638 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
588 SUNXI_FUNCTION(0x3, "ts")), /* D7 */ 639 SUNXI_FUNCTION(0x3, "ts"), /* D7 */
640 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
589 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 641 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
590 SUNXI_FUNCTION(0x0, "gpio_in"), 642 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out"), 643 SUNXI_FUNCTION(0x1, "gpio_out"),
592 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */ 644 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
645 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
593 /* Hole */ 646 /* Hole */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 647 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
595 SUNXI_FUNCTION(0x0, "gpio_in"), 648 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -625,86 +678,105 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
625 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 678 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
626 SUNXI_FUNCTION(0x0, "gpio_in"), 679 SUNXI_FUNCTION(0x0, "gpio_in"),
627 SUNXI_FUNCTION(0x1, "gpio_out"), 680 SUNXI_FUNCTION(0x1, "gpio_out"),
628 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */ 681 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
682 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
629 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 683 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
630 SUNXI_FUNCTION(0x0, "gpio_in"), 684 SUNXI_FUNCTION(0x0, "gpio_in"),
631 SUNXI_FUNCTION(0x1, "gpio_out"), 685 SUNXI_FUNCTION(0x1, "gpio_out"),
632 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */ 686 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
687 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 688 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
634 SUNXI_FUNCTION(0x0, "gpio_in"), 689 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"), 690 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */ 691 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
692 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
637 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 693 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
638 SUNXI_FUNCTION(0x0, "gpio_in"), 694 SUNXI_FUNCTION(0x0, "gpio_in"),
639 SUNXI_FUNCTION(0x1, "gpio_out"), 695 SUNXI_FUNCTION(0x1, "gpio_out"),
640 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */ 696 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
697 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
641 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 698 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
642 SUNXI_FUNCTION(0x0, "gpio_in"), 699 SUNXI_FUNCTION(0x0, "gpio_in"),
643 SUNXI_FUNCTION(0x1, "gpio_out"), 700 SUNXI_FUNCTION(0x1, "gpio_out"),
644 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */ 701 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
702 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
645 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 703 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
646 SUNXI_FUNCTION(0x0, "gpio_in"), 704 SUNXI_FUNCTION(0x0, "gpio_in"),
647 SUNXI_FUNCTION(0x1, "gpio_out"), 705 SUNXI_FUNCTION(0x1, "gpio_out"),
648 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */ 706 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
707 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 708 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
650 SUNXI_FUNCTION(0x0, "gpio_in"), 709 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"), 710 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "uart2")), /* TX */ 711 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
712 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
653 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 713 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
654 SUNXI_FUNCTION(0x0, "gpio_in"), 714 SUNXI_FUNCTION(0x0, "gpio_in"),
655 SUNXI_FUNCTION(0x1, "gpio_out"), 715 SUNXI_FUNCTION(0x1, "gpio_out"),
656 SUNXI_FUNCTION(0x2, "uart2")), /* RX */ 716 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
717 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 718 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
658 SUNXI_FUNCTION(0x0, "gpio_in"), 719 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"), 720 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */ 721 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
722 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 723 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
662 SUNXI_FUNCTION(0x0, "gpio_in"), 724 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"), 725 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */ 726 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
727 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 728 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
666 SUNXI_FUNCTION(0x0, "gpio_in"), 729 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"), 730 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ 731 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
669 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */ 732 SUNXI_FUNCTION(0x3, "usb"), /* DP3 */
733 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
670 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 734 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
671 SUNXI_FUNCTION(0x0, "gpio_in"), 735 SUNXI_FUNCTION(0x0, "gpio_in"),
672 SUNXI_FUNCTION(0x1, "gpio_out"), 736 SUNXI_FUNCTION(0x1, "gpio_out"),
673 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ 737 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
674 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */ 738 SUNXI_FUNCTION(0x3, "usb"), /* DM3 */
739 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 740 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
676 SUNXI_FUNCTION(0x0, "gpio_in"), 741 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out"), 742 SUNXI_FUNCTION(0x1, "gpio_out"),
678 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 743 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
679 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */ 744 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
745 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
680 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 746 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
681 SUNXI_FUNCTION(0x0, "gpio_in"), 747 SUNXI_FUNCTION(0x0, "gpio_in"),
682 SUNXI_FUNCTION(0x1, "gpio_out"), 748 SUNXI_FUNCTION(0x1, "gpio_out"),
683 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 749 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
684 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */ 750 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
751 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
685 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), 752 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
686 SUNXI_FUNCTION(0x0, "gpio_in"), 753 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out"), 754 SUNXI_FUNCTION(0x1, "gpio_out"),
688 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 755 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
689 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */ 756 SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
757 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
690 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), 758 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
691 SUNXI_FUNCTION(0x0, "gpio_in"), 759 SUNXI_FUNCTION(0x0, "gpio_in"),
692 SUNXI_FUNCTION(0x1, "gpio_out"), 760 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 761 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
694 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */ 762 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
763 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
695 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), 764 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
696 SUNXI_FUNCTION(0x0, "gpio_in"), 765 SUNXI_FUNCTION(0x0, "gpio_in"),
697 SUNXI_FUNCTION(0x1, "gpio_out"), 766 SUNXI_FUNCTION(0x1, "gpio_out"),
698 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 767 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
699 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */ 768 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
769 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
700 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), 770 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
701 SUNXI_FUNCTION(0x0, "gpio_in"), 771 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out"), 772 SUNXI_FUNCTION(0x1, "gpio_out"),
703 SUNXI_FUNCTION(0x2, "uart4")), /* TX */ 773 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
774 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), 775 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
705 SUNXI_FUNCTION(0x0, "gpio_in"), 776 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out"), 777 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "uart4")), /* RX */ 778 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
779 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
708 /* Hole */ 780 /* Hole */
709 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), 781 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
710 SUNXI_FUNCTION(0x0, "gpio_in"), 782 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -836,6 +908,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
836static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { 908static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
837 .pins = sun6i_a31_pins, 909 .pins = sun6i_a31_pins,
838 .npins = ARRAY_SIZE(sun6i_a31_pins), 910 .npins = ARRAY_SIZE(sun6i_a31_pins),
911 .irq_banks = 4,
839}; 912};
840 913
841static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) 914static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index d8577ce5f1a4..dac99e02bfdb 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -1036,6 +1036,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = { 1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
1037 .pins = sun7i_a20_pins, 1037 .pins = sun7i_a20_pins,
1038 .npins = ARRAY_SIZE(sun7i_a20_pins), 1038 .npins = ARRAY_SIZE(sun7i_a20_pins),
1039 .irq_banks = 1,
1039}; 1040};
1040 1041
1041static int sun7i_a20_pinctrl_probe(struct platform_device *pdev) 1042static int sun7i_a20_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
new file mode 100644
index 000000000000..90f3b3a7c51e
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
@@ -0,0 +1,142 @@
1/*
2 * Allwinner A23 SoCs special pins pinctrl driver.
3 *
4 * Copyright (C) 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
6 *
7 * Copyright (C) 2014 Boris Brezillon
8 * Boris Brezillon <boris.brezillon@free-electrons.com>
9 *
10 * Copyright (C) 2014 Maxime Ripard
11 * Maxime Ripard <maxime.ripard@free-electrons.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/reset.h>
24
25#include "pinctrl-sunxi.h"
26
27static const struct sunxi_desc_pin sun8i_a23_r_pins[] = {
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
32 SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
33 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
38 SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
39 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
44 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PL_EINT2 */
45 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
46 SUNXI_FUNCTION(0x0, "gpio_in"),
47 SUNXI_FUNCTION(0x1, "gpio_out"),
48 SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
49 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PL_EINT3 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */
54 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PL_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */
59 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PL_EINT5 */
60 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
61 SUNXI_FUNCTION(0x0, "gpio_in"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */
64 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PL_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */
69 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PL_EINT7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
74 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 8)), /* PL_EINT8 */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
79 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 9)), /* PL_EINT9 */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "s_pwm"),
84 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 10)), /* PL_EINT10 */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 11)), /* PL_EINT11 */
89};
90
91static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {
92 .pins = sun8i_a23_r_pins,
93 .npins = ARRAY_SIZE(sun8i_a23_r_pins),
94 .pin_base = PL_BASE,
95 .irq_banks = 1,
96};
97
98static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
99{
100 struct reset_control *rstc;
101 int ret;
102
103 rstc = devm_reset_control_get(&pdev->dev, NULL);
104 if (IS_ERR(rstc)) {
105 dev_err(&pdev->dev, "Reset controller missing\n");
106 return PTR_ERR(rstc);
107 }
108
109 ret = reset_control_deassert(rstc);
110 if (ret)
111 return ret;
112
113 ret = sunxi_pinctrl_init(pdev,
114 &sun8i_a23_r_pinctrl_data);
115
116 if (ret)
117 reset_control_assert(rstc);
118
119 return ret;
120}
121
122static struct of_device_id sun8i_a23_r_pinctrl_match[] = {
123 { .compatible = "allwinner,sun8i-a23-r-pinctrl", },
124 {}
125};
126MODULE_DEVICE_TABLE(of, sun8i_a23_r_pinctrl_match);
127
128static struct platform_driver sun8i_a23_r_pinctrl_driver = {
129 .probe = sun8i_a23_r_pinctrl_probe,
130 .driver = {
131 .name = "sun8i-a23-r-pinctrl",
132 .owner = THIS_MODULE,
133 .of_match_table = sun8i_a23_r_pinctrl_match,
134 },
135};
136module_platform_driver(sun8i_a23_r_pinctrl_driver);
137
138MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
139MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
140MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
141MODULE_DESCRIPTION("Allwinner A23 R_PIO pinctrl driver");
142MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
new file mode 100644
index 000000000000..ac71e8c5901b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
@@ -0,0 +1,593 @@
1/*
2 * Allwinner A23 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Chen-Yu Tsai
5 *
6 * Chen-Yu Tsai <wens@csie.org>
7 *
8 * Copyright (C) 2014 Maxime Ripard
9 *
10 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-sunxi.h"
24
25static const struct sunxi_desc_pin sun8i_a23_pins[] = {
26 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
27 SUNXI_FUNCTION(0x0, "gpio_in"),
28 SUNXI_FUNCTION(0x1, "gpio_out"),
29 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
30 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
31 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PA_EINT0 */
32 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
33 SUNXI_FUNCTION(0x0, "gpio_in"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
35 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
36 SUNXI_FUNCTION(0x3, "jtag"), /* CKO */
37 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PA_EINT1 */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
39 SUNXI_FUNCTION(0x0, "gpio_in"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
41 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
42 SUNXI_FUNCTION(0x3, "jtag"), /* DOO */
43 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PA_EINT2 */
44 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
45 SUNXI_FUNCTION(0x0, "gpio_in"),
46 SUNXI_FUNCTION(0x1, "gpio_out"),
47 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
48 SUNXI_FUNCTION(0x3, "jtag"), /* DIO */
49 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PA_EINT3 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
54 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PA_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
59 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PA_EINT5 */
60 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
61 SUNXI_FUNCTION(0x0, "gpio_in"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
64 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PA_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
69 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PA_EINT7 */
70 /* Hole */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
75 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PB_EINT0 */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
80 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PB_EINT1 */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
85 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PB_EINT2 */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
90 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PB_EINT3 */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
95 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PB_EINT4 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
97 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
100 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PB_EINT5 */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
105 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PB_EINT6 */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
110 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PB_EINT7 */
111 /* Hole */
112 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
113 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out"),
115 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
116 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
121 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
123 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
126 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
131 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
140 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
141 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
142 SUNXI_FUNCTION(0x0, "gpio_in"),
143 SUNXI_FUNCTION(0x1, "gpio_out"),
144 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
145 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
154 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
159 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
164 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
165 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
166 SUNXI_FUNCTION(0x0, "gpio_in"),
167 SUNXI_FUNCTION(0x1, "gpio_out"),
168 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
169 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
170 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
171 SUNXI_FUNCTION(0x0, "gpio_in"),
172 SUNXI_FUNCTION(0x1, "gpio_out"),
173 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
174 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
179 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
184 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
189 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
194 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
203 /* Hole */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
216 SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
221 SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
226 SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
231 SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
232 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
233 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out"),
235 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
236 SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
241 SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
246 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
251 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
252 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
253 SUNXI_FUNCTION(0x0, "gpio_in"),
254 SUNXI_FUNCTION(0x1, "gpio_out"),
255 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
256 SUNXI_FUNCTION(0x3, "uart1")), /* TX */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
261 SUNXI_FUNCTION(0x3, "uart1")), /* RX */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
266 SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
267 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
271 SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
276 SUNXI_FUNCTION(0x3, "i2s1")), /* SYNC */
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
281 SUNXI_FUNCTION(0x3, "i2s1")), /* CLK */
282 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
283 SUNXI_FUNCTION(0x0, "gpio_in"),
284 SUNXI_FUNCTION(0x1, "gpio_out"),
285 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
286 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
291 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
296 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
301 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
303 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out"),
305 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
306 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
307 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
308 SUNXI_FUNCTION(0x0, "gpio_in"),
309 SUNXI_FUNCTION(0x1, "gpio_out"),
310 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
311 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
316 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
321 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
326 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
327 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
328 SUNXI_FUNCTION(0x0, "gpio_in"),
329 SUNXI_FUNCTION(0x1, "gpio_out"),
330 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
331 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
336 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
341 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
342 /* Hole */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
344 SUNXI_FUNCTION(0x0, "gpio_in"),
345 SUNXI_FUNCTION(0x1, "gpio_out"),
346 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out"),
354 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
359 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
360 SUNXI_FUNCTION(0x0, "gpio_in"),
361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "csi")), /* D2 */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "csi")), /* D3 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "csi")), /* D4 */
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "csi")), /* D5 */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "csi")), /* D6 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "csi")), /* D7 */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out"),
394 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
395 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
396 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
397 SUNXI_FUNCTION(0x0, "gpio_in"),
398 SUNXI_FUNCTION(0x1, "gpio_out"),
399 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
400 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
401 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
402 SUNXI_FUNCTION(0x0, "gpio_in"),
403 SUNXI_FUNCTION(0x1, "gpio_out")),
404 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
405 SUNXI_FUNCTION(0x0, "gpio_in"),
406 SUNXI_FUNCTION(0x1, "gpio_out")),
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out")),
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out")),
413 /* Hole */
414 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
415 SUNXI_FUNCTION(0x0, "gpio_in"),
416 SUNXI_FUNCTION(0x1, "gpio_out"),
417 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
418 SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
419 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
420 SUNXI_FUNCTION(0x0, "gpio_in"),
421 SUNXI_FUNCTION(0x1, "gpio_out"),
422 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
423 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
424 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
425 SUNXI_FUNCTION(0x0, "gpio_in"),
426 SUNXI_FUNCTION(0x1, "gpio_out"),
427 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
428 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
429 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
430 SUNXI_FUNCTION(0x0, "gpio_in"),
431 SUNXI_FUNCTION(0x1, "gpio_out"),
432 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
433 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
434 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
435 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out"),
437 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
438 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
439 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
440 SUNXI_FUNCTION(0x0, "gpio_in"),
441 SUNXI_FUNCTION(0x1, "gpio_out"),
442 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
443 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
444 /* Hole */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
449 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 0)), /* PG_EINT0 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
454 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 1)), /* PG_EINT1 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
459 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 2)), /* PG_EINT2 */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
464 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 3)), /* PG_EINT3 */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
469 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 4)), /* PG_EINT4 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
474 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 5)), /* PG_EINT5 */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
479 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 6)), /* PG_EINT6 */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
484 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 7)), /* PG_EINT7 */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
489 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)), /* PG_EINT8 */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
494 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)), /* PG_EINT9 */
495 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
496 SUNXI_FUNCTION(0x0, "gpio_in"),
497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
499 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 10)), /* PG_EINT10 */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
504 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 11)), /* PG_EINT11 */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
509 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 12)), /* PG_EINT12 */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
514 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 13)), /* PG_EINT13 */
515 /* Hole */
516 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "pwm0")),
520 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
521 SUNXI_FUNCTION(0x0, "gpio_in"),
522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "pwm1")),
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
528 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
529 SUNXI_FUNCTION(0x0, "gpio_in"),
530 SUNXI_FUNCTION(0x1, "gpio_out"),
531 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
536 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
537 SUNXI_FUNCTION(0x0, "gpio_in"),
538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
541 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out"),
543 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
544 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
549 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
554 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
559 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
560};
561
562static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = {
563 .pins = sun8i_a23_pins,
564 .npins = ARRAY_SIZE(sun8i_a23_pins),
565 .irq_banks = 3,
566};
567
568static int sun8i_a23_pinctrl_probe(struct platform_device *pdev)
569{
570 return sunxi_pinctrl_init(pdev,
571 &sun8i_a23_pinctrl_data);
572}
573
574static struct of_device_id sun8i_a23_pinctrl_match[] = {
575 { .compatible = "allwinner,sun8i-a23-pinctrl", },
576 {}
577};
578MODULE_DEVICE_TABLE(of, sun8i_a23_pinctrl_match);
579
580static struct platform_driver sun8i_a23_pinctrl_driver = {
581 .probe = sun8i_a23_pinctrl_probe,
582 .driver = {
583 .name = "sun8i-a23-pinctrl",
584 .owner = THIS_MODULE,
585 .of_match_table = sun8i_a23_pinctrl_match,
586 },
587};
588module_platform_driver(sun8i_a23_pinctrl_driver);
589
590MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
591MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
592MODULE_DESCRIPTION("Allwinner A23 pinctrl driver");
593MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 5f38c7f67834..3df66e366c87 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -31,6 +31,9 @@
31#include "../core.h" 31#include "../core.h"
32#include "pinctrl-sunxi.h" 32#include "pinctrl-sunxi.h"
33 33
34static struct irq_chip sunxi_pinctrl_edge_irq_chip;
35static struct irq_chip sunxi_pinctrl_level_irq_chip;
36
34static struct sunxi_pinctrl_group * 37static struct sunxi_pinctrl_group *
35sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 38sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
36{ 39{
@@ -508,7 +511,7 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
508 base = PINS_PER_BANK * gpiospec->args[0]; 511 base = PINS_PER_BANK * gpiospec->args[0];
509 pin = base + gpiospec->args[1]; 512 pin = base + gpiospec->args[1];
510 513
511 if (pin > (gc->base + gc->ngpio)) 514 if (pin > gc->ngpio)
512 return -EINVAL; 515 return -EINVAL;
513 516
514 if (flags) 517 if (flags)
@@ -521,25 +524,61 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
521{ 524{
522 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 525 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
523 struct sunxi_desc_function *desc; 526 struct sunxi_desc_function *desc;
527 unsigned pinnum = pctl->desc->pin_base + offset;
528 unsigned irqnum;
524 529
525 if (offset >= chip->ngpio) 530 if (offset >= chip->ngpio)
526 return -ENXIO; 531 return -ENXIO;
527 532
528 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); 533 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
529 if (!desc) 534 if (!desc)
530 return -EINVAL; 535 return -EINVAL;
531 536
537 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
538
532 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 539 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
533 chip->label, offset + chip->base, desc->irqnum); 540 chip->label, offset + chip->base, irqnum);
534 541
535 return irq_find_mapping(pctl->domain, desc->irqnum); 542 return irq_find_mapping(pctl->domain, irqnum);
536} 543}
537 544
545static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
546{
547 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
548 struct sunxi_desc_function *func;
549 int ret;
550
551 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
552 pctl->irq_array[d->hwirq], "irq");
553 if (!func)
554 return -EINVAL;
555
556 ret = gpio_lock_as_irq(pctl->chip,
557 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
558 if (ret) {
559 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
560 irqd_to_hwirq(d));
561 return ret;
562 }
563
564 /* Change muxing to INT mode */
565 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
538 566
539static int sunxi_pinctrl_irq_set_type(struct irq_data *d, 567 return 0;
540 unsigned int type) 568}
569
570static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
571{
572 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
573
574 gpio_unlock_as_irq(pctl->chip,
575 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
576}
577
578static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
541{ 579{
542 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 580 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
581 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
543 u32 reg = sunxi_irq_cfg_reg(d->hwirq); 582 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
544 u8 index = sunxi_irq_cfg_offset(d->hwirq); 583 u8 index = sunxi_irq_cfg_offset(d->hwirq);
545 unsigned long flags; 584 unsigned long flags;
@@ -566,6 +605,14 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
566 return -EINVAL; 605 return -EINVAL;
567 } 606 }
568 607
608 if (type & IRQ_TYPE_LEVEL_MASK) {
609 d->chip = &sunxi_pinctrl_level_irq_chip;
610 desc->handle_irq = handle_fasteoi_irq;
611 } else {
612 d->chip = &sunxi_pinctrl_edge_irq_chip;
613 desc->handle_irq = handle_edge_irq;
614 }
615
569 spin_lock_irqsave(&pctl->lock, flags); 616 spin_lock_irqsave(&pctl->lock, flags);
570 617
571 regval = readl(pctl->membase + reg); 618 regval = readl(pctl->membase + reg);
@@ -577,26 +624,14 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
577 return 0; 624 return 0;
578} 625}
579 626
580static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) 627static void sunxi_pinctrl_irq_ack(struct irq_data *d)
581{ 628{
582 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 629 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
583 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
584 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
585 u32 status_reg = sunxi_irq_status_reg(d->hwirq); 630 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
586 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 631 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
587 unsigned long flags;
588 u32 val;
589
590 spin_lock_irqsave(&pctl->lock, flags);
591
592 /* Mask the IRQ */
593 val = readl(pctl->membase + ctrl_reg);
594 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
595 632
596 /* Clear the IRQ */ 633 /* Clear the IRQ */
597 writel(1 << status_idx, pctl->membase + status_reg); 634 writel(1 << status_idx, pctl->membase + status_reg);
598
599 spin_unlock_irqrestore(&pctl->lock, flags);
600} 635}
601 636
602static void sunxi_pinctrl_irq_mask(struct irq_data *d) 637static void sunxi_pinctrl_irq_mask(struct irq_data *d)
@@ -619,19 +654,11 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
619static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 654static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
620{ 655{
621 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 656 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
622 struct sunxi_desc_function *func;
623 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 657 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
624 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 658 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
625 unsigned long flags; 659 unsigned long flags;
626 u32 val; 660 u32 val;
627 661
628 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
629 pctl->irq_array[d->hwirq],
630 "irq");
631
632 /* Change muxing to INT mode */
633 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
634
635 spin_lock_irqsave(&pctl->lock, flags); 662 spin_lock_irqsave(&pctl->lock, flags);
636 663
637 /* Unmask the IRQ */ 664 /* Unmask the IRQ */
@@ -641,28 +668,60 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
641 spin_unlock_irqrestore(&pctl->lock, flags); 668 spin_unlock_irqrestore(&pctl->lock, flags);
642} 669}
643 670
644static struct irq_chip sunxi_pinctrl_irq_chip = { 671static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
672{
673 sunxi_pinctrl_irq_ack(d);
674 sunxi_pinctrl_irq_unmask(d);
675}
676
677static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
678 .irq_ack = sunxi_pinctrl_irq_ack,
679 .irq_mask = sunxi_pinctrl_irq_mask,
680 .irq_unmask = sunxi_pinctrl_irq_unmask,
681 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
682 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
683 .irq_set_type = sunxi_pinctrl_irq_set_type,
684 .flags = IRQCHIP_SKIP_SET_WAKE,
685};
686
687static struct irq_chip sunxi_pinctrl_level_irq_chip = {
688 .irq_eoi = sunxi_pinctrl_irq_ack,
645 .irq_mask = sunxi_pinctrl_irq_mask, 689 .irq_mask = sunxi_pinctrl_irq_mask,
646 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
647 .irq_unmask = sunxi_pinctrl_irq_unmask, 690 .irq_unmask = sunxi_pinctrl_irq_unmask,
691 /* Define irq_enable / disable to avoid spurious irqs for drivers
692 * using these to suppress irqs while they clear the irq source */
693 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
694 .irq_disable = sunxi_pinctrl_irq_mask,
695 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
696 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
648 .irq_set_type = sunxi_pinctrl_irq_set_type, 697 .irq_set_type = sunxi_pinctrl_irq_set_type,
698 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
699 IRQCHIP_EOI_IF_HANDLED,
649}; 700};
650 701
651static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) 702static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
652{ 703{
653 struct irq_chip *chip = irq_get_chip(irq); 704 struct irq_chip *chip = irq_get_chip(irq);
654 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); 705 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
655 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); 706 unsigned long bank, reg, val;
707
708 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
709 if (irq == pctl->irq[bank])
710 break;
711
712 if (bank == pctl->desc->irq_banks)
713 return;
656 714
657 /* Clear all interrupts */ 715 reg = sunxi_irq_status_reg_from_bank(bank);
658 writel(reg, pctl->membase + IRQ_STATUS_REG); 716 val = readl(pctl->membase + reg);
659 717
660 if (reg) { 718 if (val) {
661 int irqoffset; 719 int irqoffset;
662 720
663 chained_irq_enter(chip, desc); 721 chained_irq_enter(chip, desc);
664 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) { 722 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
665 int pin_irq = irq_find_mapping(pctl->domain, irqoffset); 723 int pin_irq = irq_find_mapping(pctl->domain,
724 bank * IRQ_PER_BANK + irqoffset);
666 generic_handle_irq(pin_irq); 725 generic_handle_irq(pin_irq);
667 } 726 }
668 chained_irq_exit(chip, desc); 727 chained_irq_exit(chip, desc);
@@ -730,8 +789,11 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev)
730 789
731 while (func->name) { 790 while (func->name) {
732 /* Create interrupt mapping while we're at it */ 791 /* Create interrupt mapping while we're at it */
733 if (!strcmp(func->name, "irq")) 792 if (!strcmp(func->name, "irq")) {
734 pctl->irq_array[func->irqnum] = pin->pin.number; 793 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
794 pctl->irq_array[irqnum] = pin->pin.number;
795 }
796
735 sunxi_pinctrl_add_function(pctl, func->name); 797 sunxi_pinctrl_add_function(pctl, func->name);
736 func++; 798 func++;
737 } 799 }
@@ -801,6 +863,13 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
801 pctl->dev = &pdev->dev; 863 pctl->dev = &pdev->dev;
802 pctl->desc = desc; 864 pctl->desc = desc;
803 865
866 pctl->irq_array = devm_kcalloc(&pdev->dev,
867 IRQ_PER_BANK * pctl->desc->irq_banks,
868 sizeof(*pctl->irq_array),
869 GFP_KERNEL);
870 if (!pctl->irq_array)
871 return -ENOMEM;
872
804 ret = sunxi_pinctrl_build_state(pdev); 873 ret = sunxi_pinctrl_build_state(pdev);
805 if (ret) { 874 if (ret) {
806 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 875 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
@@ -869,7 +938,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
869 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 938 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
870 939
871 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 940 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
872 pin->pin.number, 941 pin->pin.number - pctl->desc->pin_base,
873 pin->pin.number, 1); 942 pin->pin.number, 1);
874 if (ret) 943 if (ret)
875 goto gpiochip_error; 944 goto gpiochip_error;
@@ -885,30 +954,51 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
885 if (ret) 954 if (ret)
886 goto gpiochip_error; 955 goto gpiochip_error;
887 956
888 pctl->irq = irq_of_parse_and_map(node, 0); 957 pctl->irq = devm_kcalloc(&pdev->dev,
958 pctl->desc->irq_banks,
959 sizeof(*pctl->irq),
960 GFP_KERNEL);
889 if (!pctl->irq) { 961 if (!pctl->irq) {
890 ret = -EINVAL; 962 ret = -ENOMEM;
891 goto clk_error; 963 goto clk_error;
892 } 964 }
893 965
894 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, 966 for (i = 0; i < pctl->desc->irq_banks; i++) {
895 &irq_domain_simple_ops, NULL); 967 pctl->irq[i] = platform_get_irq(pdev, i);
968 if (pctl->irq[i] < 0) {
969 ret = pctl->irq[i];
970 goto clk_error;
971 }
972 }
973
974 pctl->domain = irq_domain_add_linear(node,
975 pctl->desc->irq_banks * IRQ_PER_BANK,
976 &irq_domain_simple_ops,
977 NULL);
896 if (!pctl->domain) { 978 if (!pctl->domain) {
897 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 979 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
898 ret = -ENOMEM; 980 ret = -ENOMEM;
899 goto clk_error; 981 goto clk_error;
900 } 982 }
901 983
902 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { 984 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
903 int irqno = irq_create_mapping(pctl->domain, i); 985 int irqno = irq_create_mapping(pctl->domain, i);
904 986
905 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, 987 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
906 handle_simple_irq); 988 handle_edge_irq);
907 irq_set_chip_data(irqno, pctl); 989 irq_set_chip_data(irqno, pctl);
908 }; 990 };
909 991
910 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); 992 for (i = 0; i < pctl->desc->irq_banks; i++) {
911 irq_set_handler_data(pctl->irq, pctl); 993 /* Mask and clear all IRQs before registering a handler */
994 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i));
995 writel(0xffffffff,
996 pctl->membase + sunxi_irq_status_reg_from_bank(i));
997
998 irq_set_chained_handler(pctl->irq[i],
999 sunxi_pinctrl_irq_handler);
1000 irq_set_handler_data(pctl->irq[i], pctl);
1001 }
912 1002
913 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1003 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
914 1004
@@ -917,8 +1007,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
917clk_error: 1007clk_error:
918 clk_disable_unprepare(clk); 1008 clk_disable_unprepare(clk);
919gpiochip_error: 1009gpiochip_error:
920 if (gpiochip_remove(pctl->chip)) 1010 gpiochip_remove(pctl->chip);
921 dev_err(&pdev->dev, "failed to remove gpio chip\n");
922pinctrl_error: 1011pinctrl_error:
923 pinctrl_unregister(pctl->pctl_dev); 1012 pinctrl_unregister(pctl->pctl_dev);
924 return ret; 1013 return ret;
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 8169ba598876..4245b96c7996 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -53,7 +53,7 @@
53#define PULL_PINS_BITS 2 53#define PULL_PINS_BITS 2
54#define PULL_PINS_MASK 0x03 54#define PULL_PINS_MASK 0x03
55 55
56#define SUNXI_IRQ_NUMBER 32 56#define IRQ_PER_BANK 32
57 57
58#define IRQ_CFG_REG 0x200 58#define IRQ_CFG_REG 0x200
59#define IRQ_CFG_IRQ_PER_REG 8 59#define IRQ_CFG_IRQ_PER_REG 8
@@ -68,6 +68,8 @@
68#define IRQ_STATUS_IRQ_BITS 1 68#define IRQ_STATUS_IRQ_BITS 1
69#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 69#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
70 70
71#define IRQ_MEM_SIZE 0x20
72
71#define IRQ_EDGE_RISING 0x00 73#define IRQ_EDGE_RISING 0x00
72#define IRQ_EDGE_FALLING 0x01 74#define IRQ_EDGE_FALLING 0x01
73#define IRQ_LEVEL_HIGH 0x02 75#define IRQ_LEVEL_HIGH 0x02
@@ -77,6 +79,7 @@
77struct sunxi_desc_function { 79struct sunxi_desc_function {
78 const char *name; 80 const char *name;
79 u8 muxval; 81 u8 muxval;
82 u8 irqbank;
80 u8 irqnum; 83 u8 irqnum;
81}; 84};
82 85
@@ -89,6 +92,7 @@ struct sunxi_pinctrl_desc {
89 const struct sunxi_desc_pin *pins; 92 const struct sunxi_desc_pin *pins;
90 int npins; 93 int npins;
91 unsigned pin_base; 94 unsigned pin_base;
95 unsigned irq_banks;
92}; 96};
93 97
94struct sunxi_pinctrl_function { 98struct sunxi_pinctrl_function {
@@ -113,8 +117,8 @@ struct sunxi_pinctrl {
113 unsigned nfunctions; 117 unsigned nfunctions;
114 struct sunxi_pinctrl_group *groups; 118 struct sunxi_pinctrl_group *groups;
115 unsigned ngroups; 119 unsigned ngroups;
116 int irq; 120 int *irq;
117 int irq_array[SUNXI_IRQ_NUMBER]; 121 unsigned *irq_array;
118 spinlock_t lock; 122 spinlock_t lock;
119 struct pinctrl_dev *pctl_dev; 123 struct pinctrl_dev *pctl_dev;
120}; 124};
@@ -139,6 +143,14 @@ struct sunxi_pinctrl {
139 .irqnum = _irq, \ 143 .irqnum = _irq, \
140 } 144 }
141 145
146#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
147 { \
148 .name = "irq", \
149 .muxval = _val, \
150 .irqbank = _bank, \
151 .irqnum = _irq, \
152 }
153
142/* 154/*
143 * The sunXi PIO registers are organized as is: 155 * The sunXi PIO registers are organized as is:
144 * 0x00 - 0x0c Muxing values. 156 * 0x00 - 0x0c Muxing values.
@@ -218,8 +230,10 @@ static inline u32 sunxi_pull_offset(u16 pin)
218 230
219static inline u32 sunxi_irq_cfg_reg(u16 irq) 231static inline u32 sunxi_irq_cfg_reg(u16 irq)
220{ 232{
221 u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04; 233 u8 bank = irq / IRQ_PER_BANK;
222 return reg + IRQ_CFG_REG; 234 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
235
236 return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
223} 237}
224 238
225static inline u32 sunxi_irq_cfg_offset(u16 irq) 239static inline u32 sunxi_irq_cfg_offset(u16 irq)
@@ -228,10 +242,16 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
228 return irq_num * IRQ_CFG_IRQ_BITS; 242 return irq_num * IRQ_CFG_IRQ_BITS;
229} 243}
230 244
245static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
246{
247 return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
248}
249
231static inline u32 sunxi_irq_ctrl_reg(u16 irq) 250static inline u32 sunxi_irq_ctrl_reg(u16 irq)
232{ 251{
233 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04; 252 u8 bank = irq / IRQ_PER_BANK;
234 return reg + IRQ_CTRL_REG; 253
254 return sunxi_irq_ctrl_reg_from_bank(bank);
235} 255}
236 256
237static inline u32 sunxi_irq_ctrl_offset(u16 irq) 257static inline u32 sunxi_irq_ctrl_offset(u16 irq)
@@ -240,10 +260,16 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
240 return irq_num * IRQ_CTRL_IRQ_BITS; 260 return irq_num * IRQ_CTRL_IRQ_BITS;
241} 261}
242 262
263static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
264{
265 return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
266}
267
243static inline u32 sunxi_irq_status_reg(u16 irq) 268static inline u32 sunxi_irq_status_reg(u16 irq)
244{ 269{
245 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04; 270 u8 bank = irq / IRQ_PER_BANK;
246 return reg + IRQ_STATUS_REG; 271
272 return sunxi_irq_status_reg_from_bank(bank);
247} 273}
248 274
249static inline u32 sunxi_irq_status_offset(u16 irq) 275static inline u32 sunxi_irq_status_offset(u16 irq)
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-02 15:58:17 -0400