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path: root/drivers/pinctrl/pinctrl-pistachio.c
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-rw-r--r--drivers/pinctrl/pinctrl-pistachio.c1504
1 files changed, 1504 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c
new file mode 100644
index 000000000000..63100be81015
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-pistachio.c
@@ -0,0 +1,1504 @@
1/*
2 * Pistachio SoC pinctrl driver
3 *
4 * Copyright (C) 2014 Imagination Technologies Ltd.
5 * Copyright (C) 2014 Google, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 */
11
12#include <linux/gpio.h>
13#include <linux/gpio/driver.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26
27#include "pinctrl-utils.h"
28
29#define PADS_SCHMITT_EN0 0x000
30#define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))
31#define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32)
32
33#define PADS_PU_PD0 0x040
34#define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16))
35#define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16))
36#define PADS_PU_PD_MASK 0x3
37#define PADS_PU_PD_HIGHZ 0x0
38#define PADS_PU_PD_UP 0x1
39#define PADS_PU_PD_DOWN 0x2
40#define PADS_PU_PD_BUS 0x3
41
42#define PADS_FUNCTION_SELECT0 0x0c0
43#define PADS_FUNCTION_SELECT1 0x0c4
44#define PADS_FUNCTION_SELECT2 0x0c8
45#define PADS_SCENARIO_SELECT 0x0f8
46
47#define PADS_SLEW_RATE0 0x100
48#define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))
49#define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32)
50
51#define PADS_DRIVE_STRENGTH0 0x120
52#define PADS_DRIVE_STRENGTH_REG(pin) \
53 (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
54#define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16))
55#define PADS_DRIVE_STRENGTH_MASK 0x3
56#define PADS_DRIVE_STRENGTH_2MA 0x0
57#define PADS_DRIVE_STRENGTH_4MA 0x1
58#define PADS_DRIVE_STRENGTH_8MA 0x2
59#define PADS_DRIVE_STRENGTH_12MA 0x3
60
61#define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank))
62
63#define GPIO_BIT_EN 0x00
64#define GPIO_OUTPUT_EN 0x04
65#define GPIO_OUTPUT 0x08
66#define GPIO_INPUT 0x0c
67#define GPIO_INPUT_POLARITY 0x10
68#define GPIO_INTERRUPT_TYPE 0x14
69#define GPIO_INTERRUPT_TYPE_LEVEL 0x0
70#define GPIO_INTERRUPT_TYPE_EDGE 0x1
71#define GPIO_INTERRUPT_EDGE 0x18
72#define GPIO_INTERRUPT_EDGE_SINGLE 0x0
73#define GPIO_INTERRUPT_EDGE_DUAL 0x1
74#define GPIO_INTERRUPT_EN 0x1c
75#define GPIO_INTERRUPT_STATUS 0x20
76
77struct pistachio_function {
78 const char *name;
79 const char * const *groups;
80 unsigned int ngroups;
81 const int *scenarios;
82 unsigned int nscenarios;
83 unsigned int scenario_reg;
84 unsigned int scenario_shift;
85 unsigned int scenario_mask;
86};
87
88struct pistachio_pin_group {
89 const char *name;
90 unsigned int pin;
91 int mux_option[3];
92 int mux_reg;
93 int mux_shift;
94 int mux_mask;
95};
96
97struct pistachio_gpio_bank {
98 struct pistachio_pinctrl *pctl;
99 void __iomem *base;
100 unsigned int pin_base;
101 unsigned int npins;
102 struct gpio_chip gpio_chip;
103 struct irq_chip irq_chip;
104};
105
106struct pistachio_pinctrl {
107 struct device *dev;
108 void __iomem *base;
109 struct pinctrl_dev *pctldev;
110 const struct pinctrl_pin_desc *pins;
111 unsigned int npins;
112 const struct pistachio_function *functions;
113 unsigned int nfunctions;
114 const struct pistachio_pin_group *groups;
115 unsigned int ngroups;
116 struct pistachio_gpio_bank *gpio_banks;
117 unsigned int nbanks;
118};
119
120#define PISTACHIO_PIN_MFIO(p) (p)
121#define PISTACHIO_PIN_TCK 90
122#define PISTACHIO_PIN_TRSTN 91
123#define PISTACHIO_PIN_TDI 92
124#define PISTACHIO_PIN_TMS 93
125#define PISTACHIO_PIN_TDO 94
126#define PISTACHIO_PIN_JTAG_COMPLY 95
127#define PISTACHIO_PIN_SAFE_MODE 96
128#define PISTACHIO_PIN_POR_DISABLE 97
129#define PISTACHIO_PIN_RESETN 98
130
131#define MFIO_PIN_DESC(p) PINCTRL_PIN(PISTACHIO_PIN_MFIO(p), "mfio" #p)
132
133static const struct pinctrl_pin_desc pistachio_pins[] = {
134 MFIO_PIN_DESC(0),
135 MFIO_PIN_DESC(1),
136 MFIO_PIN_DESC(2),
137 MFIO_PIN_DESC(3),
138 MFIO_PIN_DESC(4),
139 MFIO_PIN_DESC(5),
140 MFIO_PIN_DESC(6),
141 MFIO_PIN_DESC(7),
142 MFIO_PIN_DESC(8),
143 MFIO_PIN_DESC(9),
144 MFIO_PIN_DESC(10),
145 MFIO_PIN_DESC(11),
146 MFIO_PIN_DESC(12),
147 MFIO_PIN_DESC(13),
148 MFIO_PIN_DESC(14),
149 MFIO_PIN_DESC(15),
150 MFIO_PIN_DESC(16),
151 MFIO_PIN_DESC(17),
152 MFIO_PIN_DESC(18),
153 MFIO_PIN_DESC(19),
154 MFIO_PIN_DESC(20),
155 MFIO_PIN_DESC(21),
156 MFIO_PIN_DESC(22),
157 MFIO_PIN_DESC(23),
158 MFIO_PIN_DESC(24),
159 MFIO_PIN_DESC(25),
160 MFIO_PIN_DESC(26),
161 MFIO_PIN_DESC(27),
162 MFIO_PIN_DESC(28),
163 MFIO_PIN_DESC(29),
164 MFIO_PIN_DESC(30),
165 MFIO_PIN_DESC(31),
166 MFIO_PIN_DESC(32),
167 MFIO_PIN_DESC(33),
168 MFIO_PIN_DESC(34),
169 MFIO_PIN_DESC(35),
170 MFIO_PIN_DESC(36),
171 MFIO_PIN_DESC(37),
172 MFIO_PIN_DESC(38),
173 MFIO_PIN_DESC(39),
174 MFIO_PIN_DESC(40),
175 MFIO_PIN_DESC(41),
176 MFIO_PIN_DESC(42),
177 MFIO_PIN_DESC(43),
178 MFIO_PIN_DESC(44),
179 MFIO_PIN_DESC(45),
180 MFIO_PIN_DESC(46),
181 MFIO_PIN_DESC(47),
182 MFIO_PIN_DESC(48),
183 MFIO_PIN_DESC(49),
184 MFIO_PIN_DESC(50),
185 MFIO_PIN_DESC(51),
186 MFIO_PIN_DESC(52),
187 MFIO_PIN_DESC(53),
188 MFIO_PIN_DESC(54),
189 MFIO_PIN_DESC(55),
190 MFIO_PIN_DESC(56),
191 MFIO_PIN_DESC(57),
192 MFIO_PIN_DESC(58),
193 MFIO_PIN_DESC(59),
194 MFIO_PIN_DESC(60),
195 MFIO_PIN_DESC(61),
196 MFIO_PIN_DESC(62),
197 MFIO_PIN_DESC(63),
198 MFIO_PIN_DESC(64),
199 MFIO_PIN_DESC(65),
200 MFIO_PIN_DESC(66),
201 MFIO_PIN_DESC(67),
202 MFIO_PIN_DESC(68),
203 MFIO_PIN_DESC(69),
204 MFIO_PIN_DESC(70),
205 MFIO_PIN_DESC(71),
206 MFIO_PIN_DESC(72),
207 MFIO_PIN_DESC(73),
208 MFIO_PIN_DESC(74),
209 MFIO_PIN_DESC(75),
210 MFIO_PIN_DESC(76),
211 MFIO_PIN_DESC(77),
212 MFIO_PIN_DESC(78),
213 MFIO_PIN_DESC(79),
214 MFIO_PIN_DESC(80),
215 MFIO_PIN_DESC(81),
216 MFIO_PIN_DESC(82),
217 MFIO_PIN_DESC(83),
218 MFIO_PIN_DESC(84),
219 MFIO_PIN_DESC(85),
220 MFIO_PIN_DESC(86),
221 MFIO_PIN_DESC(87),
222 MFIO_PIN_DESC(88),
223 MFIO_PIN_DESC(89),
224 PINCTRL_PIN(PISTACHIO_PIN_TCK, "tck"),
225 PINCTRL_PIN(PISTACHIO_PIN_TRSTN, "trstn"),
226 PINCTRL_PIN(PISTACHIO_PIN_TDI, "tdi"),
227 PINCTRL_PIN(PISTACHIO_PIN_TMS, "tms"),
228 PINCTRL_PIN(PISTACHIO_PIN_TDO, "tdo"),
229 PINCTRL_PIN(PISTACHIO_PIN_JTAG_COMPLY, "jtag_comply"),
230 PINCTRL_PIN(PISTACHIO_PIN_SAFE_MODE, "safe_mode"),
231 PINCTRL_PIN(PISTACHIO_PIN_POR_DISABLE, "por_disable"),
232 PINCTRL_PIN(PISTACHIO_PIN_RESETN, "resetn"),
233};
234
235static const char * const pistachio_spim0_groups[] = {
236 "mfio1", "mfio2", "mfio8", "mfio9", "mfio10", "mfio28", "mfio29",
237 "mfio30", "mfio55", "mfio56", "mfio57",
238};
239
240static const char * const pistachio_spim1_groups[] = {
241 "mfio0", "mfio1", "mfio2", "mfio3", "mfio4", "mfio5", "mfio6",
242 "mfio7", "mfio31", "mfio55", "mfio56", "mfio57", "mfio58",
243};
244
245static const char * const pistachio_spis_groups[] = {
246 "mfio11", "mfio12", "mfio13", "mfio14",
247};
248
249static const char *const pistachio_sdhost_groups[] = {
250 "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
251 "mfio21", "mfio22", "mfio23", "mfio24", "mfio25", "mfio26",
252 "mfio27",
253};
254
255static const char * const pistachio_i2c0_groups[] = {
256 "mfio28", "mfio29",
257};
258
259static const char * const pistachio_i2c1_groups[] = {
260 "mfio30", "mfio31",
261};
262
263static const char * const pistachio_i2c2_groups[] = {
264 "mfio32", "mfio33",
265};
266
267static const char * const pistachio_i2c3_groups[] = {
268 "mfio34", "mfio35",
269};
270
271static const char * const pistachio_audio_clk_in_groups[] = {
272 "mfio36",
273};
274
275static const char * const pistachio_i2s_out_groups[] = {
276 "mfio36", "mfio37", "mfio38", "mfio39", "mfio40", "mfio41",
277 "mfio42", "mfio43", "mfio44",
278};
279
280static const char * const pistachio_debug_raw_cca_ind_groups[] = {
281 "mfio37",
282};
283
284static const char * const pistachio_debug_ed_sec20_cca_ind_groups[] = {
285 "mfio38",
286};
287
288static const char * const pistachio_debug_ed_sec40_cca_ind_groups[] = {
289 "mfio39",
290};
291
292static const char * const pistachio_debug_agc_done_0_groups[] = {
293 "mfio40",
294};
295
296static const char * const pistachio_debug_agc_done_1_groups[] = {
297 "mfio41",
298};
299
300static const char * const pistachio_debug_ed_cca_ind_groups[] = {
301 "mfio42",
302};
303
304static const char * const pistachio_debug_s2l_done_groups[] = {
305 "mfio43",
306};
307
308static const char * const pistachio_i2s_dac_clk_groups[] = {
309 "mfio45",
310};
311
312static const char * const pistachio_audio_sync_groups[] = {
313 "mfio45",
314};
315
316static const char * const pistachio_audio_trigger_groups[] = {
317 "mfio46",
318};
319
320static const char * const pistachio_i2s_in_groups[] = {
321 "mfio47", "mfio48", "mfio49", "mfio50", "mfio51", "mfio52",
322 "mfio53", "mfio54",
323};
324
325static const char * const pistachio_uart0_groups[] = {
326 "mfio55", "mfio56", "mfio57", "mfio58",
327};
328
329static const char * const pistachio_uart1_groups[] = {
330 "mfio59", "mfio60", "mfio1", "mfio2",
331};
332
333static const char * const pistachio_spdif_out_groups[] = {
334 "mfio61",
335};
336
337static const char * const pistachio_spdif_in_groups[] = {
338 "mfio62", "mfio54",
339};
340static const int pistachio_spdif_in_scenarios[] = {
341 PISTACHIO_PIN_MFIO(62),
342 PISTACHIO_PIN_MFIO(54),
343};
344
345static const char * const pistachio_eth_groups[] = {
346 "mfio63", "mfio64", "mfio65", "mfio66", "mfio67", "mfio68",
347 "mfio69", "mfio70", "mfio71",
348};
349
350static const char * const pistachio_ir_groups[] = {
351 "mfio72",
352};
353
354static const char * const pistachio_pwmpdm_groups[] = {
355 "mfio73", "mfio74", "mfio75", "mfio76",
356};
357
358static const char * const pistachio_mips_trace_clk_groups[] = {
359 "mfio15", "mfio63", "mfio73",
360};
361
362static const char * const pistachio_mips_trace_dint_groups[] = {
363 "mfio16", "mfio64", "mfio74",
364};
365static const int pistachio_mips_trace_dint_scenarios[] = {
366 PISTACHIO_PIN_MFIO(16),
367 PISTACHIO_PIN_MFIO(64),
368 PISTACHIO_PIN_MFIO(74),
369};
370
371static const char * const pistachio_mips_trace_trigout_groups[] = {
372 "mfio17", "mfio65", "mfio75",
373};
374
375static const char * const pistachio_mips_trace_trigin_groups[] = {
376 "mfio18", "mfio66", "mfio76",
377};
378static const int pistachio_mips_trace_trigin_scenarios[] = {
379 PISTACHIO_PIN_MFIO(18),
380 PISTACHIO_PIN_MFIO(66),
381 PISTACHIO_PIN_MFIO(76),
382};
383
384static const char * const pistachio_mips_trace_dm_groups[] = {
385 "mfio19", "mfio67", "mfio77",
386};
387
388static const char * const pistachio_mips_probe_n_groups[] = {
389 "mfio20", "mfio68", "mfio78",
390};
391static const int pistachio_mips_probe_n_scenarios[] = {
392 PISTACHIO_PIN_MFIO(20),
393 PISTACHIO_PIN_MFIO(68),
394 PISTACHIO_PIN_MFIO(78),
395};
396
397static const char * const pistachio_mips_trace_data_groups[] = {
398 "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
399 "mfio21", "mfio22", "mfio63", "mfio64", "mfio65", "mfio66",
400 "mfio67", "mfio68", "mfio69", "mfio70", "mfio79", "mfio80",
401 "mfio81", "mfio82", "mfio83", "mfio84", "mfio85", "mfio86",
402};
403
404static const char * const pistachio_sram_debug_groups[] = {
405 "mfio73", "mfio74",
406};
407
408static const char * const pistachio_rom_debug_groups[] = {
409 "mfio75", "mfio76",
410};
411
412static const char * const pistachio_rpu_debug_groups[] = {
413 "mfio77", "mfio78",
414};
415
416static const char * const pistachio_mips_debug_groups[] = {
417 "mfio79", "mfio80",
418};
419
420static const char * const pistachio_eth_debug_groups[] = {
421 "mfio81", "mfio82",
422};
423
424static const char * const pistachio_usb_debug_groups[] = {
425 "mfio83", "mfio84",
426};
427
428static const char * const pistachio_sdhost_debug_groups[] = {
429 "mfio85", "mfio86",
430};
431
432static const char * const pistachio_socif_debug_groups[] = {
433 "mfio87", "mfio88",
434};
435
436static const char * const pistachio_mdc_debug_groups[] = {
437 "mfio77", "mfio78",
438};
439
440static const char * const pistachio_ddr_debug_groups[] = {
441 "mfio79", "mfio80",
442};
443
444static const char * const pistachio_dreq0_groups[] = {
445 "mfio81",
446};
447
448static const char * const pistachio_dreq1_groups[] = {
449 "mfio82",
450};
451
452static const char * const pistachio_dreq2_groups[] = {
453 "mfio87",
454};
455
456static const char * const pistachio_dreq3_groups[] = {
457 "mfio88",
458};
459
460static const char * const pistachio_dreq4_groups[] = {
461 "mfio89",
462};
463
464static const char * const pistachio_dreq5_groups[] = {
465 "mfio89",
466};
467
468static const char * const pistachio_mips_pll_lock_groups[] = {
469 "mfio83",
470};
471
472static const char * const pistachio_sys_pll_lock_groups[] = {
473 "mfio84",
474};
475
476static const char * const pistachio_wifi_pll_lock_groups[] = {
477 "mfio85",
478};
479
480static const char * const pistachio_bt_pll_lock_groups[] = {
481 "mfio86",
482};
483
484static const char * const pistachio_rpu_v_pll_lock_groups[] = {
485 "mfio87",
486};
487
488static const char * const pistachio_rpu_l_pll_lock_groups[] = {
489 "mfio88",
490};
491
492static const char * const pistachio_audio_pll_lock_groups[] = {
493 "mfio89",
494};
495
496#define FUNCTION(_name) \
497 { \
498 .name = #_name, \
499 .groups = pistachio_##_name##_groups, \
500 .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
501 }
502
503#define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \
504 { \
505 .name = #_name, \
506 .groups = pistachio_##_name##_groups, \
507 .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
508 .scenarios = pistachio_##_name##_scenarios, \
509 .nscenarios = ARRAY_SIZE(pistachio_##_name##_scenarios),\
510 .scenario_reg = _reg, \
511 .scenario_shift = _shift, \
512 .scenario_mask = _mask, \
513 }
514
515enum pistachio_mux_option {
516 PISTACHIO_FUNCTION_NONE = -1,
517 PISTACHIO_FUNCTION_SPIM0,
518 PISTACHIO_FUNCTION_SPIM1,
519 PISTACHIO_FUNCTION_SPIS,
520 PISTACHIO_FUNCTION_SDHOST,
521 PISTACHIO_FUNCTION_I2C0,
522 PISTACHIO_FUNCTION_I2C1,
523 PISTACHIO_FUNCTION_I2C2,
524 PISTACHIO_FUNCTION_I2C3,
525 PISTACHIO_FUNCTION_AUDIO_CLK_IN,
526 PISTACHIO_FUNCTION_I2S_OUT,
527 PISTACHIO_FUNCTION_I2S_DAC_CLK,
528 PISTACHIO_FUNCTION_AUDIO_SYNC,
529 PISTACHIO_FUNCTION_AUDIO_TRIGGER,
530 PISTACHIO_FUNCTION_I2S_IN,
531 PISTACHIO_FUNCTION_UART0,
532 PISTACHIO_FUNCTION_UART1,
533 PISTACHIO_FUNCTION_SPDIF_OUT,
534 PISTACHIO_FUNCTION_SPDIF_IN,
535 PISTACHIO_FUNCTION_ETH,
536 PISTACHIO_FUNCTION_IR,
537 PISTACHIO_FUNCTION_PWMPDM,
538 PISTACHIO_FUNCTION_MIPS_TRACE_CLK,
539 PISTACHIO_FUNCTION_MIPS_TRACE_DINT,
540 PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT,
541 PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN,
542 PISTACHIO_FUNCTION_MIPS_TRACE_DM,
543 PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N,
544 PISTACHIO_FUNCTION_MIPS_TRACE_DATA,
545 PISTACHIO_FUNCTION_SRAM_DEBUG,
546 PISTACHIO_FUNCTION_ROM_DEBUG,
547 PISTACHIO_FUNCTION_RPU_DEBUG,
548 PISTACHIO_FUNCTION_MIPS_DEBUG,
549 PISTACHIO_FUNCTION_ETH_DEBUG,
550 PISTACHIO_FUNCTION_USB_DEBUG,
551 PISTACHIO_FUNCTION_SDHOST_DEBUG,
552 PISTACHIO_FUNCTION_SOCIF_DEBUG,
553 PISTACHIO_FUNCTION_MDC_DEBUG,
554 PISTACHIO_FUNCTION_DDR_DEBUG,
555 PISTACHIO_FUNCTION_DREQ0,
556 PISTACHIO_FUNCTION_DREQ1,
557 PISTACHIO_FUNCTION_DREQ2,
558 PISTACHIO_FUNCTION_DREQ3,
559 PISTACHIO_FUNCTION_DREQ4,
560 PISTACHIO_FUNCTION_DREQ5,
561 PISTACHIO_FUNCTION_MIPS_PLL_LOCK,
562 PISTACHIO_FUNCTION_SYS_PLL_LOCK,
563 PISTACHIO_FUNCTION_WIFI_PLL_LOCK,
564 PISTACHIO_FUNCTION_BT_PLL_LOCK,
565 PISTACHIO_FUNCTION_RPU_V_PLL_LOCK,
566 PISTACHIO_FUNCTION_RPU_L_PLL_LOCK,
567 PISTACHIO_FUNCTION_AUDIO_PLL_LOCK,
568 PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND,
569 PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND,
570 PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND,
571 PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0,
572 PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1,
573 PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND,
574 PISTACHIO_FUNCTION_DEBUG_S2L_DONE,
575};
576
577static const struct pistachio_function pistachio_functions[] = {
578 FUNCTION(spim0),
579 FUNCTION(spim1),
580 FUNCTION(spis),
581 FUNCTION(sdhost),
582 FUNCTION(i2c0),
583 FUNCTION(i2c1),
584 FUNCTION(i2c2),
585 FUNCTION(i2c3),
586 FUNCTION(audio_clk_in),
587 FUNCTION(i2s_out),
588 FUNCTION(i2s_dac_clk),
589 FUNCTION(audio_sync),
590 FUNCTION(audio_trigger),
591 FUNCTION(i2s_in),
592 FUNCTION(uart0),
593 FUNCTION(uart1),
594 FUNCTION(spdif_out),
595 FUNCTION_SCENARIO(spdif_in, PADS_SCENARIO_SELECT, 0, 0x1),
596 FUNCTION(eth),
597 FUNCTION(ir),
598 FUNCTION(pwmpdm),
599 FUNCTION(mips_trace_clk),
600 FUNCTION_SCENARIO(mips_trace_dint, PADS_SCENARIO_SELECT, 1, 0x3),
601 FUNCTION(mips_trace_trigout),
602 FUNCTION_SCENARIO(mips_trace_trigin, PADS_SCENARIO_SELECT, 3, 0x3),
603 FUNCTION(mips_trace_dm),
604 FUNCTION_SCENARIO(mips_probe_n, PADS_SCENARIO_SELECT, 5, 0x3),
605 FUNCTION(mips_trace_data),
606 FUNCTION(sram_debug),
607 FUNCTION(rom_debug),
608 FUNCTION(rpu_debug),
609 FUNCTION(mips_debug),
610 FUNCTION(eth_debug),
611 FUNCTION(usb_debug),
612 FUNCTION(sdhost_debug),
613 FUNCTION(socif_debug),
614 FUNCTION(mdc_debug),
615 FUNCTION(ddr_debug),
616 FUNCTION(dreq0),
617 FUNCTION(dreq1),
618 FUNCTION(dreq2),
619 FUNCTION(dreq3),
620 FUNCTION(dreq4),
621 FUNCTION(dreq5),
622 FUNCTION(mips_pll_lock),
623 FUNCTION(sys_pll_lock),
624 FUNCTION(wifi_pll_lock),
625 FUNCTION(bt_pll_lock),
626 FUNCTION(rpu_v_pll_lock),
627 FUNCTION(rpu_l_pll_lock),
628 FUNCTION(audio_pll_lock),
629 FUNCTION(debug_raw_cca_ind),
630 FUNCTION(debug_ed_sec20_cca_ind),
631 FUNCTION(debug_ed_sec40_cca_ind),
632 FUNCTION(debug_agc_done_0),
633 FUNCTION(debug_agc_done_1),
634 FUNCTION(debug_ed_cca_ind),
635 FUNCTION(debug_s2l_done),
636};
637
638#define PIN_GROUP(_pin, _name) \
639 { \
640 .name = #_name, \
641 .pin = PISTACHIO_PIN_##_pin, \
642 .mux_option = { \
643 PISTACHIO_FUNCTION_NONE, \
644 PISTACHIO_FUNCTION_NONE, \
645 PISTACHIO_FUNCTION_NONE, \
646 }, \
647 .mux_reg = -1, \
648 .mux_shift = -1, \
649 .mux_mask = -1, \
650 }
651
652#define MFIO_PIN_GROUP(_pin, _func) \
653 { \
654 .name = "mfio" #_pin, \
655 .pin = PISTACHIO_PIN_MFIO(_pin), \
656 .mux_option = { \
657 PISTACHIO_FUNCTION_##_func, \
658 PISTACHIO_FUNCTION_NONE, \
659 PISTACHIO_FUNCTION_NONE, \
660 }, \
661 .mux_reg = -1, \
662 .mux_shift = -1, \
663 .mux_mask = -1, \
664 }
665
666#define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \
667 { \
668 .name = "mfio" #_pin, \
669 .pin = PISTACHIO_PIN_MFIO(_pin), \
670 .mux_option = { \
671 PISTACHIO_FUNCTION_##_f0, \
672 PISTACHIO_FUNCTION_##_f1, \
673 PISTACHIO_FUNCTION_##_f2, \
674 }, \
675 .mux_reg = _reg, \
676 .mux_shift = _shift, \
677 .mux_mask = _mask, \
678 }
679
680static const struct pistachio_pin_group pistachio_groups[] = {
681 MFIO_PIN_GROUP(0, SPIM1),
682 MFIO_MUX_PIN_GROUP(1, SPIM1, SPIM0, UART1,
683 PADS_FUNCTION_SELECT0, 0, 0x3),
684 MFIO_MUX_PIN_GROUP(2, SPIM1, SPIM0, UART1,
685 PADS_FUNCTION_SELECT0, 2, 0x3),
686 MFIO_PIN_GROUP(3, SPIM1),
687 MFIO_PIN_GROUP(4, SPIM1),
688 MFIO_PIN_GROUP(5, SPIM1),
689 MFIO_PIN_GROUP(6, SPIM1),
690 MFIO_PIN_GROUP(7, SPIM1),
691 MFIO_PIN_GROUP(8, SPIM0),
692 MFIO_PIN_GROUP(9, SPIM0),
693 MFIO_PIN_GROUP(10, SPIM0),
694 MFIO_PIN_GROUP(11, SPIS),
695 MFIO_PIN_GROUP(12, SPIS),
696 MFIO_PIN_GROUP(13, SPIS),
697 MFIO_PIN_GROUP(14, SPIS),
698 MFIO_MUX_PIN_GROUP(15, SDHOST, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
699 PADS_FUNCTION_SELECT0, 4, 0x3),
700 MFIO_MUX_PIN_GROUP(16, SDHOST, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
701 PADS_FUNCTION_SELECT0, 6, 0x3),
702 MFIO_MUX_PIN_GROUP(17, SDHOST, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
703 PADS_FUNCTION_SELECT0, 8, 0x3),
704 MFIO_MUX_PIN_GROUP(18, SDHOST, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
705 PADS_FUNCTION_SELECT0, 10, 0x3),
706 MFIO_MUX_PIN_GROUP(19, SDHOST, MIPS_TRACE_DM, MIPS_TRACE_DATA,
707 PADS_FUNCTION_SELECT0, 12, 0x3),
708 MFIO_MUX_PIN_GROUP(20, SDHOST, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
709 PADS_FUNCTION_SELECT0, 14, 0x3),
710 MFIO_MUX_PIN_GROUP(21, SDHOST, NONE, MIPS_TRACE_DATA,
711 PADS_FUNCTION_SELECT0, 16, 0x3),
712 MFIO_MUX_PIN_GROUP(22, SDHOST, NONE, MIPS_TRACE_DATA,
713 PADS_FUNCTION_SELECT0, 18, 0x3),
714 MFIO_PIN_GROUP(23, SDHOST),
715 MFIO_PIN_GROUP(24, SDHOST),
716 MFIO_PIN_GROUP(25, SDHOST),
717 MFIO_PIN_GROUP(26, SDHOST),
718 MFIO_PIN_GROUP(27, SDHOST),
719 MFIO_MUX_PIN_GROUP(28, I2C0, SPIM0, NONE,
720 PADS_FUNCTION_SELECT0, 20, 0x1),
721 MFIO_MUX_PIN_GROUP(29, I2C0, SPIM0, NONE,
722 PADS_FUNCTION_SELECT0, 21, 0x1),
723 MFIO_MUX_PIN_GROUP(30, I2C1, SPIM0, NONE,
724 PADS_FUNCTION_SELECT0, 22, 0x1),
725 MFIO_MUX_PIN_GROUP(31, I2C1, SPIM1, NONE,
726 PADS_FUNCTION_SELECT0, 23, 0x1),
727 MFIO_PIN_GROUP(32, I2C2),
728 MFIO_PIN_GROUP(33, I2C2),
729 MFIO_PIN_GROUP(34, I2C3),
730 MFIO_PIN_GROUP(35, I2C3),
731 MFIO_MUX_PIN_GROUP(36, I2S_OUT, AUDIO_CLK_IN, NONE,
732 PADS_FUNCTION_SELECT0, 24, 0x1),
733 MFIO_MUX_PIN_GROUP(37, I2S_OUT, DEBUG_RAW_CCA_IND, NONE,
734 PADS_FUNCTION_SELECT0, 25, 0x1),
735 MFIO_MUX_PIN_GROUP(38, I2S_OUT, DEBUG_ED_SEC20_CCA_IND, NONE,
736 PADS_FUNCTION_SELECT0, 26, 0x1),
737 MFIO_MUX_PIN_GROUP(39, I2S_OUT, DEBUG_ED_SEC40_CCA_IND, NONE,
738 PADS_FUNCTION_SELECT0, 27, 0x1),
739 MFIO_MUX_PIN_GROUP(40, I2S_OUT, DEBUG_AGC_DONE_0, NONE,
740 PADS_FUNCTION_SELECT0, 28, 0x1),
741 MFIO_MUX_PIN_GROUP(41, I2S_OUT, DEBUG_AGC_DONE_1, NONE,
742 PADS_FUNCTION_SELECT0, 29, 0x1),
743 MFIO_MUX_PIN_GROUP(42, I2S_OUT, DEBUG_ED_CCA_IND, NONE,
744 PADS_FUNCTION_SELECT0, 30, 0x1),
745 MFIO_MUX_PIN_GROUP(43, I2S_OUT, DEBUG_S2L_DONE, NONE,
746 PADS_FUNCTION_SELECT0, 31, 0x1),
747 MFIO_PIN_GROUP(44, I2S_OUT),
748 MFIO_MUX_PIN_GROUP(45, I2S_DAC_CLK, AUDIO_SYNC, NONE,
749 PADS_FUNCTION_SELECT1, 0, 0x1),
750 MFIO_PIN_GROUP(46, AUDIO_TRIGGER),
751 MFIO_PIN_GROUP(47, I2S_IN),
752 MFIO_PIN_GROUP(48, I2S_IN),
753 MFIO_PIN_GROUP(49, I2S_IN),
754 MFIO_PIN_GROUP(50, I2S_IN),
755 MFIO_PIN_GROUP(51, I2S_IN),
756 MFIO_PIN_GROUP(52, I2S_IN),
757 MFIO_PIN_GROUP(53, I2S_IN),
758 MFIO_MUX_PIN_GROUP(54, I2S_IN, NONE, SPDIF_IN,
759 PADS_FUNCTION_SELECT1, 1, 0x3),
760 MFIO_MUX_PIN_GROUP(55, UART0, SPIM0, SPIM1,
761 PADS_FUNCTION_SELECT1, 3, 0x3),
762 MFIO_MUX_PIN_GROUP(56, UART0, SPIM0, SPIM1,
763 PADS_FUNCTION_SELECT1, 5, 0x3),
764 MFIO_MUX_PIN_GROUP(57, UART0, SPIM0, SPIM1,
765 PADS_FUNCTION_SELECT1, 7, 0x3),
766 MFIO_MUX_PIN_GROUP(58, UART0, SPIM1, NONE,
767 PADS_FUNCTION_SELECT1, 9, 0x1),
768 MFIO_PIN_GROUP(59, UART1),
769 MFIO_PIN_GROUP(60, UART1),
770 MFIO_PIN_GROUP(61, SPDIF_OUT),
771 MFIO_PIN_GROUP(62, SPDIF_IN),
772 MFIO_MUX_PIN_GROUP(63, ETH, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
773 PADS_FUNCTION_SELECT1, 10, 0x3),
774 MFIO_MUX_PIN_GROUP(64, ETH, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
775 PADS_FUNCTION_SELECT1, 12, 0x3),
776 MFIO_MUX_PIN_GROUP(65, ETH, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
777 PADS_FUNCTION_SELECT1, 14, 0x3),
778 MFIO_MUX_PIN_GROUP(66, ETH, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
779 PADS_FUNCTION_SELECT1, 16, 0x3),
780 MFIO_MUX_PIN_GROUP(67, ETH, MIPS_TRACE_DM, MIPS_TRACE_DATA,
781 PADS_FUNCTION_SELECT1, 18, 0x3),
782 MFIO_MUX_PIN_GROUP(68, ETH, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
783 PADS_FUNCTION_SELECT1, 20, 0x3),
784 MFIO_MUX_PIN_GROUP(69, ETH, NONE, MIPS_TRACE_DATA,
785 PADS_FUNCTION_SELECT1, 22, 0x3),
786 MFIO_MUX_PIN_GROUP(70, ETH, NONE, MIPS_TRACE_DATA,
787 PADS_FUNCTION_SELECT1, 24, 0x3),
788 MFIO_PIN_GROUP(71, ETH),
789 MFIO_PIN_GROUP(72, IR),
790 MFIO_MUX_PIN_GROUP(73, PWMPDM, MIPS_TRACE_CLK, SRAM_DEBUG,
791 PADS_FUNCTION_SELECT1, 26, 0x3),
792 MFIO_MUX_PIN_GROUP(74, PWMPDM, MIPS_TRACE_DINT, SRAM_DEBUG,
793 PADS_FUNCTION_SELECT1, 28, 0x3),
794 MFIO_MUX_PIN_GROUP(75, PWMPDM, MIPS_TRACE_TRIGOUT, ROM_DEBUG,
795 PADS_FUNCTION_SELECT1, 30, 0x3),
796 MFIO_MUX_PIN_GROUP(76, PWMPDM, MIPS_TRACE_TRIGIN, ROM_DEBUG,
797 PADS_FUNCTION_SELECT2, 0, 0x3),
798 MFIO_MUX_PIN_GROUP(77, MDC_DEBUG, MIPS_TRACE_DM, RPU_DEBUG,
799 PADS_FUNCTION_SELECT2, 2, 0x3),
800 MFIO_MUX_PIN_GROUP(78, MDC_DEBUG, MIPS_TRACE_PROBE_N, RPU_DEBUG,
801 PADS_FUNCTION_SELECT2, 4, 0x3),
802 MFIO_MUX_PIN_GROUP(79, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
803 PADS_FUNCTION_SELECT2, 6, 0x3),
804 MFIO_MUX_PIN_GROUP(80, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
805 PADS_FUNCTION_SELECT2, 8, 0x3),
806 MFIO_MUX_PIN_GROUP(81, DREQ0, MIPS_TRACE_DATA, ETH_DEBUG,
807 PADS_FUNCTION_SELECT2, 10, 0x3),
808 MFIO_MUX_PIN_GROUP(82, DREQ1, MIPS_TRACE_DATA, ETH_DEBUG,
809 PADS_FUNCTION_SELECT2, 12, 0x3),
810 MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
811 PADS_FUNCTION_SELECT2, 14, 0x3),
812 MFIO_MUX_PIN_GROUP(84, SYS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
813 PADS_FUNCTION_SELECT2, 16, 0x3),
814 MFIO_MUX_PIN_GROUP(85, WIFI_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
815 PADS_FUNCTION_SELECT2, 18, 0x3),
816 MFIO_MUX_PIN_GROUP(86, BT_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
817 PADS_FUNCTION_SELECT2, 20, 0x3),
818 MFIO_MUX_PIN_GROUP(87, RPU_V_PLL_LOCK, DREQ2, SOCIF_DEBUG,
819 PADS_FUNCTION_SELECT2, 22, 0x3),
820 MFIO_MUX_PIN_GROUP(88, RPU_L_PLL_LOCK, DREQ3, SOCIF_DEBUG,
821 PADS_FUNCTION_SELECT2, 24, 0x3),
822 MFIO_MUX_PIN_GROUP(89, AUDIO_PLL_LOCK, DREQ4, DREQ5,
823 PADS_FUNCTION_SELECT2, 26, 0x3),
824 PIN_GROUP(TCK, "tck"),
825 PIN_GROUP(TRSTN, "trstn"),
826 PIN_GROUP(TDI, "tdi"),
827 PIN_GROUP(TMS, "tms"),
828 PIN_GROUP(TDO, "tdo"),
829 PIN_GROUP(JTAG_COMPLY, "jtag_comply"),
830 PIN_GROUP(SAFE_MODE, "safe_mode"),
831 PIN_GROUP(POR_DISABLE, "por_disable"),
832 PIN_GROUP(RESETN, "resetn"),
833};
834
835static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg)
836{
837 return readl(pctl->base + reg);
838}
839
840static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
841{
842 writel(val, pctl->base + reg);
843}
844
845static inline struct pistachio_gpio_bank *gc_to_bank(struct gpio_chip *gc)
846{
847 return container_of(gc, struct pistachio_gpio_bank, gpio_chip);
848}
849
850static inline struct pistachio_gpio_bank *irqd_to_bank(struct irq_data *d)
851{
852 return gc_to_bank(irq_data_get_irq_chip_data(d));
853}
854
855static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg)
856{
857 return readl(bank->base + reg);
858}
859
860static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
861 u32 reg)
862{
863 writel(val, bank->base + reg);
864}
865
866static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank,
867 u32 reg, unsigned int bit, u32 val)
868{
869 /*
870 * For most of the GPIO registers, bit 16 + X must be set in order to
871 * write bit X.
872 */
873 gpio_writel(bank, (0x10000 | val) << bit, reg);
874}
875
876static inline void gpio_enable(struct pistachio_gpio_bank *bank,
877 unsigned offset)
878{
879 gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1);
880}
881
882static inline void gpio_disable(struct pistachio_gpio_bank *bank,
883 unsigned offset)
884{
885 gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0);
886}
887
888static int pistachio_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
889{
890 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
891
892 return pctl->ngroups;
893}
894
895static const char *pistachio_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
896 unsigned group)
897{
898 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
899
900 return pctl->groups[group].name;
901}
902
903static int pistachio_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
904 unsigned group,
905 const unsigned **pins,
906 unsigned *num_pins)
907{
908 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
909
910 *pins = &pctl->groups[group].pin;
911 *num_pins = 1;
912
913 return 0;
914}
915
916static const struct pinctrl_ops pistachio_pinctrl_ops = {
917 .get_groups_count = pistachio_pinctrl_get_groups_count,
918 .get_group_name = pistachio_pinctrl_get_group_name,
919 .get_group_pins = pistachio_pinctrl_get_group_pins,
920 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
921 .dt_free_map = pinctrl_utils_dt_free_map,
922};
923
924static int pistachio_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
925{
926 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
927
928 return pctl->nfunctions;
929}
930
931static const char *
932pistachio_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
933{
934 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
935
936 return pctl->functions[func].name;
937}
938
939static int pistachio_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
940 unsigned func,
941 const char * const **groups,
942 unsigned * const num_groups)
943{
944 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
945
946 *groups = pctl->functions[func].groups;
947 *num_groups = pctl->functions[func].ngroups;
948
949 return 0;
950}
951
952static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev,
953 unsigned func, unsigned group)
954{
955 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
956 const struct pistachio_pin_group *pg = &pctl->groups[group];
957 const struct pistachio_function *pf = &pctl->functions[func];
958 struct pinctrl_gpio_range *range;
959 unsigned int i;
960 u32 val;
961
962 if (pg->mux_reg > 0) {
963 for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) {
964 if (pg->mux_option[i] == func)
965 break;
966 }
967 if (i == ARRAY_SIZE(pg->mux_option)) {
968 dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",
969 group, func);
970 return -EINVAL;
971 }
972
973 val = pctl_readl(pctl, pg->mux_reg);
974 val &= ~(pg->mux_mask << pg->mux_shift);
975 val |= i << pg->mux_shift;
976 pctl_writel(pctl, val, pg->mux_reg);
977
978 if (pf->scenarios) {
979 for (i = 0; i < pf->nscenarios; i++) {
980 if (pf->scenarios[i] == group)
981 break;
982 }
983 if (WARN_ON(i == pf->nscenarios))
984 return -EINVAL;
985
986 val = pctl_readl(pctl, pf->scenario_reg);
987 val &= ~(pf->scenario_mask << pf->scenario_shift);
988 val |= i << pf->scenario_shift;
989 pctl_writel(pctl, val, pf->scenario_reg);
990 }
991 }
992
993 range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);
994 if (range)
995 gpio_disable(gc_to_bank(range->gc), pg->pin - range->pin_base);
996
997 return 0;
998}
999
1000static const struct pinmux_ops pistachio_pinmux_ops = {
1001 .get_functions_count = pistachio_pinmux_get_functions_count,
1002 .get_function_name = pistachio_pinmux_get_function_name,
1003 .get_function_groups = pistachio_pinmux_get_function_groups,
1004 .set_mux = pistachio_pinmux_enable,
1005};
1006
1007static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
1008 unsigned long *config)
1009{
1010 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1011 enum pin_config_param param = pinconf_to_config_param(*config);
1012 u32 val, arg;
1013
1014 switch (param) {
1015 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1016 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1017 arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
1018 break;
1019 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1020 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1021 PADS_PU_PD_SHIFT(pin);
1022 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
1023 break;
1024 case PIN_CONFIG_BIAS_PULL_UP:
1025 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1026 PADS_PU_PD_SHIFT(pin);
1027 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
1028 break;
1029 case PIN_CONFIG_BIAS_PULL_DOWN:
1030 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1031 PADS_PU_PD_SHIFT(pin);
1032 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
1033 break;
1034 case PIN_CONFIG_BIAS_BUS_HOLD:
1035 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1036 PADS_PU_PD_SHIFT(pin);
1037 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
1038 break;
1039 case PIN_CONFIG_SLEW_RATE:
1040 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1041 arg = !!(val & PADS_SLEW_RATE_BIT(pin));
1042 break;
1043 case PIN_CONFIG_DRIVE_STRENGTH:
1044 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
1045 PADS_DRIVE_STRENGTH_SHIFT(pin);
1046 switch (val & PADS_DRIVE_STRENGTH_MASK) {
1047 case PADS_DRIVE_STRENGTH_2MA:
1048 arg = 2;
1049 break;
1050 case PADS_DRIVE_STRENGTH_4MA:
1051 arg = 4;
1052 break;
1053 case PADS_DRIVE_STRENGTH_8MA:
1054 arg = 8;
1055 break;
1056 case PADS_DRIVE_STRENGTH_12MA:
1057 default:
1058 arg = 12;
1059 break;
1060 }
1061 break;
1062 default:
1063 dev_dbg(pctl->dev, "Property %u not supported\n", param);
1064 return -ENOTSUPP;
1065 }
1066
1067 *config = pinconf_to_config_packed(param, arg);
1068
1069 return 0;
1070}
1071
1072static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
1073 unsigned long *configs, unsigned num_configs)
1074{
1075 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1076 enum pin_config_param param;
1077 u32 drv, val, arg;
1078 unsigned int i;
1079
1080 for (i = 0; i < num_configs; i++) {
1081 param = pinconf_to_config_param(configs[i]);
1082 arg = pinconf_to_config_argument(configs[i]);
1083
1084 switch (param) {
1085 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1086 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1087 if (arg)
1088 val |= PADS_SCHMITT_EN_BIT(pin);
1089 else
1090 val &= ~PADS_SCHMITT_EN_BIT(pin);
1091 pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
1092 break;
1093 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1094 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1095 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1096 val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);
1097 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1098 break;
1099 case PIN_CONFIG_BIAS_PULL_UP:
1100 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1101 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1102 val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);
1103 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1104 break;
1105 case PIN_CONFIG_BIAS_PULL_DOWN:
1106 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1107 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1108 val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);
1109 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1110 break;
1111 case PIN_CONFIG_BIAS_BUS_HOLD:
1112 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1113 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1114 val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);
1115 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1116 break;
1117 case PIN_CONFIG_SLEW_RATE:
1118 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1119 if (arg)
1120 val |= PADS_SLEW_RATE_BIT(pin);
1121 else
1122 val &= ~PADS_SLEW_RATE_BIT(pin);
1123 pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
1124 break;
1125 case PIN_CONFIG_DRIVE_STRENGTH:
1126 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
1127 val &= ~(PADS_DRIVE_STRENGTH_MASK <<
1128 PADS_DRIVE_STRENGTH_SHIFT(pin));
1129 switch (arg) {
1130 case 2:
1131 drv = PADS_DRIVE_STRENGTH_2MA;
1132 break;
1133 case 4:
1134 drv = PADS_DRIVE_STRENGTH_4MA;
1135 break;
1136 case 8:
1137 drv = PADS_DRIVE_STRENGTH_8MA;
1138 break;
1139 case 12:
1140 drv = PADS_DRIVE_STRENGTH_12MA;
1141 break;
1142 default:
1143 dev_err(pctl->dev,
1144 "Drive strength %umA not supported\n",
1145 arg);
1146 return -EINVAL;
1147 }
1148 val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);
1149 pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));
1150 break;
1151 default:
1152 dev_err(pctl->dev, "Property %u not supported\n",
1153 param);
1154 return -ENOTSUPP;
1155 }
1156 }
1157
1158 return 0;
1159}
1160
1161static const struct pinconf_ops pistachio_pinconf_ops = {
1162 .pin_config_get = pistachio_pinconf_get,
1163 .pin_config_set = pistachio_pinconf_set,
1164 .is_generic = true,
1165};
1166
1167static struct pinctrl_desc pistachio_pinctrl_desc = {
1168 .name = "pistachio-pinctrl",
1169 .pctlops = &pistachio_pinctrl_ops,
1170 .pmxops = &pistachio_pinmux_ops,
1171 .confops = &pistachio_pinconf_ops,
1172};
1173
1174static int pistachio_gpio_request(struct gpio_chip *chip, unsigned offset)
1175{
1176 return pinctrl_request_gpio(chip->base + offset);
1177}
1178
1179static void pistachio_gpio_free(struct gpio_chip *chip, unsigned offset)
1180{
1181 pinctrl_free_gpio(chip->base + offset);
1182}
1183
1184static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1185{
1186 struct pistachio_gpio_bank *bank = gc_to_bank(chip);
1187
1188 return !(gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset));
1189}
1190
1191static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset)
1192{
1193 struct pistachio_gpio_bank *bank = gc_to_bank(chip);
1194 u32 reg;
1195
1196 if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
1197 reg = GPIO_OUTPUT;
1198 else
1199 reg = GPIO_INPUT;
1200
1201 return !!(gpio_readl(bank, reg) & BIT(offset));
1202}
1203
1204static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset,
1205 int value)
1206{
1207 struct pistachio_gpio_bank *bank = gc_to_bank(chip);
1208
1209 gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);
1210}
1211
1212static int pistachio_gpio_direction_input(struct gpio_chip *chip,
1213 unsigned offset)
1214{
1215 struct pistachio_gpio_bank *bank = gc_to_bank(chip);
1216
1217 gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0);
1218 gpio_enable(bank, offset);
1219
1220 return 0;
1221}
1222
1223static int pistachio_gpio_direction_output(struct gpio_chip *chip,
1224 unsigned offset, int value)
1225{
1226 struct pistachio_gpio_bank *bank = gc_to_bank(chip);
1227
1228 pistachio_gpio_set(chip, offset, value);
1229 gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1);
1230 gpio_enable(bank, offset);
1231
1232 return 0;
1233}
1234
1235static void pistachio_gpio_irq_ack(struct irq_data *data)
1236{
1237 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1238
1239 gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);
1240}
1241
1242static void pistachio_gpio_irq_mask(struct irq_data *data)
1243{
1244 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1245
1246 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);
1247}
1248
1249static void pistachio_gpio_irq_unmask(struct irq_data *data)
1250{
1251 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1252
1253 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);
1254}
1255
1256static unsigned int pistachio_gpio_irq_startup(struct irq_data *data)
1257{
1258 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1259
1260 pistachio_gpio_direction_input(chip, data->hwirq);
1261 pistachio_gpio_irq_unmask(data);
1262
1263 return 0;
1264}
1265
1266static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1267{
1268 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1269
1270 switch (type & IRQ_TYPE_SENSE_MASK) {
1271 case IRQ_TYPE_EDGE_RISING:
1272 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1273 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1274 GPIO_INTERRUPT_TYPE_EDGE);
1275 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1276 GPIO_INTERRUPT_EDGE_SINGLE);
1277 break;
1278 case IRQ_TYPE_EDGE_FALLING:
1279 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1280 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1281 GPIO_INTERRUPT_TYPE_EDGE);
1282 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1283 GPIO_INTERRUPT_EDGE_SINGLE);
1284 break;
1285 case IRQ_TYPE_EDGE_BOTH:
1286 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1287 GPIO_INTERRUPT_TYPE_EDGE);
1288 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1289 GPIO_INTERRUPT_EDGE_DUAL);
1290 break;
1291 case IRQ_TYPE_LEVEL_HIGH:
1292 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1293 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1294 GPIO_INTERRUPT_TYPE_LEVEL);
1295 break;
1296 case IRQ_TYPE_LEVEL_LOW:
1297 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1298 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1299 GPIO_INTERRUPT_TYPE_LEVEL);
1300 break;
1301 default:
1302 return -EINVAL;
1303 }
1304
1305 if (type & IRQ_TYPE_LEVEL_MASK)
1306 __irq_set_handler_locked(data->irq, handle_level_irq);
1307 else
1308 __irq_set_handler_locked(data->irq, handle_edge_irq);
1309
1310 return 0;
1311}
1312
1313static void pistachio_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1314{
1315 struct gpio_chip *gc = irq_get_handler_data(irq);
1316 struct pistachio_gpio_bank *bank = gc_to_bank(gc);
1317 struct irq_chip *chip = irq_get_chip(irq);
1318 unsigned long pending;
1319 unsigned int pin;
1320
1321 chained_irq_enter(chip, desc);
1322 pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
1323 gpio_readl(bank, GPIO_INTERRUPT_EN);
1324 for_each_set_bit(pin, &pending, 16)
1325 generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
1326 chained_irq_exit(chip, desc);
1327}
1328
1329#define GPIO_BANK(_bank, _pin_base, _npins) \
1330 { \
1331 .pin_base = _pin_base, \
1332 .npins = _npins, \
1333 .gpio_chip = { \
1334 .label = "GPIO" #_bank, \
1335 .request = pistachio_gpio_request, \
1336 .free = pistachio_gpio_free, \
1337 .get_direction = pistachio_gpio_get_direction, \
1338 .direction_input = pistachio_gpio_direction_input, \
1339 .direction_output = pistachio_gpio_direction_output, \
1340 .get = pistachio_gpio_get, \
1341 .set = pistachio_gpio_set, \
1342 .base = _pin_base, \
1343 .ngpio = _npins, \
1344 }, \
1345 .irq_chip = { \
1346 .name = "GPIO" #_bank, \
1347 .irq_startup = pistachio_gpio_irq_startup, \
1348 .irq_ack = pistachio_gpio_irq_ack, \
1349 .irq_mask = pistachio_gpio_irq_mask, \
1350 .irq_unmask = pistachio_gpio_irq_unmask, \
1351 .irq_set_type = pistachio_gpio_irq_set_type, \
1352 }, \
1353 }
1354
1355static struct pistachio_gpio_bank pistachio_gpio_banks[] = {
1356 GPIO_BANK(0, PISTACHIO_PIN_MFIO(0), 16),
1357 GPIO_BANK(1, PISTACHIO_PIN_MFIO(16), 16),
1358 GPIO_BANK(2, PISTACHIO_PIN_MFIO(32), 16),
1359 GPIO_BANK(3, PISTACHIO_PIN_MFIO(48), 16),
1360 GPIO_BANK(4, PISTACHIO_PIN_MFIO(64), 16),
1361 GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10),
1362};
1363
1364static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
1365{
1366 struct device_node *node = pctl->dev->of_node;
1367 struct pistachio_gpio_bank *bank;
1368 unsigned int i;
1369 int irq, ret = 0;
1370
1371 for (i = 0; i < pctl->nbanks; i++) {
1372 char child_name[sizeof("gpioXX")];
1373 struct device_node *child;
1374
1375 snprintf(child_name, sizeof(child_name), "gpio%d", i);
1376 child = of_get_child_by_name(node, child_name);
1377 if (!child) {
1378 dev_err(pctl->dev, "No node for bank %u\n", i);
1379 ret = -ENODEV;
1380 goto err;
1381 }
1382
1383 if (!of_find_property(child, "gpio-controller", NULL)) {
1384 dev_err(pctl->dev,
1385 "No gpio-controller property for bank %u\n", i);
1386 ret = -ENODEV;
1387 goto err;
1388 }
1389
1390 irq = irq_of_parse_and_map(child, 0);
1391 if (irq < 0) {
1392 dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);
1393 ret = irq;
1394 goto err;
1395 }
1396
1397 bank = &pctl->gpio_banks[i];
1398 bank->pctl = pctl;
1399 bank->base = pctl->base + GPIO_BANK_BASE(i);
1400
1401 bank->gpio_chip.dev = pctl->dev;
1402 bank->gpio_chip.of_node = child;
1403 ret = gpiochip_add(&bank->gpio_chip);
1404 if (ret < 0) {
1405 dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
1406 i, ret);
1407 goto err;
1408 }
1409
1410 ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
1411 0, handle_level_irq, IRQ_TYPE_NONE);
1412 if (ret < 0) {
1413 dev_err(pctl->dev, "Failed to add IRQ chip %u: %d\n",
1414 i, ret);
1415 gpiochip_remove(&bank->gpio_chip);
1416 goto err;
1417 }
1418 gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
1419 irq, pistachio_gpio_irq_handler);
1420
1421 ret = gpiochip_add_pin_range(&bank->gpio_chip,
1422 dev_name(pctl->dev), 0,
1423 bank->pin_base, bank->npins);
1424 if (ret < 0) {
1425 dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",
1426 i, ret);
1427 gpiochip_remove(&bank->gpio_chip);
1428 goto err;
1429 }
1430 }
1431
1432 return 0;
1433err:
1434 for (; i > 0; i--) {
1435 bank = &pctl->gpio_banks[i - 1];
1436 gpiochip_remove(&bank->gpio_chip);
1437 }
1438 return ret;
1439}
1440
1441static const struct of_device_id pistachio_pinctrl_of_match[] = {
1442 { .compatible = "img,pistachio-system-pinctrl", },
1443 { },
1444};
1445
1446static int pistachio_pinctrl_probe(struct platform_device *pdev)
1447{
1448 struct pistachio_pinctrl *pctl;
1449 struct resource *res;
1450 int ret;
1451
1452 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1453 if (!pctl)
1454 return -ENOMEM;
1455 pctl->dev = &pdev->dev;
1456 dev_set_drvdata(&pdev->dev, pctl);
1457
1458 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1459 pctl->base = devm_ioremap_resource(&pdev->dev, res);
1460 if (IS_ERR(pctl->base))
1461 return PTR_ERR(pctl->base);
1462
1463 pctl->pins = pistachio_pins;
1464 pctl->npins = ARRAY_SIZE(pistachio_pins);
1465 pctl->functions = pistachio_functions;
1466 pctl->nfunctions = ARRAY_SIZE(pistachio_functions);
1467 pctl->groups = pistachio_groups;
1468 pctl->ngroups = ARRAY_SIZE(pistachio_groups);
1469 pctl->gpio_banks = pistachio_gpio_banks;
1470 pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
1471
1472 pistachio_pinctrl_desc.pins = pctl->pins;
1473 pistachio_pinctrl_desc.npins = pctl->npins;
1474
1475 pctl->pctldev = pinctrl_register(&pistachio_pinctrl_desc, &pdev->dev,
1476 pctl);
1477 if (IS_ERR(pctl->pctldev)) {
1478 dev_err(&pdev->dev, "Failed to register pinctrl device\n");
1479 return PTR_ERR(pctl->pctldev);
1480 }
1481
1482 ret = pistachio_gpio_register(pctl);
1483 if (ret < 0) {
1484 pinctrl_unregister(pctl->pctldev);
1485 return ret;
1486 }
1487
1488 return 0;
1489}
1490
1491static struct platform_driver pistachio_pinctrl_driver = {
1492 .driver = {
1493 .name = "pistachio-pinctrl",
1494 .of_match_table = pistachio_pinctrl_of_match,
1495 .suppress_bind_attrs = true,
1496 },
1497 .probe = pistachio_pinctrl_probe,
1498};
1499
1500static int __init pistachio_pinctrl_register(void)
1501{
1502 return platform_driver_register(&pistachio_pinctrl_driver);
1503}
1504arch_initcall(pistachio_pinctrl_register);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 13:31:54 -0500