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path: root/drivers/pinctrl/mediatek/pinctrl-mt8173.c
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Diffstat (limited to 'drivers/pinctrl/mediatek/pinctrl-mt8173.c')
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8173.c377
1 files changed, 161 insertions, 216 deletions
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
index 412ea84836a1..d0c811d5f07b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
@@ -18,6 +18,7 @@
18#include <linux/of_device.h> 18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h> 19#include <linux/pinctrl/pinctrl.h>
20#include <linux/regmap.h> 20#include <linux/regmap.h>
21#include <linux/pinctrl/pinconf-generic.h>
21#include <dt-bindings/pinctrl/mt65xx.h> 22#include <dt-bindings/pinctrl/mt65xx.h>
22 23
23#include "pinctrl-mtk-common.h" 24#include "pinctrl-mtk-common.h"
@@ -25,228 +26,172 @@
25 26
26#define DRV_BASE 0xb00 27#define DRV_BASE 0xb00
27 28
28/** 29static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
29 * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting. 30 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
30 * @start: The start pin number of those special pins. 31 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
31 * @end: The end pin number of those special pins. 32 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
32 * @offset: The offset of special setting register. 33 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
33 * @bit: The bit of special setting register. 34 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
34 */ 35 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
35struct mtk_pin_ies_smt_set { 36
36 unsigned int start; 37 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
37 unsigned int end; 38 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
38 unsigned int offset; 39 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
39 unsigned char bit; 40 MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */
41 MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */
42 MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */
43 MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */
44 MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */
45 MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */
46 MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */
47 MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */
48 MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */
49
50 MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */
51 MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
52 MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
53 MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
54 MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
55 MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */
56
57 MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
58 MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
59 MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
60 MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
61 MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */
62 MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */
63
64 MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
65 MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
66 MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
67 MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
68 MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */
69 MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
40}; 70};
41 71
42#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \ 72static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
43 { \
44 .start = _start, \
45 .end = _end, \
46 .bit = _bit, \
47 .offset = _offset, \
48 }
49
50/**
51 * struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting.
52 * @pin: The pin number.
53 * @offset: The offset of special pull up/down setting register.
54 * @pupd_bit: The pull up/down bit in this register.
55 * @r0_bit: The r0 bit of pull resistor.
56 * @r1_bit: The r1 bit of pull resistor.
57 */
58struct mtk_pin_spec_pupd_set {
59 unsigned int pin;
60 unsigned int offset;
61 unsigned char pupd_bit;
62 unsigned char r1_bit;
63 unsigned char r0_bit;
64};
65
66#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \
67 { \
68 .pin = _pin, \
69 .offset = _offset, \
70 .pupd_bit = _pupd, \
71 .r1_bit = _r1, \
72 .r0_bit = _r0, \
73 }
74
75static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = {
76 MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */
77 MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */
78 MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */
79 MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */
80 MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */
81 MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */
82
83 MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */
84 MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */
85 MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */
86 MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */
87 MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */
88 MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */
89 MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */
90 MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */
91 MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */
92 MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */
93 MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */
94 MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */
95
96 MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */
97 MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
98 MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
99 MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
100 MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
101 MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */
102
103 MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
104 MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
105 MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
106 MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
107 MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */
108 MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */
109
110 MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
111 MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
112 MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
113 MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
114 MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */
115 MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
116};
117
118static int spec_pull_set(struct regmap *regmap, unsigned int pin,
119 unsigned char align, bool isup, unsigned int r1r0) 73 unsigned char align, bool isup, unsigned int r1r0)
120{ 74{
121 unsigned int i; 75 return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
122 unsigned int reg_pupd, reg_set, reg_rst; 76 ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
123 unsigned int bit_pupd, bit_r0, bit_r1;
124 const struct mtk_pin_spec_pupd_set *spec_pupd_pin;
125 bool find = false;
126
127 for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) {
128 if (pin == mt8173_spec_pupd[i].pin) {
129 find = true;
130 break;
131 }
132 }
133
134 if (!find)
135 return -EINVAL;
136
137 spec_pupd_pin = mt8173_spec_pupd + i;
138 reg_set = spec_pupd_pin->offset + align;
139 reg_rst = spec_pupd_pin->offset + (align << 1);
140
141 if (isup)
142 reg_pupd = reg_rst;
143 else
144 reg_pupd = reg_set;
145
146 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
147 regmap_write(regmap, reg_pupd, bit_pupd);
148
149 bit_r0 = BIT(spec_pupd_pin->r0_bit);
150 bit_r1 = BIT(spec_pupd_pin->r1_bit);
151
152 switch (r1r0) {
153 case MTK_PUPD_SET_R1R0_00:
154 regmap_write(regmap, reg_rst, bit_r0);
155 regmap_write(regmap, reg_rst, bit_r1);
156 break;
157 case MTK_PUPD_SET_R1R0_01:
158 regmap_write(regmap, reg_set, bit_r0);
159 regmap_write(regmap, reg_rst, bit_r1);
160 break;
161 case MTK_PUPD_SET_R1R0_10:
162 regmap_write(regmap, reg_rst, bit_r0);
163 regmap_write(regmap, reg_set, bit_r1);
164 break;
165 case MTK_PUPD_SET_R1R0_11:
166 regmap_write(regmap, reg_set, bit_r0);
167 regmap_write(regmap, reg_set, bit_r1);
168 break;
169 default:
170 return -EINVAL;
171 }
172
173 return 0;
174} 77}
175 78
176static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = { 79static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
177 MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1), 80 MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
178 MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2), 81 MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
179 MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10), 82 MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
180 MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10), 83 MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
181 MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0), 84 MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
182 MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2), 85 MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
183 MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3), 86 MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
184 MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3), 87 MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13),
185 MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4), 88 MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13),
186 MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5), 89 MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13),
187 MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6), 90 MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13),
188 MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7), 91 MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
189 MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9), 92 MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
190 MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0), 93 MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
191 MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11), 94 MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
192 MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12), 95 MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
193 MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13), 96 MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
194 MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13), 97 MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
195 MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13), 98 MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
196 MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13), 99 MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
197 MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13), 100 MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
198 MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14), 101 MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
199 MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13), 102 MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
200 MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13), 103 MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
201 MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13), 104 MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
202 MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15), 105 MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
203 MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0), 106 MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
204 MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1), 107 MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
205 MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2), 108 MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
206 MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13), 109 MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
207 MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14), 110 MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
208 MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15), 111 MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
209 MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13), 112 MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
210 MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13), 113 MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
211 MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13), 114 MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
212 MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4), 115 MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
213 MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1), 116 MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
214 MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2), 117 MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
215 MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5), 118 MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
216 MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6), 119 MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
217 MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7), 120 MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
218 MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0), 121 MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
219 MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8), 122 MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
220 MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9), 123 MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
221 MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8), 124 MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
222 MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8) 125 MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
126 MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
127 MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
128 MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
129 MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
223}; 130};
224 131
225static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin, 132static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
226 unsigned char align, int value) 133 MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
227{ 134 MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
228 unsigned int i, reg_addr, bit; 135 MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
229 bool find = false; 136 MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
230 137 MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
231 for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) { 138 MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
232 if (pin >= mt8173_ies_smt_set[i].start && 139 MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
233 pin <= mt8173_ies_smt_set[i].end) { 140 MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14),
234 find = true; 141 MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14),
235 break; 142 MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14),
236 } 143 MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14),
237 } 144 MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
238 145 MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
239 if (!find) 146 MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
240 return -EINVAL; 147 MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
241 148 MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
242 if (value) 149 MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
243 reg_addr = mt8173_ies_smt_set[i].offset + align; 150 MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
244 else 151 MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
245 reg_addr = mt8173_ies_smt_set[i].offset + (align << 1); 152 MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
153 MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
154 MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
155 MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
156 MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
157 MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
158 MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
159 MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
160 MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
161 MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
162 MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
163 MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
164 MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
165 MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
166 MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
167 MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
168 MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
169 MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
170 MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
171 MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
172 MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4),
173 MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
174 MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
175 MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
176 MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
177 MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
178 MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
179 MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
180 MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
181 MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
182 MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
183};
246 184
247 bit = BIT(mt8173_ies_smt_set[i].bit); 185static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
248 regmap_write(regmap, reg_addr, bit); 186 unsigned char align, int value, enum pin_config_param arg)
249 return 0; 187{
188 if (arg == PIN_CONFIG_INPUT_ENABLE)
189 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
190 ARRAY_SIZE(mt8173_ies_set), pin, align, value);
191 else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
192 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
193 ARRAY_SIZE(mt8173_smt_set), pin, align, value);
194 return -EINVAL;
250} 195}
251 196
252static const struct mtk_drv_group_desc mt8173_drv_grp[] = { 197static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
@@ -382,8 +327,8 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
382 .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), 327 .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
383 .pin_drv_grp = mt8173_pin_drv, 328 .pin_drv_grp = mt8173_pin_drv,
384 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), 329 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
385 .spec_pull_set = spec_pull_set, 330 .spec_pull_set = mt8173_spec_pull_set,
386 .spec_ies_smt_set = spec_ies_smt_set, 331 .spec_ies_smt_set = mt8173_ies_smt_set,
387 .dir_offset = 0x0000, 332 .dir_offset = 0x0000,
388 .pullen_offset = 0x0100, 333 .pullen_offset = 0x0100,
389 .pullsel_offset = 0x0200, 334 .pullsel_offset = 0x0200,
@@ -424,7 +369,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
424 369
425static int mt8173_pinctrl_probe(struct platform_device *pdev) 370static int mt8173_pinctrl_probe(struct platform_device *pdev)
426{ 371{
427 return mtk_pctrl_init(pdev, &mt8173_pinctrl_data); 372 return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL);
428} 373}
429 374
430static const struct of_device_id mt8173_pctrl_match[] = { 375static const struct of_device_id mt8173_pctrl_match[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-10 04:53:00 -0500