1 files changed, 13 insertions, 4 deletions

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index d29c020da082..81e2157a7cfb 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -1,5 +1,5 @@
 /*
- * Synopsys Designware PCIe host controller driver
+ * Synopsys DesignWare PCIe host controller driver
  *
  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
@@ -71,9 +71,9 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
                 while ((pos = find_next_bit((unsigned long *) &val, 32,
                                             pos)) != 32) {
                         irq = irq_find_mapping(pp->irq_domain, i * 32 + pos);
+                        generic_handle_irq(irq);
                         dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12,
                                             4, 1 << pos);
-                        generic_handle_irq(irq);
                         pos++;
                 }
         }
@@ -401,8 +401,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
                 }
         }
 
-        if (pp->ops->host_init)
-                pp->ops->host_init(pp);
+        if (pp->ops->host_init) {
+                ret = pp->ops->host_init(pp);
+                if (ret)
+                        goto error;
+        }
 
         pp->root_bus_nr = pp->busn->start;
 
@@ -594,10 +597,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
         dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
 
         /* setup interrupt pins */
+        dw_pcie_dbi_ro_wr_en(pci);
         val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
         val &= 0xffff00ff;
         val |= 0x00000100;
         dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
+        dw_pcie_dbi_ro_wr_dis(pci);
 
         /* setup bus numbers */
         val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -634,8 +639,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 
         dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
+        /* Enable write permission for the DBI read-only register */
+        dw_pcie_dbi_ro_wr_en(pci);
         /* program correct class for RC */
         dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+        /* Better disable write permission right after the update */
+        dw_pcie_dbi_ro_wr_dis(pci);
 
         dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
         val |= PORT_LOGIC_SPEED_CHANGE;