diff options
Diffstat (limited to 'drivers/net/wireless/b43/phy_ht.h')
| -rw-r--r-- | drivers/net/wireless/b43/phy_ht.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/net/wireless/b43/phy_ht.h b/drivers/net/wireless/b43/phy_ht.h index 7ad7affc8df0..6544c4293b34 100644 --- a/drivers/net/wireless/b43/phy_ht.h +++ b/drivers/net/wireless/b43/phy_ht.h | |||
| @@ -4,7 +4,11 @@ | |||
| 4 | #include "phy_common.h" | 4 | #include "phy_common.h" |
| 5 | 5 | ||
| 6 | 6 | ||
| 7 | #define B43_PHY_HT_BBCFG 0x001 /* BB config */ | ||
| 8 | #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ | ||
| 9 | #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ | ||
| 7 | #define B43_PHY_HT_BANDCTL 0x009 /* Band control */ | 10 | #define B43_PHY_HT_BANDCTL 0x009 /* Band control */ |
| 11 | #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ | ||
| 8 | #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ | 12 | #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ |
| 9 | #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ | 13 | #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ |
| 10 | #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ | 14 | #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ |
| @@ -15,6 +19,21 @@ | |||
| 15 | #define B43_PHY_HT_BW5 0x1D2 | 19 | #define B43_PHY_HT_BW5 0x1D2 |
| 16 | #define B43_PHY_HT_BW6 0x1D3 | 20 | #define B43_PHY_HT_BW6 0x1D3 |
| 17 | 21 | ||
| 22 | #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) | ||
| 23 | #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) | ||
| 24 | #define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E) | ||
| 25 | |||
| 26 | #define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000) | ||
| 27 | #define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003) | ||
| 28 | #define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ | ||
| 29 | #define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ | ||
| 30 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */ | ||
| 31 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */ | ||
| 32 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */ | ||
| 33 | #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ | ||
| 34 | #define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004) | ||
| 35 | /* Values for the status are the same as for the trigger */ | ||
| 36 | |||
| 18 | #define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010) | 37 | #define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010) |
| 19 | 38 | ||
| 20 | #define B43_PHY_HT_AFE_CTL1 B43_PHY_EXTG(0x110) | 39 | #define B43_PHY_HT_AFE_CTL1 B43_PHY_EXTG(0x110) |
