diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 3aed729e4d5e..8be4b1453394 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -222,31 +222,28 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah) | |||
222 | { | 222 | { |
223 | u32 val; | 223 | u32 val; |
224 | 224 | ||
225 | if (ah->get_mac_revision) | ||
226 | ah->hw_version.macRev = ah->get_mac_revision(); | ||
227 | |||
225 | switch (ah->hw_version.devid) { | 228 | switch (ah->hw_version.devid) { |
226 | case AR5416_AR9100_DEVID: | 229 | case AR5416_AR9100_DEVID: |
227 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; | 230 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; |
228 | break; | 231 | break; |
229 | case AR9300_DEVID_AR9330: | 232 | case AR9300_DEVID_AR9330: |
230 | ah->hw_version.macVersion = AR_SREV_VERSION_9330; | 233 | ah->hw_version.macVersion = AR_SREV_VERSION_9330; |
231 | if (ah->get_mac_revision) { | 234 | if (!ah->get_mac_revision) { |
232 | ah->hw_version.macRev = ah->get_mac_revision(); | ||
233 | } else { | ||
234 | val = REG_READ(ah, AR_SREV); | 235 | val = REG_READ(ah, AR_SREV); |
235 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | 236 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); |
236 | } | 237 | } |
237 | return; | 238 | return; |
238 | case AR9300_DEVID_AR9340: | 239 | case AR9300_DEVID_AR9340: |
239 | ah->hw_version.macVersion = AR_SREV_VERSION_9340; | 240 | ah->hw_version.macVersion = AR_SREV_VERSION_9340; |
240 | val = REG_READ(ah, AR_SREV); | ||
241 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | ||
242 | return; | 241 | return; |
243 | case AR9300_DEVID_QCA955X: | 242 | case AR9300_DEVID_QCA955X: |
244 | ah->hw_version.macVersion = AR_SREV_VERSION_9550; | 243 | ah->hw_version.macVersion = AR_SREV_VERSION_9550; |
245 | return; | 244 | return; |
246 | case AR9300_DEVID_AR953X: | 245 | case AR9300_DEVID_AR953X: |
247 | ah->hw_version.macVersion = AR_SREV_VERSION_9531; | 246 | ah->hw_version.macVersion = AR_SREV_VERSION_9531; |
248 | if (ah->get_mac_revision) | ||
249 | ah->hw_version.macRev = ah->get_mac_revision(); | ||
250 | return; | 247 | return; |
251 | } | 248 | } |
252 | 249 | ||
@@ -704,6 +701,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, | |||
704 | { | 701 | { |
705 | u32 pll; | 702 | u32 pll; |
706 | 703 | ||
704 | pll = ath9k_hw_compute_pll_control(ah, chan); | ||
705 | |||
707 | if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { | 706 | if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
708 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ | 707 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ |
709 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | 708 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
@@ -754,7 +753,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, | |||
754 | REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, | 753 | REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, |
755 | AR_CH0_DPLL3_PHASE_SHIFT, 0x1); | 754 | AR_CH0_DPLL3_PHASE_SHIFT, 0x1); |
756 | 755 | ||
757 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); | 756 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, |
757 | pll | AR_RTC_9300_PLL_BYPASS); | ||
758 | udelay(1000); | 758 | udelay(1000); |
759 | 759 | ||
760 | /* program refdiv, nint, frac to RTC register */ | 760 | /* program refdiv, nint, frac to RTC register */ |
@@ -770,7 +770,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, | |||
770 | } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { | 770 | } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { |
771 | u32 regval, pll2_divint, pll2_divfrac, refdiv; | 771 | u32 regval, pll2_divint, pll2_divfrac, refdiv; |
772 | 772 | ||
773 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); | 773 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, |
774 | pll | AR_RTC_9300_SOC_PLL_BYPASS); | ||
774 | udelay(1000); | 775 | udelay(1000); |
775 | 776 | ||
776 | REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); | 777 | REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); |
@@ -843,7 +844,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, | |||
843 | udelay(1000); | 844 | udelay(1000); |
844 | } | 845 | } |
845 | 846 | ||
846 | pll = ath9k_hw_compute_pll_control(ah, chan); | ||
847 | if (AR_SREV_9565(ah)) | 847 | if (AR_SREV_9565(ah)) |
848 | pll |= 0x40000; | 848 | pll |= 0x40000; |
849 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); | 849 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
@@ -1192,9 +1192,12 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) | |||
1192 | 1192 | ||
1193 | switch (opmode) { | 1193 | switch (opmode) { |
1194 | case NL80211_IFTYPE_ADHOC: | 1194 | case NL80211_IFTYPE_ADHOC: |
1195 | set |= AR_STA_ID1_ADHOC; | 1195 | if (!AR_SREV_9340_13(ah)) { |
1196 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | 1196 | set |= AR_STA_ID1_ADHOC; |
1197 | break; | 1197 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
1198 | break; | ||
1199 | } | ||
1200 | /* fall through */ | ||
1198 | case NL80211_IFTYPE_MESH_POINT: | 1201 | case NL80211_IFTYPE_MESH_POINT: |
1199 | case NL80211_IFTYPE_AP: | 1202 | case NL80211_IFTYPE_AP: |
1200 | set |= AR_STA_ID1_STA_AP; | 1203 | set |= AR_STA_ID1_STA_AP; |